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//*****************************************************************************
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// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: rd_data_gen.v
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// /___/ /\ Date Last Modified:
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// \ \ / \ Date Created:
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// \___\/\___\
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//
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//Device: Spartan6
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//Design Name: DDR/DDR2/DDR3/LPDDR
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//Purpose: This module has all the timing control for generating "compare data"
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// to compare the read data from memory.
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1ps/1ps
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module rd_data_gen #
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(
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parameter TCQ = 100,
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parameter FAMILY = "SPARTAN6", // "SPARTAN6", "VIRTEX6"
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parameter MEM_BURST_LEN = 8,
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parameter ADDR_WIDTH = 32,
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parameter BL_WIDTH = 6,
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parameter DWIDTH = 32,
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parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
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parameter NUM_DQ_PINS = 8,
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parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
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parameter COLUMN_WIDTH = 10
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)
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(
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input clk_i, //
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input [4:0] rst_i,
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input [31:0] prbs_fseed_i,
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input [3:0] data_mode_i, // "00" = bram;
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output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
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// And then it should reasserted when
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// it is generating the last_word.
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input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
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output last_word_o,
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// input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern.
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input [DWIDTH-1:0] fixed_data_i,
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input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
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input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data
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output user_bl_cnt_is_1_o,
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input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen in sp6
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// connect from mcb_rd_empty when used as rd_data_gen in sp6
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// connect from rd_data_valid in v6
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// When both data_rdy and data_valid is asserted, the ouput data is valid.
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output reg data_valid_o, // connect to wr_en or rd_en and is asserted whenever the
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// pattern is available.
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output [DWIDTH-1:0] data_o, // generated data pattern
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input rd_mdata_en
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);
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//
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wire [31:0] prbs_data;
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reg cmd_start;
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reg [31:0] adata;
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reg [31:0] hdata;
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reg [31:0] ndata;
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reg [31:0] w1data;
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reg [NUM_DQ_PINS*4-1:0] v6_w1data;
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reg [31:0] w0data;
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reg [DWIDTH-1:0] data;
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reg cmd_rdy;
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reg data_valid;
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reg [6:0]user_burst_cnt;
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reg data_rdy_r1,data_rdy_r2;
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reg next_count_is_one;
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reg cmd_valid_r1;
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reg [31:0] w3data;
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assign data_port_fifo_rdy = data_rdy_i;
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//assign cmd_start = cmd_valid_i & cmd_rdy ;
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always @ (posedge clk_i)
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begin
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data_rdy_r1 <= #TCQ data_rdy_i;
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data_rdy_r2 <= #TCQ data_rdy_r1;
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cmd_valid_r1 <= #TCQ cmd_valid_i;
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end
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always @ (posedge clk_i)
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begin
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if (user_burst_cnt == 2 && data_rdy_i)
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next_count_is_one <= #TCQ 1'b1;
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else
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next_count_is_one <= #TCQ 1'b0;
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end
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reg user_bl_cnt_is_1;
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assign user_bl_cnt_is_1_o = user_bl_cnt_is_1;
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always @ (posedge clk_i)
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begin
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if ((user_burst_cnt == 2 && data_port_fifo_rdy && FAMILY == "SPARTAN6")
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|| (user_burst_cnt == 2 && data_port_fifo_rdy && FAMILY == "VIRTEX6")
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)
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user_bl_cnt_is_1 <= #TCQ 1'b1;
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else
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user_bl_cnt_is_1 <= #TCQ 1'b0;
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end
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reg cmd_start_b;
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always @(cmd_valid_i,cmd_valid_r1,cmd_rdy,user_bl_cnt_is_1,rd_mdata_en)
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begin
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if (FAMILY == "SPARTAN6") begin
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cmd_start = cmd_valid_i & cmd_rdy ;
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cmd_start_b = cmd_valid_i & cmd_rdy ;
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end
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else if (MEM_BURST_LEN == 4 && FAMILY == "VIRTEX6") begin
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cmd_start = rd_mdata_en; // need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
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cmd_start_b = rd_mdata_en; // need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
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end
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else if (MEM_BURST_LEN == 8 && FAMILY == "VIRTEX6") begin
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cmd_start = (~cmd_valid_r1 & cmd_valid_i) | user_bl_cnt_is_1; // need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
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cmd_start_b = (~cmd_valid_r1 & cmd_valid_i) | user_bl_cnt_is_1; // need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
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end
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end
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// counter to count user burst length
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always @( posedge clk_i)
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begin
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if ( rst_i[0] )
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user_burst_cnt <= #TCQ 'd0;
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else if(cmd_start) begin
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if (bl_i == 6'b000000)
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user_burst_cnt <= #TCQ 7'b1000000;
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else
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user_burst_cnt <= #TCQ bl_i;
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end
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else if(data_port_fifo_rdy)
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if (user_burst_cnt != 6'd0)
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user_burst_cnt <= #TCQ user_burst_cnt - 1'b1;
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else
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user_burst_cnt <= #TCQ 'd0;
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end
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reg u_bcount_2;
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always @ (posedge clk_i)
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begin
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if ((user_burst_cnt == 2 && data_rdy_i )|| (cmd_start && bl_i == 1))
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u_bcount_2 <= #TCQ 1'b1;
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else if (last_word_o)
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u_bcount_2 <= #TCQ 1'b0;
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end
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assign last_word_o = u_bcount_2 & data_rdy_i;
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// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
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// is assert and reassert during the last data
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//data_valid_o logic
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assign cmd_rdy_o = cmd_rdy;
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always @( posedge clk_i)
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begin
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if ( rst_i[0] )
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cmd_rdy <= #TCQ 1'b1;
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else if (cmd_start)
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cmd_rdy <= #TCQ 1'b0;
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else if ((data_port_fifo_rdy && user_burst_cnt == 1))
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cmd_rdy <= #TCQ 1'b1;
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end
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always @ (posedge clk_i)
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begin
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if (rst_i[0])
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data_valid <= #TCQ 'd0;
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else if (user_burst_cnt == 6'd1 && data_port_fifo_rdy)
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data_valid <= #TCQ 1'b0;
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else if(( user_burst_cnt >= 6'd1) || cmd_start)
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data_valid <= #TCQ 1'b1;
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end
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always @ (data_valid, data_port_fifo_rdy)
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if (FAMILY == "SPARTAN6")
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data_valid_o = data_valid;
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else
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data_valid_o = data_port_fifo_rdy;
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generate
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if (FAMILY == "SPARTAN6") begin : SP6_DGEN
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sp6_data_gen #
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(
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.TCQ (TCQ),
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.ADDR_WIDTH (32 ),
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.BL_WIDTH (BL_WIDTH ),
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.DWIDTH (DWIDTH ),
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.DATA_PATTERN (DATA_PATTERN ),
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.NUM_DQ_PINS (NUM_DQ_PINS ),
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.COLUMN_WIDTH (COLUMN_WIDTH)
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)
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sp6_data_gen
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(
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.clk_i (clk_i ),
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.rst_i (rst_i[1] ),
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.data_rdy_i (data_rdy_i ),
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.prbs_fseed_i (prbs_fseed_i),
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.data_mode_i (data_mode_i ),
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.cmd_startA (cmd_start ),
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.cmd_startB (cmd_start ),
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.cmd_startC (cmd_start ),
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.cmd_startD (cmd_start ),
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.cmd_startE (cmd_start ),
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.fixed_data_i (fixed_data_i),
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.addr_i (addr_i ),
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.user_burst_cnt (user_burst_cnt),
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.fifo_rdy_i (data_port_fifo_rdy ),
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.data_o (data_o )
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);
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end
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endgenerate
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generate
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if (FAMILY == "VIRTEX6") begin : V6_DGEN
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v6_data_gen #
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(
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.TCQ (TCQ),
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.ADDR_WIDTH (32 ),
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.BL_WIDTH (BL_WIDTH ),
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.MEM_BURST_LEN (MEM_BURST_LEN),
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.DWIDTH (DWIDTH ),
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.DATA_PATTERN (DATA_PATTERN ),
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.NUM_DQ_PINS (NUM_DQ_PINS ),
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.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
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.COLUMN_WIDTH (COLUMN_WIDTH)
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)
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v6_data_gen
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(
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.clk_i (clk_i ),
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.rst_i (rst_i[1] ),
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.data_rdy_i (data_rdy_i ),
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.prbs_fseed_i (prbs_fseed_i),
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.data_mode_i (data_mode_i ),
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.cmd_startA (cmd_start ),
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.cmd_startB (cmd_start ),
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.cmd_startC (cmd_start ),
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.cmd_startD (cmd_start ),
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.cmd_startE (cmd_start ),
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.m_addr_i (addr_i),//(m_addr_i ),
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.fixed_data_i (fixed_data_i),
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.addr_i (addr_i ),
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.user_burst_cnt (user_burst_cnt),
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.fifo_rdy_i (data_port_fifo_rdy ),
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.data_o (data_o )
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);
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end
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endgenerate
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endmodule
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