1 |
2 |
ZTEX |
2014.4:
|
2 |
|
|
* Version 2.3
|
3 |
|
|
* Updated maximum frequencies and controller rates as per specifications listed in 7 Series and Zync DC and Switching Characteristics Datasheets
|
4 |
|
|
* DDR3 write calibration changes
|
5 |
|
|
|
6 |
|
|
2014.3:
|
7 |
|
|
* Version 2.2
|
8 |
|
|
* DDR3 SDRAM, DDR2 SDRAM, RLDRAM II, LPDDR2 SDRAM, QDRIIPLUS SRAM max supported frequencies updated. See (Xilinx Answer 61853) for details."
|
9 |
|
|
* Resolved (Xilinx Answer 61744) "MIG 7 Series DDR3 - ECC Multiple errors are seen in hardware when targeting Vivado 2014.2. Errors were not seen in previous versions."
|
10 |
|
|
* Resolved (Xilinx Answer 61521) "MIG 7 Series - Cannot generate data width greater than 8-bits for CPG325 packages"
|
11 |
|
|
* Resolved (Xilinx Answer 60480) "MIG 7 Series - Receiving ERROR [Drc 23-20] when CLOCK_DEDICATED_ROUTE set to BACKBONE but backbone resources are not used"
|
12 |
|
|
* Resolved (Xilinx Answer 60051) "MIG 7 Series DDR3 - VCS simulations fail with unresolved modules"
|
13 |
|
|
|
14 |
|
|
2014.2:
|
15 |
|
|
* Version 2.1
|
16 |
|
|
* DDR3 clocking and read path calibration updates. Refer to Answer Record 60470 for details
|
17 |
|
|
* Addition of Artix-7Q(xq7a50t-cs325,xq7a50t-fg484) and XAZynq (xa7z030-fbg484) devices
|
18 |
|
|
|
19 |
|
|
2014.1:
|
20 |
|
|
* Version 2.0 (Rev. 3)
|
21 |
|
|
* Extended IES and VCS support to Multi-Controller and Multi-Interface designs
|
22 |
|
|
|
23 |
|
|
2013.4:
|
24 |
|
|
* Version 2.0 (Rev. 2)
|
25 |
|
|
* Added OOC support
|
26 |
|
|
* Added support for IES and VCS Simulators
|
27 |
|
|
|
28 |
|
|
2013.3:
|
29 |
|
|
* Version 2.0 (Rev. 1)
|
30 |
|
|
* Added support for ILA 3.0 and VIO 3.0
|
31 |
|
|
* Resolved controller hang issues on read-modify-write commands (See Xilinx Answer 54710)
|
32 |
|
|
* Resolved Clock Driver Enable settings for RC1 on RDIMM interfaces (See Xilinx Answer 57279)
|
33 |
|
|
* Updated Chipscope debug signals for OCLKDELAY calibration (See Xilinx Answer 54918)
|
34 |
|
|
* Resolved timing failures with larger SSI devices (See Xilinx Answer 56385)
|
35 |
|
|
* Added AXI addressing support over 32 bits for DDR2 and DDR3
|
36 |
|
|
* Corrected Chip Select width for single rank RDIMM devices (See Xilinx Answer 57436)
|
37 |
|
|
|
38 |
|
|
2013.2:
|
39 |
|
|
* Version 2.0
|
40 |
|
|
* 2013.2 software support
|
41 |
|
|
* Added support for ILA 2.0 and VIO 2.0
|
42 |
|
|
|
43 |
|
|
2013.1:
|
44 |
|
|
* Version 1.9.a
|
45 |
|
|
* 2013.1 software support
|
46 |
|
|
* Questa SIM 10.1b Support
|
47 |
|
|
* Synplify Pro supported version G-2012.09-SP1
|
48 |
|
|
* Support of LPDDR2 SDRAM Verilog designs
|
49 |
|
|
* System Reset Pin Polarity selection
|
50 |
|
|
* Additional clocks selection for AXI interface designs
|
51 |
|
|
|
52 |
|
|
(c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
|
53 |
|
|
|
54 |
|
|
This file contains confidential and proprietary information
|
55 |
|
|
of Xilinx, Inc. and is protected under U.S. and
|
56 |
|
|
international copyright and other intellectual property
|
57 |
|
|
laws.
|
58 |
|
|
|
59 |
|
|
DISCLAIMER
|
60 |
|
|
This disclaimer is not a license and does not grant any
|
61 |
|
|
rights to the materials distributed herewith. Except as
|
62 |
|
|
otherwise provided in a valid license issued to you by
|
63 |
|
|
Xilinx, and to the maximum extent permitted by applicable
|
64 |
|
|
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
65 |
|
|
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
66 |
|
|
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
67 |
|
|
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
68 |
|
|
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
69 |
|
|
(2) Xilinx shall not be liable (whether in contract or tort,
|
70 |
|
|
including negligence, or under any other theory of
|
71 |
|
|
liability) for any loss or damage of any kind or nature
|
72 |
|
|
related to, arising under or in connection with these
|
73 |
|
|
materials, including for any direct, or any indirect,
|
74 |
|
|
special, incidental, or consequential loss or damage
|
75 |
|
|
(including loss of data, profits, goodwill, or any type of
|
76 |
|
|
loss or damage suffered as a result of any action brought
|
77 |
|
|
by a third party) even if such damage or loss was
|
78 |
|
|
reasonably foreseeable or Xilinx had been advised of the
|
79 |
|
|
possibility of the same.
|
80 |
|
|
|
81 |
|
|
CRITICAL APPLICATIONS
|
82 |
|
|
Xilinx products are not designed or intended to be fail-
|
83 |
|
|
safe, or for use in any application requiring fail-safe
|
84 |
|
|
performance, such as life-support or safety devices or
|
85 |
|
|
systems, Class III medical devices, nuclear facilities,
|
86 |
|
|
applications related to the deployment of airbags, or any
|
87 |
|
|
other applications that could lead to death, personal
|
88 |
|
|
injury, or severe property or environmental damage
|
89 |
|
|
(individually and collectively, "Critical
|
90 |
|
|
Applications"). Customer assumes the sole risk and
|
91 |
|
|
liability of any use of Xilinx products in Critical
|
92 |
|
|
Applications, subject only to applicable laws and
|
93 |
|
|
regulations governing limitations on product liability.
|
94 |
|
|
|
95 |
|
|
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
96 |
|
|
PART OF THIS FILE AT ALL TIMES.
|