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//*****************************************************************************
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// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 2.3
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// \ \ Application : MIG
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// / / Filename : mig_7series_0_mig.v
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// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
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// \ \ / \ Date Created : Tue Sept 21 2010
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// \___\/\___\
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//
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// Device : 7 Series
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// Design Name : DDR3 SDRAM
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// Purpose :
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// Top-level module. This module can be instantiated in the
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// system and interconnect as shown in user design wrapper file (user top module).
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// In addition to the memory controller, the module instantiates:
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// 1. Clock generation/distribution, reset logic
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// 2. IDELAY control block
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// 3. Debug logic
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// Reference :
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// Revision History :
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//*****************************************************************************
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`timescale 1ps/1ps
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module mig_7series_0_mig #
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(
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//***************************************************************************
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// The following parameters refer to width of various ports
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//***************************************************************************
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parameter BANK_WIDTH = 3,
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// # of memory Bank Address bits.
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parameter CK_WIDTH = 1,
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// # of CK/CK# outputs to memory.
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parameter COL_WIDTH = 10,
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// # of memory Column Address bits.
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parameter CS_WIDTH = 1,
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// # of unique CS outputs to memory.
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parameter nCS_PER_RANK = 1,
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// # of unique CS outputs per rank for phy
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parameter CKE_WIDTH = 1,
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// # of CKE outputs to memory.
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parameter DATA_BUF_ADDR_WIDTH = 5,
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parameter DQ_CNT_WIDTH = 4,
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// = ceil(log2(DQ_WIDTH))
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parameter DQ_PER_DM = 8,
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parameter DM_WIDTH = 2,
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// # of DM (data mask)
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parameter DQ_WIDTH = 16,
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// # of DQ (data)
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parameter DQS_WIDTH = 2,
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parameter DQS_CNT_WIDTH = 1,
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// = ceil(log2(DQS_WIDTH))
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parameter DRAM_WIDTH = 8,
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// # of DQ per DQS
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parameter ECC = "OFF",
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parameter DATA_WIDTH = 16,
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parameter ECC_TEST = "OFF",
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parameter PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH,
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parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
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//Possible Parameters
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//1.BANK_ROW_COLUMN : Address mapping is
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// in form of Bank Row Column.
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//2.ROW_BANK_COLUMN : Address mapping is
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// in the form of Row Bank Column.
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//3.TG_TEST : Scrambles Address bits
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// for distributed Addressing.
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parameter nBANK_MACHS = 4,
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parameter RANKS = 1,
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// # of Ranks.
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parameter ODT_WIDTH = 1,
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// # of ODT outputs to memory.
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parameter ROW_WIDTH = 14,
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// # of memory Row Address bits.
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parameter ADDR_WIDTH = 28,
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// # = RANK_WIDTH + BANK_WIDTH
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// + ROW_WIDTH + COL_WIDTH;
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// Chip Select is always tied to low for
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// single rank devices
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parameter USE_CS_PORT = 0,
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// # = 1, When Chip Select (CS#) output is enabled
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// = 0, When Chip Select (CS#) output is disabled
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// If CS_N disabled, user must connect
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// DRAM CS_N input(s) to ground
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parameter USE_DM_PORT = 1,
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// # = 1, When Data Mask option is enabled
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// = 0, When Data Mask option is disbaled
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// When Data Mask option is disabled in
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// MIG Controller Options page, the logic
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// related to Data Mask should not get
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// synthesized
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parameter USE_ODT_PORT = 1,
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// # = 1, When ODT output is enabled
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// = 0, When ODT output is disabled
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// Parameter configuration for Dynamic ODT support:
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// USE_ODT_PORT = 0, RTT_NOM = "DISABLED", RTT_WR = "60/120".
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// This configuration allows to save ODT pin mapping from FPGA.
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// The user can tie the ODT input of DRAM to HIGH.
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parameter IS_CLK_SHARED = "FALSE",
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// # = "true" when clock is shared
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// = "false" when clock is not shared
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parameter PHY_CONTROL_MASTER_BANK = 0,
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// The bank index where master PHY_CONTROL resides,
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// equal to the PLL residing bank
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parameter MEM_DENSITY = "2Gb",
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// Indicates the density of the Memory part
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// Added for the sake of Vivado simulations
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parameter MEM_SPEEDGRADE = "125",
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// Indicates the Speed grade of Memory Part
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// Added for the sake of Vivado simulations
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parameter MEM_DEVICE_WIDTH = 16,
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// Indicates the device width of the Memory Part
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// Added for the sake of Vivado simulations
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//***************************************************************************
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// The following parameters are mode register settings
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//***************************************************************************
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parameter AL = "0",
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// DDR3 SDRAM:
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// Additive Latency (Mode Register 1).
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// # = "0", "CL-1", "CL-2".
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// DDR2 SDRAM:
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// Additive Latency (Extended Mode Register).
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parameter nAL = 0,
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// # Additive Latency in number of clock
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// cycles.
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parameter BURST_MODE = "8",
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// DDR3 SDRAM:
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// Burst Length (Mode Register 0).
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// # = "8", "4", "OTF".
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// DDR2 SDRAM:
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// Burst Length (Mode Register).
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// # = "8", "4".
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parameter BURST_TYPE = "SEQ",
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// DDR3 SDRAM: Burst Type (Mode Register 0).
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// DDR2 SDRAM: Burst Type (Mode Register).
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// # = "SEQ" - (Sequential),
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// = "INT" - (Interleaved).
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parameter CL = 6,
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// in number of clock cycles
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// DDR3 SDRAM: CAS Latency (Mode Register 0).
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// DDR2 SDRAM: CAS Latency (Mode Register).
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parameter CWL = 5,
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// in number of clock cycles
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// DDR3 SDRAM: CAS Write Latency (Mode Register 2).
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// DDR2 SDRAM: Can be ignored
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parameter OUTPUT_DRV = "HIGH",
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// Output Driver Impedance Control (Mode Register 1).
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// # = "HIGH" - RZQ/7,
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// = "LOW" - RZQ/6.
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parameter RTT_NOM = "40",
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// RTT_NOM (ODT) (Mode Register 1).
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// = "120" - RZQ/2,
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// = "60" - RZQ/4,
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// = "40" - RZQ/6.
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parameter RTT_WR = "OFF",
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// RTT_WR (ODT) (Mode Register 2).
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// # = "OFF" - Dynamic ODT off,
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// = "120" - RZQ/2,
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// = "60" - RZQ/4,
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parameter ADDR_CMD_MODE = "1T" ,
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// # = "1T", "2T".
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parameter REG_CTRL = "OFF",
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// # = "ON" - RDIMMs,
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// = "OFF" - Components, SODIMMs, UDIMMs.
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parameter CA_MIRROR = "OFF",
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// C/A mirror opt for DDR3 dual rank
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parameter VDD_OP_VOLT = "150",
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// # = "150" - 1.5V Vdd Memory part
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// = "135" - 1.35V Vdd Memory part
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//***************************************************************************
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// The following parameters are multiplier and divisor factors for PLLE2.
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// Based on the selected design frequency these parameters vary.
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//***************************************************************************
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parameter CLKIN_PERIOD = 2500,
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// Input Clock Period
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parameter CLKFBOUT_MULT = 2,
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// write PLL VCO multiplier
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parameter DIVCLK_DIVIDE = 1,
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// write PLL VCO divisor
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parameter CLKOUT0_PHASE = 337.5,
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// Phase for PLL output clock (CLKOUT0)
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parameter CLKOUT0_DIVIDE = 2,
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// VCO output divisor for PLL output clock (CLKOUT0)
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parameter CLKOUT1_DIVIDE = 2,
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// VCO output divisor for PLL output clock (CLKOUT1)
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parameter CLKOUT2_DIVIDE = 32,
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// VCO output divisor for PLL output clock (CLKOUT2)
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parameter CLKOUT3_DIVIDE = 8,
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// VCO output divisor for PLL output clock (CLKOUT3)
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parameter MMCM_VCO = 800,
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// Max Freq (MHz) of MMCM VCO
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parameter MMCM_MULT_F = 8,
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// write MMCM VCO multiplier
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parameter MMCM_DIVCLK_DIVIDE = 1,
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// write MMCM VCO divisor
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//***************************************************************************
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// Memory Timing Parameters. These parameters varies based on the selected
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// memory part.
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//***************************************************************************
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parameter tCKE = 5000,
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// memory tCKE paramter in pS
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parameter tFAW = 40000,
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// memory tRAW paramter in pS.
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parameter tPRDI = 1_000_000,
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// memory tPRDI paramter in pS.
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parameter tRAS = 35000,
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// memory tRAS paramter in pS.
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parameter tRCD = 13750,
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// memory tRCD paramter in pS.
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parameter tREFI = 7800000,
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// memory tREFI paramter in pS.
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parameter tRFC = 160000,
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// memory tRFC paramter in pS.
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parameter tRP = 13750,
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// memory tRP paramter in pS.
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parameter tRRD = 7500,
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// memory tRRD paramter in pS.
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parameter tRTP = 7500,
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// memory tRTP paramter in pS.
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parameter tWTR = 7500,
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// memory tWTR paramter in pS.
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parameter tZQI = 128_000_000,
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// memory tZQI paramter in nS.
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parameter tZQCS = 64,
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// memory tZQCS paramter in clock cycles.
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//***************************************************************************
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// Simulation parameters
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//***************************************************************************
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parameter SIM_BYPASS_INIT_CAL = "FAST",
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// # = "OFF" - Complete memory init &
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// calibration sequence
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// # = "SKIP" - Not supported
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// # = "FAST" - Complete memory init & use
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// abbreviated calib sequence
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parameter SIMULATION = "TRUE",
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// Should be TRUE during design simulations and
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// FALSE during implementations
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//***************************************************************************
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// The following parameters varies based on the pin out entered in MIG GUI.
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// Do not change any of these parameters directly by editing the RTL.
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// Any changes required should be done through GUI and the design regenerated.
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//***************************************************************************
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parameter BYTE_LANES_B0 = 4'b1111,
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// Byte lanes used in an IO column.
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parameter BYTE_LANES_B1 = 4'b0000,
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// Byte lanes used in an IO column.
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parameter BYTE_LANES_B2 = 4'b0000,
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// Byte lanes used in an IO column.
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parameter BYTE_LANES_B3 = 4'b0000,
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// Byte lanes used in an IO column.
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parameter BYTE_LANES_B4 = 4'b0000,
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// Byte lanes used in an IO column.
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parameter DATA_CTL_B0 = 4'b0011,
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// Indicates Byte lane is data byte lane
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// or control Byte lane. '1' in a bit
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// position indicates a data byte lane and
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// a '0' indicates a control byte lane
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parameter DATA_CTL_B1 = 4'b0000,
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// Indicates Byte lane is data byte lane
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// or control Byte lane. '1' in a bit
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// position indicates a data byte lane and
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// a '0' indicates a control byte lane
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parameter DATA_CTL_B2 = 4'b0000,
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// Indicates Byte lane is data byte lane
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// or control Byte lane. '1' in a bit
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// position indicates a data byte lane and
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// a '0' indicates a control byte lane
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parameter DATA_CTL_B3 = 4'b0000,
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// Indicates Byte lane is data byte lane
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// or control Byte lane. '1' in a bit
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// position indicates a data byte lane and
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// a '0' indicates a control byte lane
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parameter DATA_CTL_B4 = 4'b0000,
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// Indicates Byte lane is data byte lane
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// or control Byte lane. '1' in a bit
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// position indicates a data byte lane and
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// a '0' indicates a control byte lane
|
337 |
|
|
parameter PHY_0_BITLANES = 48'hFFF_CFF_3DF_2FF,
|
338 |
|
|
parameter PHY_1_BITLANES = 48'h000_000_000_000,
|
339 |
|
|
parameter PHY_2_BITLANES = 48'h000_000_000_000,
|
340 |
|
|
|
341 |
|
|
// control/address/data pin mapping parameters
|
342 |
|
|
parameter CK_BYTE_MAP
|
343 |
|
|
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02,
|
344 |
|
|
parameter ADDR_MAP
|
345 |
|
|
= 192'h000_000_037_025_03A_024_035_03B_039_027_031_026_023_034_036_038,
|
346 |
|
|
parameter BANK_MAP = 36'h033_02A_032,
|
347 |
|
|
parameter CAS_MAP = 12'h020,
|
348 |
|
|
parameter CKE_ODT_BYTE_MAP = 8'h00,
|
349 |
|
|
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_02B,
|
350 |
|
|
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_030,
|
351 |
|
|
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
|
352 |
|
|
parameter PARITY_MAP = 12'h000,
|
353 |
|
|
parameter RAS_MAP = 12'h021,
|
354 |
|
|
parameter WE_MAP = 12'h022,
|
355 |
|
|
parameter DQS_BYTE_MAP
|
356 |
|
|
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01,
|
357 |
|
|
parameter DATA0_MAP = 96'h016_018_014_019_010_017_011_013,
|
358 |
|
|
parameter DATA1_MAP = 96'h003_002_005_004_001_006_000_007,
|
359 |
|
|
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
|
360 |
|
|
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
|
361 |
|
|
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
|
362 |
|
|
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
|
363 |
|
|
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
|
364 |
|
|
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
|
365 |
|
|
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
|
366 |
|
|
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
|
367 |
|
|
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
|
368 |
|
|
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
|
369 |
|
|
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
|
370 |
|
|
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
|
371 |
|
|
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
|
372 |
|
|
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
|
373 |
|
|
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
|
374 |
|
|
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
|
375 |
|
|
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_009_012,
|
376 |
|
|
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
|
377 |
|
|
|
378 |
|
|
parameter SLOT_0_CONFIG = 8'b0000_0001,
|
379 |
|
|
// Mapping of Ranks.
|
380 |
|
|
parameter SLOT_1_CONFIG = 8'b0000_0000,
|
381 |
|
|
// Mapping of Ranks.
|
382 |
|
|
|
383 |
|
|
//***************************************************************************
|
384 |
|
|
// IODELAY and PHY related parameters
|
385 |
|
|
//***************************************************************************
|
386 |
|
|
parameter IBUF_LPWR_MODE = "OFF",
|
387 |
|
|
// to phy_top
|
388 |
|
|
parameter DATA_IO_IDLE_PWRDWN = "ON",
|
389 |
|
|
// # = "ON", "OFF"
|
390 |
|
|
parameter BANK_TYPE = "HR_IO",
|
391 |
|
|
// # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
|
392 |
|
|
parameter DATA_IO_PRIM_TYPE = "HR_LP",
|
393 |
|
|
// # = "HP_LP", "HR_LP", "DEFAULT"
|
394 |
|
|
parameter CKE_ODT_AUX = "FALSE",
|
395 |
|
|
parameter USER_REFRESH = "OFF",
|
396 |
|
|
parameter WRLVL = "ON",
|
397 |
|
|
// # = "ON" - DDR3 SDRAM
|
398 |
|
|
// = "OFF" - DDR2 SDRAM.
|
399 |
|
|
parameter ORDERING = "NORM",
|
400 |
|
|
// # = "NORM", "STRICT", "RELAXED".
|
401 |
|
|
parameter CALIB_ROW_ADD = 16'h0000,
|
402 |
|
|
// Calibration row address will be used for
|
403 |
|
|
// calibration read and write operations
|
404 |
|
|
parameter CALIB_COL_ADD = 12'h000,
|
405 |
|
|
// Calibration column address will be used for
|
406 |
|
|
// calibration read and write operations
|
407 |
|
|
parameter CALIB_BA_ADD = 3'h0,
|
408 |
|
|
// Calibration bank address will be used for
|
409 |
|
|
// calibration read and write operations
|
410 |
|
|
parameter TCQ = 100,
|
411 |
|
|
parameter IDELAY_ADJ = "OFF",
|
412 |
|
|
parameter FINE_PER_BIT = "OFF",
|
413 |
|
|
parameter CENTER_COMP_MODE = "OFF",
|
414 |
|
|
parameter PI_VAL_ADJ = "OFF",
|
415 |
|
|
parameter IODELAY_GRP0 = "MIG_7SERIES_0_IODELAY_MIG0",
|
416 |
|
|
// It is associated to a set of IODELAYs with
|
417 |
|
|
// an IDELAYCTRL that have same IODELAY CONTROLLER
|
418 |
|
|
// clock frequency (200MHz).
|
419 |
|
|
parameter IODELAY_GRP1 = "MIG_7SERIES_0_IODELAY_MIG1",
|
420 |
|
|
// It is associated to a set of IODELAYs with
|
421 |
|
|
// an IDELAYCTRL that have same IODELAY CONTROLLER
|
422 |
|
|
// clock frequency (300MHz/400MHz).
|
423 |
|
|
parameter SYSCLK_TYPE = "NO_BUFFER",
|
424 |
|
|
// System clock type DIFFERENTIAL, SINGLE_ENDED,
|
425 |
|
|
// NO_BUFFER
|
426 |
|
|
parameter REFCLK_TYPE = "NO_BUFFER",
|
427 |
|
|
// Reference clock type DIFFERENTIAL, SINGLE_ENDED,
|
428 |
|
|
// NO_BUFFER, USE_SYSTEM_CLOCK
|
429 |
|
|
parameter SYS_RST_PORT = "FALSE",
|
430 |
|
|
// "TRUE" - if pin is selected for sys_rst
|
431 |
|
|
// and IBUF will be instantiated.
|
432 |
|
|
// "FALSE" - if pin is not selected for sys_rst
|
433 |
|
|
parameter FPGA_SPEED_GRADE = 2,
|
434 |
|
|
// FPGA speed grade
|
435 |
|
|
|
436 |
|
|
parameter CMD_PIPE_PLUS1 = "ON",
|
437 |
|
|
// add pipeline stage between MC and PHY
|
438 |
|
|
parameter DRAM_TYPE = "DDR3",
|
439 |
|
|
parameter CAL_WIDTH = "HALF",
|
440 |
|
|
parameter STARVE_LIMIT = 2,
|
441 |
|
|
// # = 2,3,4.
|
442 |
|
|
parameter REF_CLK_MMCM_IODELAY_CTRL = "FALSE",
|
443 |
|
|
|
444 |
|
|
//***************************************************************************
|
445 |
|
|
// Referece clock frequency parameters
|
446 |
|
|
//***************************************************************************
|
447 |
|
|
parameter REFCLK_FREQ = 200.0,
|
448 |
|
|
// IODELAYCTRL reference clock frequency
|
449 |
|
|
parameter DIFF_TERM_REFCLK = "TRUE",
|
450 |
|
|
// Differential Termination for idelay
|
451 |
|
|
// reference clock input pins
|
452 |
|
|
//***************************************************************************
|
453 |
|
|
// System clock frequency parameters
|
454 |
|
|
//***************************************************************************
|
455 |
|
|
parameter tCK = 2500,
|
456 |
|
|
// memory tCK paramter.
|
457 |
|
|
// # = Clock Period in pS.
|
458 |
|
|
parameter nCK_PER_CLK = 4,
|
459 |
|
|
// # of memory CKs per fabric CLK
|
460 |
|
|
parameter DIFF_TERM_SYSCLK = "TRUE",
|
461 |
|
|
// Differential Termination for System
|
462 |
|
|
// clock input pins
|
463 |
|
|
|
464 |
|
|
|
465 |
|
|
|
466 |
|
|
//***************************************************************************
|
467 |
|
|
// Debug parameters
|
468 |
|
|
//***************************************************************************
|
469 |
|
|
parameter DEBUG_PORT = "OFF",
|
470 |
|
|
// # = "ON" Enable debug signals/controls.
|
471 |
|
|
// = "OFF" Disable debug signals/controls.
|
472 |
|
|
|
473 |
|
|
//***************************************************************************
|
474 |
|
|
// Temparature monitor parameter
|
475 |
|
|
//***************************************************************************
|
476 |
|
|
parameter TEMP_MON_CONTROL = "INTERNAL",
|
477 |
|
|
// # = "INTERNAL", "EXTERNAL"
|
478 |
|
|
|
479 |
|
|
parameter RST_ACT_LOW = 1
|
480 |
|
|
// =1 for active low reset,
|
481 |
|
|
// =0 for active high.
|
482 |
|
|
)
|
483 |
|
|
(
|
484 |
|
|
|
485 |
|
|
// Inouts
|
486 |
|
|
inout [DQ_WIDTH-1:0] ddr3_dq,
|
487 |
|
|
inout [DQS_WIDTH-1:0] ddr3_dqs_n,
|
488 |
|
|
inout [DQS_WIDTH-1:0] ddr3_dqs_p,
|
489 |
|
|
|
490 |
|
|
// Outputs
|
491 |
|
|
output [ROW_WIDTH-1:0] ddr3_addr,
|
492 |
|
|
output [BANK_WIDTH-1:0] ddr3_ba,
|
493 |
|
|
output ddr3_ras_n,
|
494 |
|
|
output ddr3_cas_n,
|
495 |
|
|
output ddr3_we_n,
|
496 |
|
|
output ddr3_reset_n,
|
497 |
|
|
output [CK_WIDTH-1:0] ddr3_ck_p,
|
498 |
|
|
output [CK_WIDTH-1:0] ddr3_ck_n,
|
499 |
|
|
output [CKE_WIDTH-1:0] ddr3_cke,
|
500 |
|
|
output [DM_WIDTH-1:0] ddr3_dm,
|
501 |
|
|
output [ODT_WIDTH-1:0] ddr3_odt,
|
502 |
|
|
|
503 |
|
|
// Inputs
|
504 |
|
|
// Single-ended system clock
|
505 |
|
|
input sys_clk_i,
|
506 |
|
|
// Single-ended iodelayctrl clk (reference clock)
|
507 |
|
|
input clk_ref_i,
|
508 |
|
|
// user interface signals
|
509 |
|
|
input [ADDR_WIDTH-1:0] app_addr,
|
510 |
|
|
input [2:0] app_cmd,
|
511 |
|
|
input app_en,
|
512 |
|
|
input [(nCK_PER_CLK*2*PAYLOAD_WIDTH)-1:0] app_wdf_data,
|
513 |
|
|
input app_wdf_end,
|
514 |
|
|
input [((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8)-1:0] app_wdf_mask,
|
515 |
|
|
input app_wdf_wren,
|
516 |
|
|
output [(nCK_PER_CLK*2*PAYLOAD_WIDTH)-1:0] app_rd_data,
|
517 |
|
|
output app_rd_data_end,
|
518 |
|
|
output app_rd_data_valid,
|
519 |
|
|
output app_rdy,
|
520 |
|
|
output app_wdf_rdy,
|
521 |
|
|
input app_sr_req,
|
522 |
|
|
input app_ref_req,
|
523 |
|
|
input app_zq_req,
|
524 |
|
|
output app_sr_active,
|
525 |
|
|
output app_ref_ack,
|
526 |
|
|
output app_zq_ack,
|
527 |
|
|
output ui_clk,
|
528 |
|
|
output ui_clk_sync_rst,
|
529 |
|
|
output init_calib_complete,
|
530 |
|
|
|
531 |
|
|
|
532 |
|
|
// System reset - Default polarity of sys_rst pin is Active Low.
|
533 |
|
|
// System reset polarity will change based on the option
|
534 |
|
|
// selected in GUI.
|
535 |
|
|
input sys_rst
|
536 |
|
|
);
|
537 |
|
|
|
538 |
|
|
function integer clogb2 (input integer size);
|
539 |
|
|
begin
|
540 |
|
|
size = size - 1;
|
541 |
|
|
for (clogb2=1; size>1; clogb2=clogb2+1)
|
542 |
|
|
size = size >> 1;
|
543 |
|
|
end
|
544 |
|
|
endfunction // clogb2
|
545 |
|
|
|
546 |
|
|
|
547 |
|
|
localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS);
|
548 |
|
|
localparam RANK_WIDTH = clogb2(RANKS);
|
549 |
|
|
|
550 |
|
|
localparam ECC_WIDTH = (ECC == "OFF")?
|
551 |
|
|
|
552 |
|
|
4 : (DATA_WIDTH <= 10)?
|
553 |
|
|
5 : (DATA_WIDTH <= 26)?
|
554 |
|
|
6 : (DATA_WIDTH <= 57)?
|
555 |
|
|
7 : (DATA_WIDTH <= 120)?
|
556 |
|
|
8 : (DATA_WIDTH <= 247)?
|
557 |
|
|
9 : 10;
|
558 |
|
|
localparam DATA_BUF_OFFSET_WIDTH = 1;
|
559 |
|
|
localparam MC_ERR_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH)
|
560 |
|
|
+ BANK_WIDTH + ROW_WIDTH + COL_WIDTH
|
561 |
|
|
+ DATA_BUF_OFFSET_WIDTH;
|
562 |
|
|
|
563 |
|
|
localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
|
564 |
|
|
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
|
565 |
|
|
localparam TEMP_MON_EN = (SIMULATION == "TRUE") ? "ON" : "OFF";
|
566 |
|
|
// Enable or disable the temp monitor module
|
567 |
|
|
localparam tTEMPSAMPLE = 10000000; // sample every 10 us
|
568 |
|
|
localparam XADC_CLK_PERIOD = 5000; // Use 200 MHz IODELAYCTRL clock
|
569 |
|
|
|
570 |
|
|
|
571 |
|
|
localparam TAPSPERKCLK = (56*MMCM_MULT_F)/nCK_PER_CLK;
|
572 |
|
|
|
573 |
|
|
// Wire declarations
|
574 |
|
|
|
575 |
|
|
wire [BM_CNT_WIDTH-1:0] bank_mach_next;
|
576 |
|
|
wire clk;
|
577 |
|
|
wire [1:0] clk_ref;
|
578 |
|
|
wire [1:0] iodelay_ctrl_rdy;
|
579 |
|
|
wire clk_ref_in;
|
580 |
|
|
wire sys_rst_o;
|
581 |
|
|
wire freq_refclk ;
|
582 |
|
|
wire mem_refclk ;
|
583 |
|
|
wire pll_lock ;
|
584 |
|
|
wire sync_pulse;
|
585 |
|
|
wire mmcm_ps_clk;
|
586 |
|
|
wire poc_sample_pd;
|
587 |
|
|
wire psen;
|
588 |
|
|
wire psincdec;
|
589 |
|
|
wire psdone;
|
590 |
|
|
wire iddr_rst;
|
591 |
|
|
wire ref_dll_lock;
|
592 |
|
|
wire rst_phaser_ref;
|
593 |
|
|
wire pll_locked;
|
594 |
|
|
|
595 |
|
|
wire rst;
|
596 |
|
|
|
597 |
|
|
wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err;
|
598 |
|
|
wire ddr3_parity;
|
599 |
|
|
|
600 |
|
|
|
601 |
|
|
wire sys_clk_p;
|
602 |
|
|
wire sys_clk_n;
|
603 |
|
|
wire mmcm_clk;
|
604 |
|
|
wire clk_ref_p;
|
605 |
|
|
wire clk_ref_n;
|
606 |
|
|
wire [11:0] device_temp;
|
607 |
|
|
wire [11:0] device_temp_i;
|
608 |
|
|
|
609 |
|
|
// Debug port signals
|
610 |
|
|
wire dbg_idel_down_all;
|
611 |
|
|
wire dbg_idel_down_cpt;
|
612 |
|
|
wire dbg_idel_up_all;
|
613 |
|
|
wire dbg_idel_up_cpt;
|
614 |
|
|
wire dbg_sel_all_idel_cpt;
|
615 |
|
|
wire [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt;
|
616 |
|
|
wire dbg_sel_pi_incdec;
|
617 |
|
|
wire [DQS_CNT_WIDTH:0] dbg_byte_sel;
|
618 |
|
|
wire dbg_pi_f_inc;
|
619 |
|
|
wire dbg_pi_f_dec;
|
620 |
|
|
wire [5:0] dbg_pi_counter_read_val;
|
621 |
|
|
wire [8:0] dbg_po_counter_read_val;
|
622 |
|
|
|
623 |
|
|
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_tap_cnt;
|
624 |
|
|
wire [(5*DQS_WIDTH*RANKS)-1:0] dbg_dq_idelay_tap_cnt;
|
625 |
|
|
wire [255:0] dbg_calib_top;
|
626 |
|
|
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_first_edge_cnt;
|
627 |
|
|
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_second_edge_cnt;
|
628 |
|
|
wire [(6*RANKS)-1:0] dbg_rd_data_offset;
|
629 |
|
|
wire [255:0] dbg_phy_rdlvl;
|
630 |
|
|
wire [99:0] dbg_phy_wrcal;
|
631 |
|
|
wire [(6*DQS_WIDTH)-1:0] dbg_final_po_fine_tap_cnt;
|
632 |
|
|
wire [(3*DQS_WIDTH)-1:0] dbg_final_po_coarse_tap_cnt;
|
633 |
|
|
wire [255:0] dbg_phy_wrlvl;
|
634 |
|
|
wire [255:0] dbg_phy_init;
|
635 |
|
|
wire [255:0] dbg_prbs_rdlvl;
|
636 |
|
|
wire [255:0] dbg_dqs_found_cal;
|
637 |
|
|
wire dbg_pi_phaselock_start;
|
638 |
|
|
wire dbg_pi_phaselocked_done;
|
639 |
|
|
wire dbg_pi_phaselock_err;
|
640 |
|
|
wire dbg_pi_dqsfound_start;
|
641 |
|
|
wire dbg_pi_dqsfound_done;
|
642 |
|
|
wire dbg_pi_dqsfound_err;
|
643 |
|
|
wire dbg_wrcal_start;
|
644 |
|
|
wire dbg_wrcal_done;
|
645 |
|
|
wire dbg_wrcal_err;
|
646 |
|
|
wire [11:0] dbg_pi_dqs_found_lanes_phy4lanes;
|
647 |
|
|
wire [11:0] dbg_pi_phase_locked_phy4lanes;
|
648 |
|
|
wire dbg_oclkdelay_calib_start;
|
649 |
|
|
wire dbg_oclkdelay_calib_done;
|
650 |
|
|
wire [255:0] dbg_phy_oclkdelay_cal;
|
651 |
|
|
wire [(DRAM_WIDTH*16)-1:0] dbg_oclkdelay_rd_data;
|
652 |
|
|
wire [DQS_WIDTH-1:0] dbg_rd_data_edge_detect;
|
653 |
|
|
wire [(2*nCK_PER_CLK*DQ_WIDTH)-1:0] dbg_rddata;
|
654 |
|
|
wire dbg_rddata_valid;
|
655 |
|
|
wire [1:0] dbg_rdlvl_done;
|
656 |
|
|
wire [1:0] dbg_rdlvl_err;
|
657 |
|
|
wire [1:0] dbg_rdlvl_start;
|
658 |
|
|
wire [(6*DQS_WIDTH)-1:0] dbg_wrlvl_fine_tap_cnt;
|
659 |
|
|
wire [(3*DQS_WIDTH)-1:0] dbg_wrlvl_coarse_tap_cnt;
|
660 |
|
|
wire [5:0] dbg_tap_cnt_during_wrlvl;
|
661 |
|
|
wire dbg_wl_edge_detect_valid;
|
662 |
|
|
wire dbg_wrlvl_done;
|
663 |
|
|
wire dbg_wrlvl_err;
|
664 |
|
|
wire dbg_wrlvl_start;
|
665 |
|
|
reg [63:0] dbg_rddata_r;
|
666 |
|
|
reg dbg_rddata_valid_r;
|
667 |
|
|
wire [53:0] ocal_tap_cnt;
|
668 |
|
|
wire [4:0] dbg_dqs;
|
669 |
|
|
wire [8:0] dbg_bit;
|
670 |
|
|
wire [8:0] rd_data_edge_detect_r;
|
671 |
|
|
wire [53:0] wl_po_fine_cnt;
|
672 |
|
|
wire [26:0] wl_po_coarse_cnt;
|
673 |
|
|
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_1;
|
674 |
|
|
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_2;
|
675 |
|
|
wire [5:0] dbg_data_offset;
|
676 |
|
|
wire [5:0] dbg_data_offset_1;
|
677 |
|
|
wire [5:0] dbg_data_offset_2;
|
678 |
|
|
|
679 |
|
|
wire [390:0] ddr3_ila_wrpath_int;
|
680 |
|
|
wire [1023:0] ddr3_ila_rdpath_int;
|
681 |
|
|
wire [119:0] ddr3_ila_basic_int;
|
682 |
|
|
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_final_dqs_tap_cnt_r_int;
|
683 |
|
|
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_first_edge_taps_int;
|
684 |
|
|
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_second_edge_taps_int;
|
685 |
|
|
|
686 |
|
|
|
687 |
|
|
//***************************************************************************
|
688 |
|
|
|
689 |
|
|
|
690 |
|
|
|
691 |
|
|
assign ui_clk = clk;
|
692 |
|
|
assign ui_clk_sync_rst = rst;
|
693 |
|
|
|
694 |
|
|
assign sys_clk_p = 1'b0;
|
695 |
|
|
assign sys_clk_n = 1'b0;
|
696 |
|
|
assign clk_ref_p = 1'b0;
|
697 |
|
|
assign clk_ref_n = 1'b0;
|
698 |
|
|
|
699 |
|
|
|
700 |
|
|
generate
|
701 |
|
|
if (REFCLK_TYPE == "USE_SYSTEM_CLOCK")
|
702 |
|
|
assign clk_ref_in = mmcm_clk;
|
703 |
|
|
else
|
704 |
|
|
assign clk_ref_in = clk_ref_i;
|
705 |
|
|
endgenerate
|
706 |
|
|
|
707 |
|
|
mig_7series_v2_3_iodelay_ctrl #
|
708 |
|
|
(
|
709 |
|
|
.TCQ (TCQ),
|
710 |
|
|
.IODELAY_GRP0 (IODELAY_GRP0),
|
711 |
|
|
.IODELAY_GRP1 (IODELAY_GRP1),
|
712 |
|
|
.REFCLK_TYPE (REFCLK_TYPE),
|
713 |
|
|
.SYSCLK_TYPE (SYSCLK_TYPE),
|
714 |
|
|
.SYS_RST_PORT (SYS_RST_PORT),
|
715 |
|
|
.RST_ACT_LOW (RST_ACT_LOW),
|
716 |
|
|
.DIFF_TERM_REFCLK (DIFF_TERM_REFCLK),
|
717 |
|
|
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
|
718 |
|
|
.REF_CLK_MMCM_IODELAY_CTRL (REF_CLK_MMCM_IODELAY_CTRL)
|
719 |
|
|
)
|
720 |
|
|
u_iodelay_ctrl
|
721 |
|
|
(
|
722 |
|
|
// Outputs
|
723 |
|
|
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
|
724 |
|
|
.sys_rst_o (sys_rst_o),
|
725 |
|
|
.clk_ref (clk_ref),
|
726 |
|
|
// Inputs
|
727 |
|
|
.clk_ref_p (clk_ref_p),
|
728 |
|
|
.clk_ref_n (clk_ref_n),
|
729 |
|
|
.clk_ref_i (clk_ref_in),
|
730 |
|
|
.sys_rst (sys_rst)
|
731 |
|
|
);
|
732 |
|
|
mig_7series_v2_3_clk_ibuf #
|
733 |
|
|
(
|
734 |
|
|
.SYSCLK_TYPE (SYSCLK_TYPE),
|
735 |
|
|
.DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK)
|
736 |
|
|
)
|
737 |
|
|
u_ddr3_clk_ibuf
|
738 |
|
|
(
|
739 |
|
|
.sys_clk_p (sys_clk_p),
|
740 |
|
|
.sys_clk_n (sys_clk_n),
|
741 |
|
|
.sys_clk_i (sys_clk_i),
|
742 |
|
|
.mmcm_clk (mmcm_clk)
|
743 |
|
|
);
|
744 |
|
|
// Temperature monitoring logic
|
745 |
|
|
|
746 |
|
|
generate
|
747 |
|
|
if (TEMP_MON_EN == "ON") begin: temp_mon_enabled
|
748 |
|
|
|
749 |
|
|
mig_7series_v2_3_tempmon #
|
750 |
|
|
(
|
751 |
|
|
.TCQ (TCQ),
|
752 |
|
|
.TEMP_MON_CONTROL (TEMP_MON_CONTROL),
|
753 |
|
|
.XADC_CLK_PERIOD (XADC_CLK_PERIOD),
|
754 |
|
|
.tTEMPSAMPLE (tTEMPSAMPLE)
|
755 |
|
|
)
|
756 |
|
|
u_tempmon
|
757 |
|
|
(
|
758 |
|
|
.clk (clk),
|
759 |
|
|
.xadc_clk (clk_ref[0]),
|
760 |
|
|
.rst (rst),
|
761 |
|
|
.device_temp_i (device_temp_i),
|
762 |
|
|
.device_temp (device_temp)
|
763 |
|
|
);
|
764 |
|
|
end else begin: temp_mon_disabled
|
765 |
|
|
|
766 |
|
|
assign device_temp = 'b0;
|
767 |
|
|
|
768 |
|
|
end
|
769 |
|
|
endgenerate
|
770 |
|
|
|
771 |
|
|
mig_7series_v2_3_infrastructure #
|
772 |
|
|
(
|
773 |
|
|
.TCQ (TCQ),
|
774 |
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
775 |
|
|
.CLKIN_PERIOD (CLKIN_PERIOD),
|
776 |
|
|
.SYSCLK_TYPE (SYSCLK_TYPE),
|
777 |
|
|
.CLKFBOUT_MULT (CLKFBOUT_MULT),
|
778 |
|
|
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
|
779 |
|
|
.CLKOUT0_PHASE (CLKOUT0_PHASE),
|
780 |
|
|
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
|
781 |
|
|
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
|
782 |
|
|
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
|
783 |
|
|
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
|
784 |
|
|
.MMCM_VCO (MMCM_VCO),
|
785 |
|
|
.MMCM_MULT_F (MMCM_MULT_F),
|
786 |
|
|
.MMCM_DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE),
|
787 |
|
|
.RST_ACT_LOW (RST_ACT_LOW),
|
788 |
|
|
.tCK (tCK),
|
789 |
|
|
.MEM_TYPE (DRAM_TYPE)
|
790 |
|
|
)
|
791 |
|
|
u_ddr3_infrastructure
|
792 |
|
|
(
|
793 |
|
|
// Outputs
|
794 |
|
|
.rstdiv0 (rst),
|
795 |
|
|
.clk (clk),
|
796 |
|
|
.mem_refclk (mem_refclk),
|
797 |
|
|
.freq_refclk (freq_refclk),
|
798 |
|
|
.sync_pulse (sync_pulse),
|
799 |
|
|
.mmcm_ps_clk (mmcm_ps_clk),
|
800 |
|
|
.poc_sample_pd (poc_sample_pd),
|
801 |
|
|
.psdone (psdone),
|
802 |
|
|
.iddr_rst (iddr_rst),
|
803 |
|
|
.auxout_clk (),
|
804 |
|
|
.ui_addn_clk_0 (),
|
805 |
|
|
.ui_addn_clk_1 (),
|
806 |
|
|
.ui_addn_clk_2 (),
|
807 |
|
|
.ui_addn_clk_3 (),
|
808 |
|
|
.ui_addn_clk_4 (),
|
809 |
|
|
.pll_locked (pll_locked),
|
810 |
|
|
.mmcm_locked (),
|
811 |
|
|
.rst_phaser_ref (rst_phaser_ref),
|
812 |
|
|
// Inputs
|
813 |
|
|
.psen (psen),
|
814 |
|
|
.psincdec (psincdec),
|
815 |
|
|
.mmcm_clk (mmcm_clk),
|
816 |
|
|
.sys_rst (sys_rst_o),
|
817 |
|
|
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
|
818 |
|
|
.ref_dll_lock (ref_dll_lock)
|
819 |
|
|
);
|
820 |
|
|
|
821 |
|
|
|
822 |
|
|
mig_7series_v2_3_memc_ui_top_std #
|
823 |
|
|
(
|
824 |
|
|
.TCQ (TCQ),
|
825 |
|
|
.ADDR_CMD_MODE (ADDR_CMD_MODE),
|
826 |
|
|
.AL (AL),
|
827 |
|
|
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
|
828 |
|
|
.BANK_WIDTH (BANK_WIDTH),
|
829 |
|
|
.BM_CNT_WIDTH (BM_CNT_WIDTH),
|
830 |
|
|
.BURST_MODE (BURST_MODE),
|
831 |
|
|
.BURST_TYPE (BURST_TYPE),
|
832 |
|
|
.CA_MIRROR (CA_MIRROR),
|
833 |
|
|
.DDR3_VDD_OP_VOLT (VDD_OP_VOLT),
|
834 |
|
|
.CK_WIDTH (CK_WIDTH),
|
835 |
|
|
.COL_WIDTH (COL_WIDTH),
|
836 |
|
|
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
|
837 |
|
|
.CS_WIDTH (CS_WIDTH),
|
838 |
|
|
.nCS_PER_RANK (nCS_PER_RANK),
|
839 |
|
|
.CKE_WIDTH (CKE_WIDTH),
|
840 |
|
|
.DATA_WIDTH (DATA_WIDTH),
|
841 |
|
|
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
|
842 |
|
|
.DM_WIDTH (DM_WIDTH),
|
843 |
|
|
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
|
844 |
|
|
.DQ_WIDTH (DQ_WIDTH),
|
845 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
846 |
|
|
.DQS_WIDTH (DQS_WIDTH),
|
847 |
|
|
.DRAM_TYPE (DRAM_TYPE),
|
848 |
|
|
.DRAM_WIDTH (DRAM_WIDTH),
|
849 |
|
|
.ECC (ECC),
|
850 |
|
|
.ECC_WIDTH (ECC_WIDTH),
|
851 |
|
|
.ECC_TEST (ECC_TEST),
|
852 |
|
|
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
|
853 |
|
|
.REFCLK_FREQ (REFCLK_FREQ),
|
854 |
|
|
.nAL (nAL),
|
855 |
|
|
.nBANK_MACHS (nBANK_MACHS),
|
856 |
|
|
.CKE_ODT_AUX (CKE_ODT_AUX),
|
857 |
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
858 |
|
|
.ORDERING (ORDERING),
|
859 |
|
|
.OUTPUT_DRV (OUTPUT_DRV),
|
860 |
|
|
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
|
861 |
|
|
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
|
862 |
|
|
.BANK_TYPE (BANK_TYPE),
|
863 |
|
|
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
|
864 |
|
|
.IODELAY_GRP0 (IODELAY_GRP0),
|
865 |
|
|
.IODELAY_GRP1 (IODELAY_GRP1),
|
866 |
|
|
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
|
867 |
|
|
.REG_CTRL (REG_CTRL),
|
868 |
|
|
.RTT_NOM (RTT_NOM),
|
869 |
|
|
.RTT_WR (RTT_WR),
|
870 |
|
|
.CL (CL),
|
871 |
|
|
.CWL (CWL),
|
872 |
|
|
.tCK (tCK),
|
873 |
|
|
.tCKE (tCKE),
|
874 |
|
|
.tFAW (tFAW),
|
875 |
|
|
.tPRDI (tPRDI),
|
876 |
|
|
.tRAS (tRAS),
|
877 |
|
|
.tRCD (tRCD),
|
878 |
|
|
.tREFI (tREFI),
|
879 |
|
|
.tRFC (tRFC),
|
880 |
|
|
.tRP (tRP),
|
881 |
|
|
.tRRD (tRRD),
|
882 |
|
|
.tRTP (tRTP),
|
883 |
|
|
.tWTR (tWTR),
|
884 |
|
|
.tZQI (tZQI),
|
885 |
|
|
.tZQCS (tZQCS),
|
886 |
|
|
.USER_REFRESH (USER_REFRESH),
|
887 |
|
|
.TEMP_MON_EN (TEMP_MON_EN),
|
888 |
|
|
.WRLVL (WRLVL),
|
889 |
|
|
.DEBUG_PORT (DEBUG_PORT),
|
890 |
|
|
.CAL_WIDTH (CAL_WIDTH),
|
891 |
|
|
.RANK_WIDTH (RANK_WIDTH),
|
892 |
|
|
.RANKS (RANKS),
|
893 |
|
|
.ODT_WIDTH (ODT_WIDTH),
|
894 |
|
|
.ROW_WIDTH (ROW_WIDTH),
|
895 |
|
|
.ADDR_WIDTH (ADDR_WIDTH),
|
896 |
|
|
.APP_DATA_WIDTH (APP_DATA_WIDTH),
|
897 |
|
|
.APP_MASK_WIDTH (APP_MASK_WIDTH),
|
898 |
|
|
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
|
899 |
|
|
.BYTE_LANES_B0 (BYTE_LANES_B0),
|
900 |
|
|
.BYTE_LANES_B1 (BYTE_LANES_B1),
|
901 |
|
|
.BYTE_LANES_B2 (BYTE_LANES_B2),
|
902 |
|
|
.BYTE_LANES_B3 (BYTE_LANES_B3),
|
903 |
|
|
.BYTE_LANES_B4 (BYTE_LANES_B4),
|
904 |
|
|
.DATA_CTL_B0 (DATA_CTL_B0),
|
905 |
|
|
.DATA_CTL_B1 (DATA_CTL_B1),
|
906 |
|
|
.DATA_CTL_B2 (DATA_CTL_B2),
|
907 |
|
|
.DATA_CTL_B3 (DATA_CTL_B3),
|
908 |
|
|
.DATA_CTL_B4 (DATA_CTL_B4),
|
909 |
|
|
.PHY_0_BITLANES (PHY_0_BITLANES),
|
910 |
|
|
.PHY_1_BITLANES (PHY_1_BITLANES),
|
911 |
|
|
.PHY_2_BITLANES (PHY_2_BITLANES),
|
912 |
|
|
.CK_BYTE_MAP (CK_BYTE_MAP),
|
913 |
|
|
.ADDR_MAP (ADDR_MAP),
|
914 |
|
|
.BANK_MAP (BANK_MAP),
|
915 |
|
|
.CAS_MAP (CAS_MAP),
|
916 |
|
|
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
|
917 |
|
|
.CKE_MAP (CKE_MAP),
|
918 |
|
|
.ODT_MAP (ODT_MAP),
|
919 |
|
|
.CS_MAP (CS_MAP),
|
920 |
|
|
.PARITY_MAP (PARITY_MAP),
|
921 |
|
|
.RAS_MAP (RAS_MAP),
|
922 |
|
|
.WE_MAP (WE_MAP),
|
923 |
|
|
.DQS_BYTE_MAP (DQS_BYTE_MAP),
|
924 |
|
|
.DATA0_MAP (DATA0_MAP),
|
925 |
|
|
.DATA1_MAP (DATA1_MAP),
|
926 |
|
|
.DATA2_MAP (DATA2_MAP),
|
927 |
|
|
.DATA3_MAP (DATA3_MAP),
|
928 |
|
|
.DATA4_MAP (DATA4_MAP),
|
929 |
|
|
.DATA5_MAP (DATA5_MAP),
|
930 |
|
|
.DATA6_MAP (DATA6_MAP),
|
931 |
|
|
.DATA7_MAP (DATA7_MAP),
|
932 |
|
|
.DATA8_MAP (DATA8_MAP),
|
933 |
|
|
.DATA9_MAP (DATA9_MAP),
|
934 |
|
|
.DATA10_MAP (DATA10_MAP),
|
935 |
|
|
.DATA11_MAP (DATA11_MAP),
|
936 |
|
|
.DATA12_MAP (DATA12_MAP),
|
937 |
|
|
.DATA13_MAP (DATA13_MAP),
|
938 |
|
|
.DATA14_MAP (DATA14_MAP),
|
939 |
|
|
.DATA15_MAP (DATA15_MAP),
|
940 |
|
|
.DATA16_MAP (DATA16_MAP),
|
941 |
|
|
.DATA17_MAP (DATA17_MAP),
|
942 |
|
|
.MASK0_MAP (MASK0_MAP),
|
943 |
|
|
.MASK1_MAP (MASK1_MAP),
|
944 |
|
|
.CALIB_ROW_ADD (CALIB_ROW_ADD),
|
945 |
|
|
.CALIB_COL_ADD (CALIB_COL_ADD),
|
946 |
|
|
.CALIB_BA_ADD (CALIB_BA_ADD),
|
947 |
|
|
.IDELAY_ADJ (IDELAY_ADJ),
|
948 |
|
|
.FINE_PER_BIT (FINE_PER_BIT),
|
949 |
|
|
.CENTER_COMP_MODE (CENTER_COMP_MODE),
|
950 |
|
|
.PI_VAL_ADJ (PI_VAL_ADJ),
|
951 |
|
|
.SLOT_0_CONFIG (SLOT_0_CONFIG),
|
952 |
|
|
.SLOT_1_CONFIG (SLOT_1_CONFIG),
|
953 |
|
|
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
|
954 |
|
|
.STARVE_LIMIT (STARVE_LIMIT),
|
955 |
|
|
.USE_CS_PORT (USE_CS_PORT),
|
956 |
|
|
.USE_DM_PORT (USE_DM_PORT),
|
957 |
|
|
.USE_ODT_PORT (USE_ODT_PORT),
|
958 |
|
|
.MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK),
|
959 |
|
|
.TAPSPERKCLK (TAPSPERKCLK)
|
960 |
|
|
)
|
961 |
|
|
u_memc_ui_top_std
|
962 |
|
|
(
|
963 |
|
|
.clk (clk),
|
964 |
|
|
.clk_ref (clk_ref),
|
965 |
|
|
.mem_refclk (mem_refclk), //memory clock
|
966 |
|
|
.freq_refclk (freq_refclk),
|
967 |
|
|
.pll_lock (pll_locked),
|
968 |
|
|
.sync_pulse (sync_pulse),
|
969 |
|
|
.mmcm_ps_clk (mmcm_ps_clk),
|
970 |
|
|
.poc_sample_pd (poc_sample_pd),
|
971 |
|
|
.psdone (psdone),
|
972 |
|
|
.iddr_rst (iddr_rst),
|
973 |
|
|
.psen (psen),
|
974 |
|
|
.psincdec (psincdec),
|
975 |
|
|
.rst (rst),
|
976 |
|
|
.rst_phaser_ref (rst_phaser_ref),
|
977 |
|
|
.ref_dll_lock (ref_dll_lock),
|
978 |
|
|
|
979 |
|
|
// Memory interface ports
|
980 |
|
|
.ddr_dq (ddr3_dq),
|
981 |
|
|
.ddr_dqs_n (ddr3_dqs_n),
|
982 |
|
|
.ddr_dqs (ddr3_dqs_p),
|
983 |
|
|
.ddr_addr (ddr3_addr),
|
984 |
|
|
.ddr_ba (ddr3_ba),
|
985 |
|
|
.ddr_cas_n (ddr3_cas_n),
|
986 |
|
|
.ddr_ck_n (ddr3_ck_n),
|
987 |
|
|
.ddr_ck (ddr3_ck_p),
|
988 |
|
|
.ddr_cke (ddr3_cke),
|
989 |
|
|
.ddr_cs_n (),
|
990 |
|
|
.ddr_dm (ddr3_dm),
|
991 |
|
|
.ddr_odt (ddr3_odt),
|
992 |
|
|
.ddr_ras_n (ddr3_ras_n),
|
993 |
|
|
.ddr_reset_n (ddr3_reset_n),
|
994 |
|
|
.ddr_parity (ddr3_parity),
|
995 |
|
|
.ddr_we_n (ddr3_we_n),
|
996 |
|
|
.bank_mach_next (bank_mach_next),
|
997 |
|
|
|
998 |
|
|
// Application interface ports
|
999 |
|
|
.app_addr (app_addr),
|
1000 |
|
|
.app_cmd (app_cmd),
|
1001 |
|
|
.app_en (app_en),
|
1002 |
|
|
.app_hi_pri (1'b0),
|
1003 |
|
|
.app_wdf_data (app_wdf_data),
|
1004 |
|
|
.app_wdf_end (app_wdf_end),
|
1005 |
|
|
.app_wdf_mask (app_wdf_mask),
|
1006 |
|
|
.app_wdf_wren (app_wdf_wren),
|
1007 |
|
|
.app_ecc_multiple_err (app_ecc_multiple_err),
|
1008 |
|
|
.app_rd_data (app_rd_data),
|
1009 |
|
|
.app_rd_data_end (app_rd_data_end),
|
1010 |
|
|
.app_rd_data_valid (app_rd_data_valid),
|
1011 |
|
|
.app_rdy (app_rdy),
|
1012 |
|
|
.app_wdf_rdy (app_wdf_rdy),
|
1013 |
|
|
.app_sr_req (app_sr_req),
|
1014 |
|
|
.app_sr_active (app_sr_active),
|
1015 |
|
|
.app_ref_req (app_ref_req),
|
1016 |
|
|
.app_ref_ack (app_ref_ack),
|
1017 |
|
|
.app_zq_req (app_zq_req),
|
1018 |
|
|
.app_zq_ack (app_zq_ack),
|
1019 |
|
|
.app_raw_not_ecc ({2*nCK_PER_CLK{1'b0}}),
|
1020 |
|
|
.app_correct_en_i (1'b1),
|
1021 |
|
|
|
1022 |
|
|
.device_temp (device_temp),
|
1023 |
|
|
|
1024 |
|
|
// Debug logic ports
|
1025 |
|
|
.dbg_idel_up_all (dbg_idel_up_all),
|
1026 |
|
|
.dbg_idel_down_all (dbg_idel_down_all),
|
1027 |
|
|
.dbg_idel_up_cpt (dbg_idel_up_cpt),
|
1028 |
|
|
.dbg_idel_down_cpt (dbg_idel_down_cpt),
|
1029 |
|
|
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
|
1030 |
|
|
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
|
1031 |
|
|
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
|
1032 |
|
|
.dbg_sel_po_incdec (dbg_sel_po_incdec),
|
1033 |
|
|
.dbg_byte_sel (dbg_byte_sel),
|
1034 |
|
|
.dbg_pi_f_inc (dbg_pi_f_inc),
|
1035 |
|
|
.dbg_pi_f_dec (dbg_pi_f_dec),
|
1036 |
|
|
.dbg_po_f_inc (dbg_po_f_inc),
|
1037 |
|
|
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
|
1038 |
|
|
.dbg_po_f_dec (dbg_po_f_dec),
|
1039 |
|
|
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
|
1040 |
|
|
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
|
1041 |
|
|
.dbg_calib_top (dbg_calib_top),
|
1042 |
|
|
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
|
1043 |
|
|
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
|
1044 |
|
|
.dbg_rd_data_offset (dbg_rd_data_offset),
|
1045 |
|
|
.dbg_phy_rdlvl (dbg_phy_rdlvl),
|
1046 |
|
|
.dbg_phy_wrcal (dbg_phy_wrcal),
|
1047 |
|
|
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
|
1048 |
|
|
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
|
1049 |
|
|
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
|
1050 |
|
|
.dbg_rddata (dbg_rddata),
|
1051 |
|
|
.dbg_rddata_valid (dbg_rddata_valid),
|
1052 |
|
|
.dbg_rdlvl_done (dbg_rdlvl_done),
|
1053 |
|
|
.dbg_rdlvl_err (dbg_rdlvl_err),
|
1054 |
|
|
.dbg_rdlvl_start (dbg_rdlvl_start),
|
1055 |
|
|
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
|
1056 |
|
|
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
|
1057 |
|
|
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
|
1058 |
|
|
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
|
1059 |
|
|
.dbg_wrlvl_done (dbg_wrlvl_done),
|
1060 |
|
|
.dbg_wrlvl_err (dbg_wrlvl_err),
|
1061 |
|
|
.dbg_wrlvl_start (dbg_wrlvl_start),
|
1062 |
|
|
.dbg_phy_wrlvl (dbg_phy_wrlvl),
|
1063 |
|
|
.dbg_phy_init (dbg_phy_init),
|
1064 |
|
|
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
|
1065 |
|
|
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
|
1066 |
|
|
.dbg_po_counter_read_val (dbg_po_counter_read_val),
|
1067 |
|
|
.dbg_prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r_int),
|
1068 |
|
|
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps_int),
|
1069 |
|
|
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps_int),
|
1070 |
|
|
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
|
1071 |
|
|
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
|
1072 |
|
|
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
|
1073 |
|
|
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
|
1074 |
|
|
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
|
1075 |
|
|
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
|
1076 |
|
|
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
|
1077 |
|
|
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
|
1078 |
|
|
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
|
1079 |
|
|
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
|
1080 |
|
|
.dbg_data_offset (dbg_data_offset),
|
1081 |
|
|
.dbg_data_offset_1 (dbg_data_offset_1),
|
1082 |
|
|
.dbg_data_offset_2 (dbg_data_offset_2),
|
1083 |
|
|
.dbg_wrcal_start (dbg_wrcal_start),
|
1084 |
|
|
.dbg_wrcal_done (dbg_wrcal_done),
|
1085 |
|
|
.dbg_wrcal_err (dbg_wrcal_err),
|
1086 |
|
|
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
|
1087 |
|
|
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
|
1088 |
|
|
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
|
1089 |
|
|
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
|
1090 |
|
|
.dbg_dqs_found_cal (dbg_dqs_found_cal),
|
1091 |
|
|
.init_calib_complete (init_calib_complete)
|
1092 |
|
|
);
|
1093 |
|
|
|
1094 |
|
|
|
1095 |
|
|
|
1096 |
|
|
|
1097 |
|
|
|
1098 |
|
|
|
1099 |
|
|
//*********************************************************************
|
1100 |
|
|
// Resetting all RTL debug inputs as the debug ports are not enabled
|
1101 |
|
|
//*********************************************************************
|
1102 |
|
|
assign dbg_idel_down_all = 1'b0;
|
1103 |
|
|
assign dbg_idel_down_cpt = 1'b0;
|
1104 |
|
|
assign dbg_idel_up_all = 1'b0;
|
1105 |
|
|
assign dbg_idel_up_cpt = 1'b0;
|
1106 |
|
|
assign dbg_sel_all_idel_cpt = 1'b0;
|
1107 |
|
|
assign dbg_sel_idel_cpt = 'b0;
|
1108 |
|
|
assign dbg_byte_sel = 'd0;
|
1109 |
|
|
assign dbg_sel_pi_incdec = 1'b0;
|
1110 |
|
|
assign dbg_pi_f_inc = 1'b0;
|
1111 |
|
|
assign dbg_pi_f_dec = 1'b0;
|
1112 |
|
|
assign dbg_po_f_inc = 'b0;
|
1113 |
|
|
assign dbg_po_f_dec = 'b0;
|
1114 |
|
|
assign dbg_po_f_stg23_sel = 'b0;
|
1115 |
|
|
assign dbg_sel_po_incdec = 'b0;
|
1116 |
|
|
|
1117 |
|
|
|
1118 |
|
|
|
1119 |
|
|
endmodule
|