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//*****************************************************************************
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// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version:
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// \ \ Application: MIG
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// / / Filename: ddr_phy_dqs_found_cal.v
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// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $
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// \ \ / \ Date Created:
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// \___\/\___\
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//
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//Device: 7 Series
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//Design Name: DDR3 SDRAM
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//Purpose:
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// Read leveling calibration logic
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// NOTES:
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// 1. Phaser_In DQSFOUND calibration
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//Reference:
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//Revision History:
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//*****************************************************************************
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/******************************************************************************
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**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $
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**$Date: 2011/06/02 08:35:08 $
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**$Author:
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**$Revision:
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**$Source:
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******************************************************************************/
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`timescale 1ps/1ps
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module mig_7series_v2_3_ddr_phy_dqs_found_cal #
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(
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parameter TCQ = 100, // clk->out delay (sim only)
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parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
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parameter nCL = 5, // Read CAS latency
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parameter AL = "0",
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parameter nCWL = 5, // Write CAS latency
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parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
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parameter RANKS = 1, // # of memory ranks in the system
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parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
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parameter DQS_WIDTH = 8, // # of DQS (strobe)
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parameter DRAM_WIDTH = 8, // # of DQ per DQS
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parameter REG_CTRL = "ON", // "ON" for registered DIMM
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parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
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parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate
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parameter N_CTL_LANES = 3, // Number of control byte lanes
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parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)
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parameter HIGHEST_BANK = 3, // Sum of I/O Banks
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parameter BYTE_LANES_B0 = 4'b1111,
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parameter BYTE_LANES_B1 = 4'b0000,
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parameter BYTE_LANES_B2 = 4'b0000,
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parameter BYTE_LANES_B3 = 4'b0000,
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parameter BYTE_LANES_B4 = 4'b0000,
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parameter DATA_CTL_B0 = 4'hc,
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parameter DATA_CTL_B1 = 4'hf,
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parameter DATA_CTL_B2 = 4'hf,
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parameter DATA_CTL_B3 = 4'hf,
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parameter DATA_CTL_B4 = 4'hf
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)
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(
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input clk,
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input rst,
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input dqsfound_retry,
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// From phy_init
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input pi_dqs_found_start,
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input detect_pi_found_dqs,
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input prech_done,
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// DQSFOUND per Phaser_IN
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input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
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output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
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// To phy_init
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output [5:0] rd_data_offset_0,
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output [5:0] rd_data_offset_1,
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output [5:0] rd_data_offset_2,
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output pi_dqs_found_rank_done,
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output pi_dqs_found_done,
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output reg pi_dqs_found_err,
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output [6*RANKS-1:0] rd_data_offset_ranks_0,
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output [6*RANKS-1:0] rd_data_offset_ranks_1,
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output [6*RANKS-1:0] rd_data_offset_ranks_2,
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output reg dqsfound_retry_done,
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output reg dqs_found_prech_req,
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//To MC
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output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,
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output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,
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output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,
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input [8:0] po_counter_read_val,
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output rd_data_offset_cal_done,
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output fine_adjust_done,
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output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,
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output reg ck_po_stg2_f_indec,
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output reg ck_po_stg2_f_en,
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output [255:0] dbg_dqs_found_cal
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);
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// For non-zero AL values
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localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
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// Adding the register dimm latency to write latency
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localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
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// Added to reduce simulation time
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localparam LATENCY_FACTOR = 13;
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localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1;
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localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),
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(DATA_CTL_B4[2] & BYTE_LANES_B4[2]),
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(DATA_CTL_B4[1] & BYTE_LANES_B4[1]),
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(DATA_CTL_B4[0] & BYTE_LANES_B4[0]),
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(DATA_CTL_B3[3] & BYTE_LANES_B3[3]),
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(DATA_CTL_B3[2] & BYTE_LANES_B3[2]),
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(DATA_CTL_B3[1] & BYTE_LANES_B3[1]),
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(DATA_CTL_B3[0] & BYTE_LANES_B3[0]),
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(DATA_CTL_B2[3] & BYTE_LANES_B2[3]),
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(DATA_CTL_B2[2] & BYTE_LANES_B2[2]),
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(DATA_CTL_B2[1] & BYTE_LANES_B2[1]),
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(DATA_CTL_B2[0] & BYTE_LANES_B2[0]),
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(DATA_CTL_B1[3] & BYTE_LANES_B1[3]),
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(DATA_CTL_B1[2] & BYTE_LANES_B1[2]),
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(DATA_CTL_B1[1] & BYTE_LANES_B1[1]),
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(DATA_CTL_B1[0] & BYTE_LANES_B1[0]),
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(DATA_CTL_B0[3] & BYTE_LANES_B0[3]),
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(DATA_CTL_B0[2] & BYTE_LANES_B0[2]),
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(DATA_CTL_B0[1] & BYTE_LANES_B0[1]),
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(DATA_CTL_B0[0] & BYTE_LANES_B0[0])};
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localparam FINE_ADJ_IDLE = 4'h0;
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localparam RST_POSTWAIT = 4'h1;
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localparam RST_POSTWAIT1 = 4'h2;
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localparam RST_WAIT = 4'h3;
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localparam FINE_ADJ_INIT = 4'h4;
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localparam FINE_INC = 4'h5;
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localparam FINE_INC_WAIT = 4'h6;
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localparam FINE_INC_PREWAIT = 4'h7;
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localparam DETECT_PREWAIT = 4'h8;
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localparam DETECT_DQSFOUND = 4'h9;
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localparam PRECH_WAIT = 4'hA;
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localparam FINE_DEC = 4'hB;
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localparam FINE_DEC_WAIT = 4'hC;
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localparam FINE_DEC_PREWAIT = 4'hD;
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localparam FINAL_WAIT = 4'hE;
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localparam FINE_ADJ_DONE = 4'hF;
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integer k,l,m,n,p,q,r,s;
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reg dqs_found_start_r;
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reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];
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reg rank_done_r;
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reg rank_done_r1;
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reg dqs_found_done_r;
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(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;
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(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;
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(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;
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reg init_dqsfound_done_r;
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reg init_dqsfound_done_r1;
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reg init_dqsfound_done_r2;
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reg init_dqsfound_done_r3;
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reg init_dqsfound_done_r4;
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reg init_dqsfound_done_r5;
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reg [1:0] rnk_cnt_r;
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reg [2:0 ] final_do_index[0:RANKS-1];
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reg [5:0 ] final_do_max[0:RANKS-1];
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reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];
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reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];
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reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;
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reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;
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reg [10*HIGHEST_BANK-1:0] retry_cnt;
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reg dqsfound_retry_r1;
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wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;
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reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;
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reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;
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reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;
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reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;
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reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;
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// CK/Control byte lanes fine adjust stage
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reg fine_adjust;
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reg [N_CTL_LANES-1:0] ctl_lane_cnt;
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reg [3:0] fine_adj_state_r;
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reg fine_adjust_done_r;
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reg rst_dqs_find;
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reg rst_dqs_find_r1;
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reg rst_dqs_find_r2;
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reg [5:0] init_dec_cnt;
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reg [5:0] dec_cnt;
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reg [5:0] inc_cnt;
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reg final_dec_done;
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reg init_dec_done;
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reg first_fail_detect;
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reg second_fail_detect;
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reg [5:0] first_fail_taps;
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reg [5:0] second_fail_taps;
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reg [5:0] stable_pass_cnt;
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reg [3:0] detect_rd_cnt;
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//***************************************************************************
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// Debug signals
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//
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//***************************************************************************
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assign dbg_dqs_found_cal[5:0] = first_fail_taps;
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assign dbg_dqs_found_cal[11:6] = second_fail_taps;
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assign dbg_dqs_found_cal[12] = first_fail_detect;
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assign dbg_dqs_found_cal[13] = second_fail_detect;
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assign dbg_dqs_found_cal[14] = fine_adjust_done_r;
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assign pi_dqs_found_rank_done = rank_done_r;
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assign pi_dqs_found_done = dqs_found_done_r;
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generate
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genvar rnk_cnt;
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if (HIGHEST_BANK == 3) begin // Three Bank Interface
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for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
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assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
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assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
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assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];
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assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
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assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
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assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];
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end
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end else if (HIGHEST_BANK == 2) begin // Two Bank Interface
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for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
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assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
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assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
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assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
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assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
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assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
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assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
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|
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end
|
287 |
|
|
end else begin // Single Bank Interface
|
288 |
|
|
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
|
289 |
|
|
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
|
290 |
|
|
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;
|
291 |
|
|
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
|
292 |
|
|
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
|
293 |
|
|
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;
|
294 |
|
|
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
|
295 |
|
|
end
|
296 |
|
|
end
|
297 |
|
|
endgenerate
|
298 |
|
|
|
299 |
|
|
// final_data_offset is used during write calibration and during
|
300 |
|
|
// normal operation. One rd_data_offset value per rank for entire
|
301 |
|
|
// interface
|
302 |
|
|
generate
|
303 |
|
|
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
|
304 |
|
|
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
|
305 |
|
|
final_data_offset[rnk_cnt_r][0+:6];
|
306 |
|
|
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
|
307 |
|
|
final_data_offset[rnk_cnt_r][6+:6];
|
308 |
|
|
assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :
|
309 |
|
|
final_data_offset[rnk_cnt_r][12+:6];
|
310 |
|
|
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
|
311 |
|
|
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
|
312 |
|
|
final_data_offset[rnk_cnt_r][0+:6];
|
313 |
|
|
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
|
314 |
|
|
final_data_offset[rnk_cnt_r][6+:6];
|
315 |
|
|
assign rd_data_offset_2 = 'd0;
|
316 |
|
|
end else begin
|
317 |
|
|
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
|
318 |
|
|
final_data_offset[rnk_cnt_r][0+:6];
|
319 |
|
|
assign rd_data_offset_1 = 'd0;
|
320 |
|
|
assign rd_data_offset_2 = 'd0;
|
321 |
|
|
end
|
322 |
|
|
endgenerate
|
323 |
|
|
|
324 |
|
|
assign rd_data_offset_cal_done = init_dqsfound_done_r;
|
325 |
|
|
assign fine_adjust_lane_cnt = ctl_lane_cnt;
|
326 |
|
|
|
327 |
|
|
//**************************************************************************
|
328 |
|
|
// DQSFOUND all and any generation
|
329 |
|
|
// pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are
|
330 |
|
|
// asserted
|
331 |
|
|
// pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx
|
332 |
|
|
// is asserted
|
333 |
|
|
//**************************************************************************
|
334 |
|
|
|
335 |
|
|
generate
|
336 |
|
|
if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))
|
337 |
|
|
assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;
|
338 |
|
|
else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))
|
339 |
|
|
assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};
|
340 |
|
|
else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))
|
341 |
|
|
assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};
|
342 |
|
|
else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))
|
343 |
|
|
assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};
|
344 |
|
|
endgenerate
|
345 |
|
|
|
346 |
|
|
always @(posedge clk) begin
|
347 |
|
|
if (rst) begin
|
348 |
|
|
for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found
|
349 |
|
|
pi_dqs_found_all_bank[k] <= #TCQ 'b0;
|
350 |
|
|
pi_dqs_found_any_bank[k] <= #TCQ 'b0;
|
351 |
|
|
end
|
352 |
|
|
end else if (pi_dqs_found_start) begin
|
353 |
|
|
for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found
|
354 |
|
|
pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &
|
355 |
|
|
(!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &
|
356 |
|
|
(!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &
|
357 |
|
|
(!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);
|
358 |
|
|
pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |
|
359 |
|
|
(DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |
|
360 |
|
|
(DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |
|
361 |
|
|
(DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);
|
362 |
|
|
end
|
363 |
|
|
end
|
364 |
|
|
end
|
365 |
|
|
|
366 |
|
|
|
367 |
|
|
always @(posedge clk) begin
|
368 |
|
|
pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;
|
369 |
|
|
pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;
|
370 |
|
|
end
|
371 |
|
|
|
372 |
|
|
//*****************************************************************************
|
373 |
|
|
// Counter to increase number of 4 back-to-back reads per rd_data_offset and
|
374 |
|
|
// per CK/A/C tap value
|
375 |
|
|
//*****************************************************************************
|
376 |
|
|
|
377 |
|
|
always @(posedge clk) begin
|
378 |
|
|
if (rst || (detect_rd_cnt == 'd0))
|
379 |
|
|
detect_rd_cnt <= #TCQ NUM_READS;
|
380 |
|
|
else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
|
381 |
|
|
detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
|
382 |
|
|
end
|
383 |
|
|
|
384 |
|
|
|
385 |
|
|
//**************************************************************************
|
386 |
|
|
// Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls
|
387 |
|
|
//
|
388 |
|
|
//**************************************************************************
|
389 |
|
|
|
390 |
|
|
assign fine_adjust_done = fine_adjust_done_r;
|
391 |
|
|
|
392 |
|
|
always @(posedge clk) begin
|
393 |
|
|
rst_dqs_find_r1 <= #TCQ rst_dqs_find;
|
394 |
|
|
rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;
|
395 |
|
|
end
|
396 |
|
|
|
397 |
|
|
always @(posedge clk) begin
|
398 |
|
|
if(rst)begin
|
399 |
|
|
fine_adjust <= #TCQ 1'b0;
|
400 |
|
|
ctl_lane_cnt <= #TCQ 'd0;
|
401 |
|
|
fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;
|
402 |
|
|
fine_adjust_done_r <= #TCQ 1'b0;
|
403 |
|
|
ck_po_stg2_f_indec <= #TCQ 1'b0;
|
404 |
|
|
ck_po_stg2_f_en <= #TCQ 1'b0;
|
405 |
|
|
rst_dqs_find <= #TCQ 1'b0;
|
406 |
|
|
init_dec_cnt <= #TCQ 'd31;
|
407 |
|
|
dec_cnt <= #TCQ 'd0;
|
408 |
|
|
inc_cnt <= #TCQ 'd0;
|
409 |
|
|
init_dec_done <= #TCQ 1'b0;
|
410 |
|
|
final_dec_done <= #TCQ 1'b0;
|
411 |
|
|
first_fail_detect <= #TCQ 1'b0;
|
412 |
|
|
second_fail_detect <= #TCQ 1'b0;
|
413 |
|
|
first_fail_taps <= #TCQ 'd0;
|
414 |
|
|
second_fail_taps <= #TCQ 'd0;
|
415 |
|
|
stable_pass_cnt <= #TCQ 'd0;
|
416 |
|
|
dqs_found_prech_req<= #TCQ 1'b0;
|
417 |
|
|
end else begin
|
418 |
|
|
case (fine_adj_state_r)
|
419 |
|
|
|
420 |
|
|
FINE_ADJ_IDLE: begin
|
421 |
|
|
if (init_dqsfound_done_r5) begin
|
422 |
|
|
if (SIM_CAL_OPTION == "FAST_CAL") begin
|
423 |
|
|
fine_adjust <= #TCQ 1'b1;
|
424 |
|
|
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
|
425 |
|
|
rst_dqs_find <= #TCQ 1'b0;
|
426 |
|
|
end else begin
|
427 |
|
|
fine_adjust <= #TCQ 1'b1;
|
428 |
|
|
fine_adj_state_r <= #TCQ RST_WAIT;
|
429 |
|
|
rst_dqs_find <= #TCQ 1'b1;
|
430 |
|
|
end
|
431 |
|
|
end
|
432 |
|
|
end
|
433 |
|
|
|
434 |
|
|
RST_WAIT: begin
|
435 |
|
|
if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin
|
436 |
|
|
rst_dqs_find <= #TCQ 1'b0;
|
437 |
|
|
if (|init_dec_cnt)
|
438 |
|
|
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
|
439 |
|
|
else if (final_dec_done)
|
440 |
|
|
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
|
441 |
|
|
else
|
442 |
|
|
fine_adj_state_r <= #TCQ RST_POSTWAIT;
|
443 |
|
|
end
|
444 |
|
|
end
|
445 |
|
|
|
446 |
|
|
RST_POSTWAIT: begin
|
447 |
|
|
fine_adj_state_r <= #TCQ RST_POSTWAIT1;
|
448 |
|
|
end
|
449 |
|
|
|
450 |
|
|
RST_POSTWAIT1: begin
|
451 |
|
|
fine_adj_state_r <= #TCQ FINE_ADJ_INIT;
|
452 |
|
|
end
|
453 |
|
|
|
454 |
|
|
FINE_ADJ_INIT: begin
|
455 |
|
|
//if (detect_pi_found_dqs && (inc_cnt < 'd63))
|
456 |
|
|
fine_adj_state_r <= #TCQ FINE_INC;
|
457 |
|
|
end
|
458 |
|
|
|
459 |
|
|
FINE_INC: begin
|
460 |
|
|
fine_adj_state_r <= #TCQ FINE_INC_WAIT;
|
461 |
|
|
ck_po_stg2_f_indec <= #TCQ 1'b1;
|
462 |
|
|
ck_po_stg2_f_en <= #TCQ 1'b1;
|
463 |
|
|
if (ctl_lane_cnt == N_CTL_LANES-1)
|
464 |
|
|
inc_cnt <= #TCQ inc_cnt + 1;
|
465 |
|
|
end
|
466 |
|
|
|
467 |
|
|
FINE_INC_WAIT: begin
|
468 |
|
|
ck_po_stg2_f_indec <= #TCQ 1'b0;
|
469 |
|
|
ck_po_stg2_f_en <= #TCQ 1'b0;
|
470 |
|
|
if (ctl_lane_cnt != N_CTL_LANES-1) begin
|
471 |
|
|
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
|
472 |
|
|
fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;
|
473 |
|
|
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
|
474 |
|
|
ctl_lane_cnt <= #TCQ 'd0;
|
475 |
|
|
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
|
476 |
|
|
end
|
477 |
|
|
end
|
478 |
|
|
|
479 |
|
|
FINE_INC_PREWAIT: begin
|
480 |
|
|
fine_adj_state_r <= #TCQ FINE_INC;
|
481 |
|
|
end
|
482 |
|
|
|
483 |
|
|
DETECT_PREWAIT: begin
|
484 |
|
|
if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))
|
485 |
|
|
fine_adj_state_r <= #TCQ DETECT_DQSFOUND;
|
486 |
|
|
else
|
487 |
|
|
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
|
488 |
|
|
end
|
489 |
|
|
|
490 |
|
|
DETECT_DQSFOUND: begin
|
491 |
|
|
if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin
|
492 |
|
|
stable_pass_cnt <= #TCQ 'd0;
|
493 |
|
|
if (~first_fail_detect && (inc_cnt == 'd63)) begin
|
494 |
|
|
// First failing tap detected at 63 taps
|
495 |
|
|
// then decrement to 31
|
496 |
|
|
first_fail_detect <= #TCQ 1'b1;
|
497 |
|
|
first_fail_taps <= #TCQ inc_cnt;
|
498 |
|
|
fine_adj_state_r <= #TCQ FINE_DEC;
|
499 |
|
|
dec_cnt <= #TCQ 'd32;
|
500 |
|
|
end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin
|
501 |
|
|
// First failing tap detected at greater than 30 taps
|
502 |
|
|
// then stop looking for second edge and decrement
|
503 |
|
|
first_fail_detect <= #TCQ 1'b1;
|
504 |
|
|
first_fail_taps <= #TCQ inc_cnt;
|
505 |
|
|
fine_adj_state_r <= #TCQ FINE_DEC;
|
506 |
|
|
dec_cnt <= #TCQ (inc_cnt>>1) + 1;
|
507 |
|
|
end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin
|
508 |
|
|
// First failing tap detected, continue incrementing
|
509 |
|
|
// until either second failing tap detected or 63
|
510 |
|
|
first_fail_detect <= #TCQ 1'b1;
|
511 |
|
|
first_fail_taps <= #TCQ inc_cnt;
|
512 |
|
|
rst_dqs_find <= #TCQ 1'b1;
|
513 |
|
|
if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin
|
514 |
|
|
dqs_found_prech_req <= #TCQ 1'b1;
|
515 |
|
|
fine_adj_state_r <= #TCQ PRECH_WAIT;
|
516 |
|
|
end else
|
517 |
|
|
fine_adj_state_r <= #TCQ RST_WAIT;
|
518 |
|
|
end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin
|
519 |
|
|
// Consecutive 30 taps of passing region was not found
|
520 |
|
|
// continue incrementing
|
521 |
|
|
first_fail_detect <= #TCQ 1'b1;
|
522 |
|
|
first_fail_taps <= #TCQ inc_cnt;
|
523 |
|
|
rst_dqs_find <= #TCQ 1'b1;
|
524 |
|
|
if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
|
525 |
|
|
dqs_found_prech_req <= #TCQ 1'b1;
|
526 |
|
|
fine_adj_state_r <= #TCQ PRECH_WAIT;
|
527 |
|
|
end else
|
528 |
|
|
fine_adj_state_r <= #TCQ RST_WAIT;
|
529 |
|
|
end else if (first_fail_detect && (inc_cnt == 'd63)) begin
|
530 |
|
|
if (stable_pass_cnt < 'd30) begin
|
531 |
|
|
// Consecutive 30 taps of passing region was not found
|
532 |
|
|
// from tap 0 to 63 so decrement back to 31
|
533 |
|
|
first_fail_detect <= #TCQ 1'b1;
|
534 |
|
|
first_fail_taps <= #TCQ inc_cnt;
|
535 |
|
|
fine_adj_state_r <= #TCQ FINE_DEC;
|
536 |
|
|
dec_cnt <= #TCQ 'd32;
|
537 |
|
|
end else begin
|
538 |
|
|
// Consecutive 30 taps of passing region was found
|
539 |
|
|
// between first_fail_taps and 63
|
540 |
|
|
fine_adj_state_r <= #TCQ FINE_DEC;
|
541 |
|
|
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
|
542 |
|
|
end
|
543 |
|
|
end else begin
|
544 |
|
|
// Second failing tap detected, decrement to center of
|
545 |
|
|
// failing taps
|
546 |
|
|
second_fail_detect <= #TCQ 1'b1;
|
547 |
|
|
second_fail_taps <= #TCQ inc_cnt;
|
548 |
|
|
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
|
549 |
|
|
fine_adj_state_r <= #TCQ FINE_DEC;
|
550 |
|
|
end
|
551 |
|
|
end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin
|
552 |
|
|
stable_pass_cnt <= #TCQ stable_pass_cnt + 1;
|
553 |
|
|
if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) ||
|
554 |
|
|
(inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
|
555 |
|
|
dqs_found_prech_req <= #TCQ 1'b1;
|
556 |
|
|
fine_adj_state_r <= #TCQ PRECH_WAIT;
|
557 |
|
|
end else if (inc_cnt < 'd63) begin
|
558 |
|
|
rst_dqs_find <= #TCQ 1'b1;
|
559 |
|
|
fine_adj_state_r <= #TCQ RST_WAIT;
|
560 |
|
|
end else begin
|
561 |
|
|
fine_adj_state_r <= #TCQ FINE_DEC;
|
562 |
|
|
if (~first_fail_detect || (first_fail_taps > 'd33))
|
563 |
|
|
// No failing taps detected, decrement by 31
|
564 |
|
|
dec_cnt <= #TCQ 'd32;
|
565 |
|
|
//else if (first_fail_detect && (stable_pass_cnt > 'd28))
|
566 |
|
|
// // First failing tap detected between 0 and 34
|
567 |
|
|
// // decrement midpoint between 63 and failing tap
|
568 |
|
|
// dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
|
569 |
|
|
else
|
570 |
|
|
// First failing tap detected
|
571 |
|
|
// decrement to midpoint between 63 and failing tap
|
572 |
|
|
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
|
573 |
|
|
end
|
574 |
|
|
end
|
575 |
|
|
end
|
576 |
|
|
|
577 |
|
|
PRECH_WAIT: begin
|
578 |
|
|
if (prech_done) begin
|
579 |
|
|
dqs_found_prech_req <= #TCQ 1'b0;
|
580 |
|
|
rst_dqs_find <= #TCQ 1'b1;
|
581 |
|
|
fine_adj_state_r <= #TCQ RST_WAIT;
|
582 |
|
|
end
|
583 |
|
|
end
|
584 |
|
|
|
585 |
|
|
|
586 |
|
|
FINE_DEC: begin
|
587 |
|
|
fine_adj_state_r <= #TCQ FINE_DEC_WAIT;
|
588 |
|
|
ck_po_stg2_f_indec <= #TCQ 1'b0;
|
589 |
|
|
ck_po_stg2_f_en <= #TCQ 1'b1;
|
590 |
|
|
if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))
|
591 |
|
|
init_dec_cnt <= #TCQ init_dec_cnt - 1;
|
592 |
|
|
else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))
|
593 |
|
|
dec_cnt <= #TCQ dec_cnt - 1;
|
594 |
|
|
end
|
595 |
|
|
|
596 |
|
|
FINE_DEC_WAIT: begin
|
597 |
|
|
ck_po_stg2_f_indec <= #TCQ 1'b0;
|
598 |
|
|
ck_po_stg2_f_en <= #TCQ 1'b0;
|
599 |
|
|
if (ctl_lane_cnt != N_CTL_LANES-1) begin
|
600 |
|
|
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
|
601 |
|
|
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
|
602 |
|
|
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
|
603 |
|
|
ctl_lane_cnt <= #TCQ 'd0;
|
604 |
|
|
if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))
|
605 |
|
|
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
|
606 |
|
|
else begin
|
607 |
|
|
fine_adj_state_r <= #TCQ FINAL_WAIT;
|
608 |
|
|
if ((init_dec_cnt == 'd0) && ~init_dec_done)
|
609 |
|
|
init_dec_done <= #TCQ 1'b1;
|
610 |
|
|
else
|
611 |
|
|
final_dec_done <= #TCQ 1'b1;
|
612 |
|
|
end
|
613 |
|
|
end
|
614 |
|
|
end
|
615 |
|
|
|
616 |
|
|
FINE_DEC_PREWAIT: begin
|
617 |
|
|
fine_adj_state_r <= #TCQ FINE_DEC;
|
618 |
|
|
end
|
619 |
|
|
|
620 |
|
|
FINAL_WAIT: begin
|
621 |
|
|
rst_dqs_find <= #TCQ 1'b1;
|
622 |
|
|
fine_adj_state_r <= #TCQ RST_WAIT;
|
623 |
|
|
end
|
624 |
|
|
|
625 |
|
|
FINE_ADJ_DONE: begin
|
626 |
|
|
if (&pi_dqs_found_all_bank) begin
|
627 |
|
|
fine_adjust_done_r <= #TCQ 1'b1;
|
628 |
|
|
rst_dqs_find <= #TCQ 1'b0;
|
629 |
|
|
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
|
630 |
|
|
end
|
631 |
|
|
end
|
632 |
|
|
|
633 |
|
|
endcase
|
634 |
|
|
end
|
635 |
|
|
end
|
636 |
|
|
|
637 |
|
|
|
638 |
|
|
|
639 |
|
|
|
640 |
|
|
//*****************************************************************************
|
641 |
|
|
|
642 |
|
|
|
643 |
|
|
always@(posedge clk)
|
644 |
|
|
dqs_found_start_r <= #TCQ pi_dqs_found_start;
|
645 |
|
|
|
646 |
|
|
|
647 |
|
|
always @(posedge clk) begin
|
648 |
|
|
if (rst)
|
649 |
|
|
rnk_cnt_r <= #TCQ 2'b00;
|
650 |
|
|
else if (init_dqsfound_done_r)
|
651 |
|
|
rnk_cnt_r <= #TCQ rnk_cnt_r;
|
652 |
|
|
else if (rank_done_r)
|
653 |
|
|
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
|
654 |
|
|
end
|
655 |
|
|
|
656 |
|
|
//*****************************************************************
|
657 |
|
|
// Read data_offset calibration done signal
|
658 |
|
|
//*****************************************************************
|
659 |
|
|
|
660 |
|
|
always @(posedge clk) begin
|
661 |
|
|
if (rst || (|pi_rst_stg1_cal_r))
|
662 |
|
|
init_dqsfound_done_r <= #TCQ 1'b0;
|
663 |
|
|
else if (&pi_dqs_found_all_bank) begin
|
664 |
|
|
if (rnk_cnt_r == RANKS-1)
|
665 |
|
|
init_dqsfound_done_r <= #TCQ 1'b1;
|
666 |
|
|
else
|
667 |
|
|
init_dqsfound_done_r <= #TCQ 1'b0;
|
668 |
|
|
end
|
669 |
|
|
end
|
670 |
|
|
|
671 |
|
|
always @(posedge clk) begin
|
672 |
|
|
if (rst ||
|
673 |
|
|
(init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))
|
674 |
|
|
rank_done_r <= #TCQ 1'b0;
|
675 |
|
|
else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))
|
676 |
|
|
rank_done_r <= #TCQ 1'b1;
|
677 |
|
|
else
|
678 |
|
|
rank_done_r <= #TCQ 1'b0;
|
679 |
|
|
end
|
680 |
|
|
|
681 |
|
|
always @(posedge clk) begin
|
682 |
|
|
pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;
|
683 |
|
|
pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;
|
684 |
|
|
pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;
|
685 |
|
|
init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;
|
686 |
|
|
init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;
|
687 |
|
|
init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;
|
688 |
|
|
init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;
|
689 |
|
|
init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;
|
690 |
|
|
rank_done_r1 <= #TCQ rank_done_r;
|
691 |
|
|
dqsfound_retry_r1 <= #TCQ dqsfound_retry;
|
692 |
|
|
end
|
693 |
|
|
|
694 |
|
|
|
695 |
|
|
always @(posedge clk) begin
|
696 |
|
|
if (rst)
|
697 |
|
|
dqs_found_done_r <= #TCQ 1'b0;
|
698 |
|
|
else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&
|
699 |
|
|
(fine_adj_state_r == FINE_ADJ_DONE))
|
700 |
|
|
dqs_found_done_r <= #TCQ 1'b1;
|
701 |
|
|
else
|
702 |
|
|
dqs_found_done_r <= #TCQ 1'b0;
|
703 |
|
|
end
|
704 |
|
|
|
705 |
|
|
|
706 |
|
|
generate
|
707 |
|
|
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
|
708 |
|
|
|
709 |
|
|
// Reset read data offset calibration in all DQS Phaser_INs
|
710 |
|
|
// in a Bank after the read data offset value for a rank is determined
|
711 |
|
|
// or if within a Bank DQSFOUND is not asserted for all DQSs
|
712 |
|
|
always @(posedge clk) begin
|
713 |
|
|
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
|
714 |
|
|
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
|
715 |
|
|
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
|
716 |
|
|
//(dqsfound_retry[0]) ||
|
717 |
|
|
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
|
718 |
|
|
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
|
719 |
|
|
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
|
720 |
|
|
end
|
721 |
|
|
|
722 |
|
|
always @(posedge clk) begin
|
723 |
|
|
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
|
724 |
|
|
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
|
725 |
|
|
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
|
726 |
|
|
//(dqsfound_retry[1]) ||
|
727 |
|
|
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
|
728 |
|
|
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
|
729 |
|
|
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
|
730 |
|
|
end
|
731 |
|
|
|
732 |
|
|
always @(posedge clk) begin
|
733 |
|
|
if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)
|
734 |
|
|
pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;
|
735 |
|
|
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
|
736 |
|
|
//(dqsfound_retry[2]) ||
|
737 |
|
|
(pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||
|
738 |
|
|
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
|
739 |
|
|
pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;
|
740 |
|
|
end
|
741 |
|
|
|
742 |
|
|
always @(posedge clk) begin
|
743 |
|
|
if (rst || fine_adjust)
|
744 |
|
|
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
|
745 |
|
|
else if (pi_rst_stg1_cal_r[0])
|
746 |
|
|
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
|
747 |
|
|
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
|
748 |
|
|
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
|
749 |
|
|
end
|
750 |
|
|
|
751 |
|
|
always @(posedge clk) begin
|
752 |
|
|
if (rst || fine_adjust)
|
753 |
|
|
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
|
754 |
|
|
else if (pi_rst_stg1_cal_r[1])
|
755 |
|
|
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
|
756 |
|
|
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
|
757 |
|
|
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
|
758 |
|
|
end
|
759 |
|
|
|
760 |
|
|
always @(posedge clk) begin
|
761 |
|
|
if (rst || fine_adjust)
|
762 |
|
|
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
|
763 |
|
|
else if (pi_rst_stg1_cal_r[2])
|
764 |
|
|
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;
|
765 |
|
|
else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])
|
766 |
|
|
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
|
767 |
|
|
end
|
768 |
|
|
|
769 |
|
|
//*****************************************************************************
|
770 |
|
|
// Retry counter to track number of DQSFOUND retries
|
771 |
|
|
//*****************************************************************************
|
772 |
|
|
|
773 |
|
|
always @(posedge clk) begin
|
774 |
|
|
if (rst || rank_done_r)
|
775 |
|
|
retry_cnt[0+:10] <= #TCQ 'b0;
|
776 |
|
|
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
|
777 |
|
|
~pi_dqs_found_all_bank[0])
|
778 |
|
|
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
|
779 |
|
|
else
|
780 |
|
|
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
|
781 |
|
|
end
|
782 |
|
|
|
783 |
|
|
always @(posedge clk) begin
|
784 |
|
|
if (rst || rank_done_r)
|
785 |
|
|
retry_cnt[10+:10] <= #TCQ 'b0;
|
786 |
|
|
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) &&
|
787 |
|
|
~pi_dqs_found_all_bank[1])
|
788 |
|
|
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
|
789 |
|
|
else
|
790 |
|
|
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
|
791 |
|
|
end
|
792 |
|
|
|
793 |
|
|
always @(posedge clk) begin
|
794 |
|
|
if (rst || rank_done_r)
|
795 |
|
|
retry_cnt[20+:10] <= #TCQ 'b0;
|
796 |
|
|
else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)) &&
|
797 |
|
|
~pi_dqs_found_all_bank[2])
|
798 |
|
|
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;
|
799 |
|
|
else
|
800 |
|
|
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];
|
801 |
|
|
end
|
802 |
|
|
|
803 |
|
|
// Error generation in case pi_dqs_found_all_bank
|
804 |
|
|
// is not asserted
|
805 |
|
|
always @(posedge clk) begin
|
806 |
|
|
if (rst)
|
807 |
|
|
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
|
808 |
|
|
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
|
809 |
|
|
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
|
810 |
|
|
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
|
811 |
|
|
end
|
812 |
|
|
|
813 |
|
|
always @(posedge clk) begin
|
814 |
|
|
if (rst)
|
815 |
|
|
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
|
816 |
|
|
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
|
817 |
|
|
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
|
818 |
|
|
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
|
819 |
|
|
end
|
820 |
|
|
|
821 |
|
|
always @(posedge clk) begin
|
822 |
|
|
if (rst)
|
823 |
|
|
pi_dqs_found_err_r[2] <= #TCQ 1'b0;
|
824 |
|
|
else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&
|
825 |
|
|
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
|
826 |
|
|
pi_dqs_found_err_r[2] <= #TCQ 1'b1;
|
827 |
|
|
end
|
828 |
|
|
|
829 |
|
|
// Read data offset value for all DQS in a Bank
|
830 |
|
|
always @(posedge clk) begin
|
831 |
|
|
if (rst) begin
|
832 |
|
|
for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop
|
833 |
|
|
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
|
834 |
|
|
end
|
835 |
|
|
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
|
836 |
|
|
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
|
837 |
|
|
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
|
838 |
|
|
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
|
839 |
|
|
//(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) &&
|
840 |
|
|
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
|
841 |
|
|
rd_byte_data_offset[rnk_cnt_r][0+:6]
|
842 |
|
|
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1;
|
843 |
|
|
end
|
844 |
|
|
|
845 |
|
|
always @(posedge clk) begin
|
846 |
|
|
if (rst) begin
|
847 |
|
|
for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop
|
848 |
|
|
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
|
849 |
|
|
end
|
850 |
|
|
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
|
851 |
|
|
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
|
852 |
|
|
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
|
853 |
|
|
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
|
854 |
|
|
//(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) &&
|
855 |
|
|
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
|
856 |
|
|
rd_byte_data_offset[rnk_cnt_r][6+:6]
|
857 |
|
|
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1;
|
858 |
|
|
end
|
859 |
|
|
|
860 |
|
|
always @(posedge clk) begin
|
861 |
|
|
if (rst) begin
|
862 |
|
|
for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop
|
863 |
|
|
rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
|
864 |
|
|
end
|
865 |
|
|
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
|
866 |
|
|
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
|
867 |
|
|
rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
|
868 |
|
|
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&
|
869 |
|
|
//(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL -1)) &&
|
870 |
|
|
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
|
871 |
|
|
rd_byte_data_offset[rnk_cnt_r][12+:6]
|
872 |
|
|
<= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] - 1;
|
873 |
|
|
end
|
874 |
|
|
|
875 |
|
|
//*****************************************************************************
|
876 |
|
|
// Two I/O Bank Interface
|
877 |
|
|
//*****************************************************************************
|
878 |
|
|
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
|
879 |
|
|
|
880 |
|
|
// Reset read data offset calibration in all DQS Phaser_INs
|
881 |
|
|
// in a Bank after the read data offset value for a rank is determined
|
882 |
|
|
// or if within a Bank DQSFOUND is not asserted for all DQSs
|
883 |
|
|
always @(posedge clk) begin
|
884 |
|
|
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
|
885 |
|
|
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
|
886 |
|
|
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
|
887 |
|
|
//(dqsfound_retry[0]) ||
|
888 |
|
|
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
|
889 |
|
|
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
|
890 |
|
|
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
|
891 |
|
|
end
|
892 |
|
|
|
893 |
|
|
always @(posedge clk) begin
|
894 |
|
|
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
|
895 |
|
|
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
|
896 |
|
|
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
|
897 |
|
|
//(dqsfound_retry[1]) ||
|
898 |
|
|
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
|
899 |
|
|
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
|
900 |
|
|
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
|
901 |
|
|
end
|
902 |
|
|
|
903 |
|
|
always @(posedge clk) begin
|
904 |
|
|
if (rst || fine_adjust)
|
905 |
|
|
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
|
906 |
|
|
else if (pi_rst_stg1_cal_r[0])
|
907 |
|
|
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
|
908 |
|
|
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
|
909 |
|
|
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
|
910 |
|
|
end
|
911 |
|
|
|
912 |
|
|
always @(posedge clk) begin
|
913 |
|
|
if (rst || fine_adjust)
|
914 |
|
|
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
|
915 |
|
|
else if (pi_rst_stg1_cal_r[1])
|
916 |
|
|
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
|
917 |
|
|
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
|
918 |
|
|
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
|
919 |
|
|
end
|
920 |
|
|
|
921 |
|
|
//*****************************************************************************
|
922 |
|
|
// Retry counter to track number of DQSFOUND retries
|
923 |
|
|
//*****************************************************************************
|
924 |
|
|
|
925 |
|
|
always @(posedge clk) begin
|
926 |
|
|
if (rst || rank_done_r)
|
927 |
|
|
retry_cnt[0+:10] <= #TCQ 'b0;
|
928 |
|
|
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
|
929 |
|
|
~pi_dqs_found_all_bank[0])
|
930 |
|
|
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
|
931 |
|
|
else
|
932 |
|
|
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
|
933 |
|
|
end
|
934 |
|
|
|
935 |
|
|
always @(posedge clk) begin
|
936 |
|
|
if (rst || rank_done_r)
|
937 |
|
|
retry_cnt[10+:10] <= #TCQ 'b0;
|
938 |
|
|
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) &&
|
939 |
|
|
~pi_dqs_found_all_bank[1])
|
940 |
|
|
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
|
941 |
|
|
else
|
942 |
|
|
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
|
943 |
|
|
end
|
944 |
|
|
|
945 |
|
|
// Error generation in case pi_dqs_found_all_bank
|
946 |
|
|
// is not asserted
|
947 |
|
|
always @(posedge clk) begin
|
948 |
|
|
if (rst)
|
949 |
|
|
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
|
950 |
|
|
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
|
951 |
|
|
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
|
952 |
|
|
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
|
953 |
|
|
end
|
954 |
|
|
|
955 |
|
|
always @(posedge clk) begin
|
956 |
|
|
if (rst)
|
957 |
|
|
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
|
958 |
|
|
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
|
959 |
|
|
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
|
960 |
|
|
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
|
961 |
|
|
end
|
962 |
|
|
|
963 |
|
|
|
964 |
|
|
// Read data offset value for all DQS in a Bank
|
965 |
|
|
always @(posedge clk) begin
|
966 |
|
|
if (rst) begin
|
967 |
|
|
for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop
|
968 |
|
|
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
|
969 |
|
|
end
|
970 |
|
|
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
|
971 |
|
|
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
|
972 |
|
|
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
|
973 |
|
|
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
|
974 |
|
|
//(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) &&
|
975 |
|
|
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
|
976 |
|
|
rd_byte_data_offset[rnk_cnt_r][0+:6]
|
977 |
|
|
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1;
|
978 |
|
|
end
|
979 |
|
|
|
980 |
|
|
always @(posedge clk) begin
|
981 |
|
|
if (rst) begin
|
982 |
|
|
for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop
|
983 |
|
|
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
|
984 |
|
|
end
|
985 |
|
|
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
|
986 |
|
|
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
|
987 |
|
|
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
|
988 |
|
|
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
|
989 |
|
|
//(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) &&
|
990 |
|
|
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
|
991 |
|
|
rd_byte_data_offset[rnk_cnt_r][6+:6]
|
992 |
|
|
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1;
|
993 |
|
|
end
|
994 |
|
|
//*****************************************************************************
|
995 |
|
|
// One I/O Bank Interface
|
996 |
|
|
//*****************************************************************************
|
997 |
|
|
end else begin // One I/O Bank Interface
|
998 |
|
|
|
999 |
|
|
// Read data offset value for all DQS in Bank0
|
1000 |
|
|
always @(posedge clk) begin
|
1001 |
|
|
if (rst) begin
|
1002 |
|
|
for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop
|
1003 |
|
|
rd_byte_data_offset[l] <= #TCQ nCL + nAL + LATENCY_FACTOR;
|
1004 |
|
|
end
|
1005 |
|
|
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
|
1006 |
|
|
(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL - 1)))
|
1007 |
|
|
rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL + LATENCY_FACTOR;
|
1008 |
|
|
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
|
1009 |
|
|
//(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL -1)) &&
|
1010 |
|
|
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
|
1011 |
|
|
rd_byte_data_offset[rnk_cnt_r]
|
1012 |
|
|
<= #TCQ rd_byte_data_offset[rnk_cnt_r] - 1;
|
1013 |
|
|
end
|
1014 |
|
|
|
1015 |
|
|
// Reset read data offset calibration in all DQS Phaser_INs
|
1016 |
|
|
// in a Bank after the read data offset value for a rank is determined
|
1017 |
|
|
// or if within a Bank DQSFOUND is not asserted for all DQSs
|
1018 |
|
|
always @(posedge clk) begin
|
1019 |
|
|
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
|
1020 |
|
|
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
|
1021 |
|
|
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
|
1022 |
|
|
//(dqsfound_retry[0]) ||
|
1023 |
|
|
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
|
1024 |
|
|
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
|
1025 |
|
|
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
|
1026 |
|
|
end
|
1027 |
|
|
|
1028 |
|
|
always @(posedge clk) begin
|
1029 |
|
|
if (rst || fine_adjust)
|
1030 |
|
|
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
|
1031 |
|
|
else if (pi_rst_stg1_cal_r[0])
|
1032 |
|
|
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
|
1033 |
|
|
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
|
1034 |
|
|
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
|
1035 |
|
|
end
|
1036 |
|
|
|
1037 |
|
|
//*****************************************************************************
|
1038 |
|
|
// Retry counter to track number of DQSFOUND retries
|
1039 |
|
|
//*****************************************************************************
|
1040 |
|
|
|
1041 |
|
|
always @(posedge clk) begin
|
1042 |
|
|
if (rst || rank_done_r)
|
1043 |
|
|
retry_cnt[0+:10] <= #TCQ 'b0;
|
1044 |
|
|
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
|
1045 |
|
|
~pi_dqs_found_all_bank[0])
|
1046 |
|
|
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
|
1047 |
|
|
else
|
1048 |
|
|
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
|
1049 |
|
|
end
|
1050 |
|
|
|
1051 |
|
|
// Error generation in case pi_dqs_found_all_bank
|
1052 |
|
|
// is not asserted even with 3 dqfound retries
|
1053 |
|
|
always @(posedge clk) begin
|
1054 |
|
|
if (rst)
|
1055 |
|
|
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
|
1056 |
|
|
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
|
1057 |
|
|
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
|
1058 |
|
|
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
|
1059 |
|
|
end
|
1060 |
|
|
|
1061 |
|
|
end
|
1062 |
|
|
endgenerate
|
1063 |
|
|
|
1064 |
|
|
always @(posedge clk) begin
|
1065 |
|
|
if (rst)
|
1066 |
|
|
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};
|
1067 |
|
|
else if (rst_dqs_find)
|
1068 |
|
|
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};
|
1069 |
|
|
else
|
1070 |
|
|
pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;
|
1071 |
|
|
end
|
1072 |
|
|
|
1073 |
|
|
|
1074 |
|
|
|
1075 |
|
|
// Final read data offset value to be used during write calibration and
|
1076 |
|
|
// normal operation
|
1077 |
|
|
generate
|
1078 |
|
|
genvar i;
|
1079 |
|
|
genvar j;
|
1080 |
|
|
for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop
|
1081 |
|
|
reg [5:0] final_do_cand [RANKS-1:0];
|
1082 |
|
|
// combinatorially select the candidate offset for the bank
|
1083 |
|
|
// indexed by final_do_index
|
1084 |
|
|
if (HIGHEST_BANK == 3) begin
|
1085 |
|
|
always @(*) begin
|
1086 |
|
|
case (final_do_index[i])
|
1087 |
|
|
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
|
1088 |
|
|
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
|
1089 |
|
|
3'b010: final_do_cand[i] = final_data_offset[i][17:12];
|
1090 |
|
|
default: final_do_cand[i] = 'd0;
|
1091 |
|
|
endcase
|
1092 |
|
|
end
|
1093 |
|
|
end else if (HIGHEST_BANK == 2) begin
|
1094 |
|
|
always @(*) begin
|
1095 |
|
|
case (final_do_index[i])
|
1096 |
|
|
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
|
1097 |
|
|
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
|
1098 |
|
|
3'b010: final_do_cand[i] = 'd0;
|
1099 |
|
|
default: final_do_cand[i] = 'd0;
|
1100 |
|
|
endcase
|
1101 |
|
|
end
|
1102 |
|
|
end else begin
|
1103 |
|
|
always @(*) begin
|
1104 |
|
|
case (final_do_index[i])
|
1105 |
|
|
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
|
1106 |
|
|
3'b001: final_do_cand[i] = 'd0;
|
1107 |
|
|
3'b010: final_do_cand[i] = 'd0;
|
1108 |
|
|
default: final_do_cand[i] = 'd0;
|
1109 |
|
|
endcase
|
1110 |
|
|
end
|
1111 |
|
|
end
|
1112 |
|
|
|
1113 |
|
|
always @(posedge clk) begin
|
1114 |
|
|
if (rst)
|
1115 |
|
|
final_do_max[i] <= #TCQ 0;
|
1116 |
|
|
else begin
|
1117 |
|
|
final_do_max[i] <= #TCQ final_do_max[i]; // default
|
1118 |
|
|
case (final_do_index[i])
|
1119 |
|
|
3'b000: if ( | DATA_PRESENT[3:0])
|
1120 |
|
|
if (final_do_max[i] < final_do_cand[i])
|
1121 |
|
|
if (CWL_M % 2) // odd latency CAS slot 1
|
1122 |
|
|
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
|
1123 |
|
|
else
|
1124 |
|
|
final_do_max[i] <= #TCQ final_do_cand[i];
|
1125 |
|
|
3'b001: if ( | DATA_PRESENT[7:4])
|
1126 |
|
|
if (final_do_max[i] < final_do_cand[i])
|
1127 |
|
|
if (CWL_M % 2) // odd latency CAS slot 1
|
1128 |
|
|
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
|
1129 |
|
|
else
|
1130 |
|
|
final_do_max[i] <= #TCQ final_do_cand[i];
|
1131 |
|
|
3'b010: if ( | DATA_PRESENT[11:8])
|
1132 |
|
|
if (final_do_max[i] < final_do_cand[i])
|
1133 |
|
|
if (CWL_M % 2) // odd latency CAS slot 1
|
1134 |
|
|
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
|
1135 |
|
|
else
|
1136 |
|
|
final_do_max[i] <= #TCQ final_do_cand[i];
|
1137 |
|
|
default:
|
1138 |
|
|
final_do_max[i] <= #TCQ final_do_max[i];
|
1139 |
|
|
endcase
|
1140 |
|
|
end
|
1141 |
|
|
end
|
1142 |
|
|
|
1143 |
|
|
always @(posedge clk)
|
1144 |
|
|
if (rst) begin
|
1145 |
|
|
final_do_index[i] <= #TCQ 0;
|
1146 |
|
|
end
|
1147 |
|
|
else begin
|
1148 |
|
|
final_do_index[i] <= #TCQ final_do_index[i] + 1;
|
1149 |
|
|
end
|
1150 |
|
|
|
1151 |
|
|
for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop
|
1152 |
|
|
|
1153 |
|
|
always @(posedge clk) begin
|
1154 |
|
|
if (rst) begin
|
1155 |
|
|
final_data_offset[i][6*j+:6] <= #TCQ 'b0;
|
1156 |
|
|
end
|
1157 |
|
|
else begin
|
1158 |
|
|
//if (dqsfound_retry[j])
|
1159 |
|
|
// final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
|
1160 |
|
|
//else
|
1161 |
|
|
if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin
|
1162 |
|
|
if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane
|
1163 |
|
|
final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
|
1164 |
|
|
if (CWL_M % 2) // odd latency CAS slot 1
|
1165 |
|
|
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;
|
1166 |
|
|
else // even latency CAS slot 0
|
1167 |
|
|
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
|
1168 |
|
|
end
|
1169 |
|
|
end
|
1170 |
|
|
else if (init_dqsfound_done_r5 ) begin
|
1171 |
|
|
if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes
|
1172 |
|
|
final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];
|
1173 |
|
|
final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];
|
1174 |
|
|
end
|
1175 |
|
|
end
|
1176 |
|
|
end
|
1177 |
|
|
end
|
1178 |
|
|
end
|
1179 |
|
|
end
|
1180 |
|
|
endgenerate
|
1181 |
|
|
|
1182 |
|
|
|
1183 |
|
|
// Error generation in case pi_found_dqs signal from Phaser_IN
|
1184 |
|
|
// is not asserted when a common rddata_offset value is used
|
1185 |
|
|
|
1186 |
|
|
always @(posedge clk) begin
|
1187 |
|
|
pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;
|
1188 |
|
|
end
|
1189 |
|
|
|
1190 |
|
|
|
1191 |
|
|
|
1192 |
|
|
endmodule
|
1193 |
|
|
|
1194 |
|
|
|
1195 |
|
|
|
1196 |
|
|
|
1197 |
|
|
|
1198 |
|
|
|