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//*****************************************************************************
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// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: ddr_phy_v2_3_phy_ocd_samp.v
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// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
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// \ \ / \ Date Created: Aug 03 2009
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// \___\/\___\
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//
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//Device: 7 Series
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//Design Name: DDR3 SDRAM
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//Purpose: Controls the number of samples and generates an aggregate
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//sampling result.
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//
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// The following shows the nesting of the sampling loop. Nominally built
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// to accomodate the "complex" sampling protocol. Adapted for use with
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// "simple" samplng.
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//
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// simple complex
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//
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// samples OCAL_SIMPLE_SCAN_SAMPS 1 or 50 Depends on SIM_CAL_OPTION
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// rd_victim_sel 0 0 to 7
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// data_cnt 1 157
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//
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// First it collects comparison results provided on the
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// two bit "match" bus. A particular phaser tap setting may be recorded one
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// or many times depending on various parameter settings.
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// The two bit match bus corresponds to comparisons for the
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// zero or rising phase, and the oneeighty or falling phase. The "aggregate"
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// starts out as NULL and then begins collecting comparison results
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// when phy_rddata_en_1 is high. The first result is always set into
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// the aggregate result. Subsequent results that match aggregate, don't
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// make any change. Subsequent compare results that don't match cause the aggregate
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// to turn to FUZZ.
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//
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// A "sample" is defined as a single DRAM burst for the simple step, and
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// an entire 157 DRAM data bursts across the 8 victim bits for complex.
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//
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// Once all samples have been taken, the samp_result is computed by
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// comparing the number of successful compares against the threshold.
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//
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// The second function is to track and control the number of samples. For
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// "simple" data, the number of samples is set by OCAL_SIMPLE_SCAN_SAMPS.
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// For "complex" data, nominally
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// the complex data pattern consists of a sequence of 157 DRAM chunks. This
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// sequence is run with each bit in the byte designated as the "victim". This sequence
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// is repeated 50 times, although when SIM_CAL_OPTION is set to none "NONE", it is only
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// repeated once.
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//
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// This block generates oclk_calib_resume. For the simple pattern, a single DRAM
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// burst is returned For complex its 157 which indicates the start of the 157*50
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// sequence for a bit. samp_done is pulsed.
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//
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1ps/1ps
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module mig_7series_v2_3_ddr_phy_ocd_samp #
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(parameter nCK_PER_CLK = 4,
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parameter OCAL_SIMPLE_SCAN_SAMPS = 2,
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parameter SCAN_PCT_SAMPS_SOLID = 95,
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parameter TCQ = 100,
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parameter SIM_CAL_OPTION = "NONE")
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(/*AUTOARG*/
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// Outputs
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samp_done, oclk_calib_resume, rd_victim_sel, samp_result,
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// Inputs
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complex_oclkdelay_calib_start, clk, rst, reset_scan,
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ocal_num_samples_inc, match, phy_rddata_en_1, taps_set
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);
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function integer clogb2 (input integer size); // ceiling logb2
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begin
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size = size - 1;
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for (clogb2=1; size>1; clogb2=clogb2+1)
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size = size >> 1;
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end
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endfunction // clogb2
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localparam ONE = 1;
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localparam CMPLX_DATA_CNT = nCK_PER_CLK == 2 ? 157 * 2 : 157;
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localparam SIMP_DATA_CNT = nCK_PER_CLK == 2 ? 2 : 1;
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localparam DATA_CNT_WIDTH = nCK_PER_CLK == 2 ? 9 : 8;
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localparam CMPLX_SAMPS = SIM_CAL_OPTION == "NONE" ? 50 : 1;
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// Plus one because were counting in natural numbers.
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localparam SAMP_CNT_WIDTH = clogb2(OCAL_SIMPLE_SCAN_SAMPS > CMPLX_SAMPS
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? OCAL_SIMPLE_SCAN_SAMPS : CMPLX_SAMPS) + 1;
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// Remember SAMPLES is natural number counting. One corresponds to one sample.
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localparam integer SIMP_SAMPS_SOLID_THRESH = OCAL_SIMPLE_SCAN_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01;
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localparam integer CMPLX_SAMPS_SOLID_THRESH = CMPLX_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01;
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input complex_oclkdelay_calib_start;
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wire [SAMP_CNT_WIDTH-1:0] samples = complex_oclkdelay_calib_start
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? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0]
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: OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0];
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localparam [1:0] NULL = 2'b11,
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FUZZ = 2'b00,
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ONEEIGHTY = 2'b10,
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ZERO = 2'b01;
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input clk;
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input rst;
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input reset_scan;
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// Given the need to count phy_data_en, this is not useful.
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input ocal_num_samples_inc;
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input [1:0] match;
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input phy_rddata_en_1;
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input taps_set;
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reg samp_done_ns, samp_done_r;
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always @(posedge clk) samp_done_r <= #TCQ samp_done_ns;
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output samp_done;
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assign samp_done = samp_done_r;
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reg [1:0] agg_samp_ns, agg_samp_r;
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always @(posedge clk) agg_samp_r <= #TCQ agg_samp_ns;
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reg oclk_calib_resume_ns, oclk_calib_resume_r;
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always @(posedge clk) oclk_calib_resume_r <= #TCQ oclk_calib_resume_ns;
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output oclk_calib_resume;
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assign oclk_calib_resume = oclk_calib_resume_r;
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// Complex data counting.
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// Inner most loop. 157 phy_data_en.
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reg [DATA_CNT_WIDTH-1:0] data_cnt_ns, data_cnt_r;
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always @(posedge clk) data_cnt_r <= #TCQ data_cnt_ns;
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// Nominally, 50 samples of the above 157 phy_data_en.
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reg [SAMP_CNT_WIDTH-1:0] samps_ns, samps_r;
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always @(posedge clk) samps_r <= #TCQ samps_ns;
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// Step through the 8 bits in the byte.
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reg [2:0] rd_victim_sel_ns, rd_victim_sel_r;
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always @(posedge clk) rd_victim_sel_r <= #TCQ rd_victim_sel_ns;
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output [2:0] rd_victim_sel;
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assign rd_victim_sel = rd_victim_sel_r;
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reg [SAMP_CNT_WIDTH-1:0] zero_ns, zero_r, oneeighty_ns, oneeighty_r;
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always @(posedge clk) zero_r <= #TCQ zero_ns;
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always @(posedge clk) oneeighty_r <= #TCQ oneeighty_ns;
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output [1:0] samp_result;
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assign samp_result[0] = zero_r >= (complex_oclkdelay_calib_start
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? CMPLX_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]
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: SIMP_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]);
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assign samp_result[1] = oneeighty_r >= (complex_oclkdelay_calib_start
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? CMPLX_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]
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: SIMP_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]);
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reg [0:0] sm_ns, sm_r;
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always @(posedge clk) sm_r <= #TCQ sm_ns;
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wire [DATA_CNT_WIDTH-1:0] data_cnt = complex_oclkdelay_calib_start
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? CMPLX_DATA_CNT[DATA_CNT_WIDTH-1:0]
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: SIMP_DATA_CNT[DATA_CNT_WIDTH-1:0];
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wire [2:0] rd_victim_end = complex_oclkdelay_calib_start ? 3'h7 : 3'h0;
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wire data_end = data_cnt_r == ONE[DATA_CNT_WIDTH-1:0];
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wire samp_end = samps_r == ONE[SAMP_CNT_WIDTH-1:0];
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// Primary state machine.
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always @(*) begin
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// Default next state assignments.
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agg_samp_ns = agg_samp_r;
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data_cnt_ns = data_cnt_r;
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oclk_calib_resume_ns = 1'b0;
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oneeighty_ns = oneeighty_r;
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rd_victim_sel_ns = rd_victim_sel_r;
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samp_done_ns = samp_done_r;
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samps_ns = samps_r;
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sm_ns = sm_r;
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zero_ns = zero_r;
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if (rst == 1'b1) begin
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// RESET next states
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sm_ns = /*AK("READY")*/1'd0;
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end else
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// State based actions and next states.
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case (sm_r)
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/*AL("READY")*/1'd0:begin
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agg_samp_ns = NULL;
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data_cnt_ns = data_cnt;
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oneeighty_ns = {SAMP_CNT_WIDTH{1'b0}};
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rd_victim_sel_ns = 3'b0;
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samps_ns = complex_oclkdelay_calib_start ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0]
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: OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0];
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zero_ns = {SAMP_CNT_WIDTH{1'b0}};
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if (taps_set) begin
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samp_done_ns = 1'b0;
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sm_ns = /*AK("AWAITING_DATA")*/1'd1;
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oclk_calib_resume_ns = 1'b1;
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end
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end
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/*AL("AWAITING_DATA")*/1'd1:begin
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if (phy_rddata_en_1) begin
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case (agg_samp_r)
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NULL : if (~&match) agg_samp_ns = match;
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ZERO, ONEEIGHTY : if (~(agg_samp_r == match || &match)) agg_samp_ns = FUZZ;
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FUZZ : ;
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endcase // case (agg_samp_r)
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if (~data_end) data_cnt_ns = data_cnt_r - ONE[DATA_CNT_WIDTH-1:0];
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else begin
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data_cnt_ns = data_cnt;
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if (rd_victim_end != rd_victim_sel_r) rd_victim_sel_ns = rd_victim_sel_r + 3'h1;
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else begin
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rd_victim_sel_ns = 3'h0;
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if (agg_samp_ns == ZERO) zero_ns = zero_r + ONE[SAMP_CNT_WIDTH-1:0];
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if (agg_samp_ns == ONEEIGHTY) oneeighty_ns = oneeighty_r + ONE[SAMP_CNT_WIDTH-1:0];
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agg_samp_ns = NULL;
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if (~samp_end) samps_ns = samps_r - ONE[SAMP_CNT_WIDTH-1:0];
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else samp_done_ns = 1'b1;
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end
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end
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if (samp_done_ns) sm_ns = /*AK("READY")*/1'd0;
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else oclk_calib_resume_ns = ~complex_oclkdelay_calib_start && data_end;
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end
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end
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endcase // case (sm_r)
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end // always @ begin
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endmodule // mig_7series_v2_3_ddr_phy_ocd_samp
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// Local Variables:
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// verilog-autolabel-prefix: "1'd"
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// End:
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