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//*****************************************************************************
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// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version:%version
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// \ \ Application: MIG
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// / / Filename: mig_7series_v2_3_poc_cc.v
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// /___/ /\ Date Last Modified: $$
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// \ \ / \ Date Created:Tue 20 Jan 2014
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// \___\/\___\
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//
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//Device: Virtex-7
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//Design Name: DDR3 SDRAM
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//Purpose: Phaser out characterization and control. Logic to interface with
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//Chipscope and control. Intended to support real time observation. Largely
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//not generated for production implementations.
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1 ps / 1 ps
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module mig_7series_v2_3_poc_cc #
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(parameter TCQ = 100,
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parameter CCENABLE = 0,
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parameter PCT_SAMPS_SOLID = 95,
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parameter SAMPCNTRWIDTH = 8,
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parameter SAMPLES = 128,
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parameter TAPCNTRWIDTH = 7)
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(/*AUTOARG*/
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// Outputs
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samples, samps_solid_thresh, poc_error,
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// Inputs
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tap, samps_hi_held, psen, clk, rst, ktap_at_right_edge,
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ktap_at_left_edge, mmcm_lbclk_edge_aligned, mmcm_edge_detect_done,
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fall_lead_right, fall_trail_right, rise_lead_right,
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rise_trail_right, fall_lead_left, fall_trail_left, rise_lead_left,
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rise_trail_left, fall_lead_center, fall_trail_center,
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rise_lead_center, rise_trail_center
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);
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// Remember SAMPLES is whole number counting. Zero corresponds to one sample.
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localparam integer SAMPS_SOLID_THRESH = (SAMPLES+1) * PCT_SAMPS_SOLID * 0.01;
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output [SAMPCNTRWIDTH:0] samples, samps_solid_thresh;
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input [TAPCNTRWIDTH-1:0] tap;
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input [SAMPCNTRWIDTH:0] samps_hi_held;
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input psen;
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input clk, rst;
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input ktap_at_right_edge, ktap_at_left_edge;
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input mmcm_lbclk_edge_aligned;
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wire reset_aligned_cnt = rst || ktap_at_right_edge || ktap_at_left_edge || mmcm_lbclk_edge_aligned;
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input mmcm_edge_detect_done;
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reg mmcm_edge_detect_done_r;
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always @(posedge clk) mmcm_edge_detect_done_r <= #TCQ mmcm_edge_detect_done;
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wire done = mmcm_edge_detect_done && ~mmcm_edge_detect_done_r;
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reg [6:0] aligned_cnt_r;
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wire [6:0] aligned_cnt_ns = reset_aligned_cnt ? 7'b0 : aligned_cnt_r + {6'b0, done};
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always @(posedge clk) aligned_cnt_r <= #TCQ aligned_cnt_ns;
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reg poc_error_r;
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wire poc_error_ns = ~rst && (aligned_cnt_r[6] || poc_error_r);
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always @(posedge clk) poc_error_r <= #TCQ poc_error_ns;
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output poc_error;
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assign poc_error = poc_error_r;
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input [TAPCNTRWIDTH-1:0] fall_lead_right, fall_trail_right, rise_lead_right, rise_trail_right;
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input [TAPCNTRWIDTH-1:0] fall_lead_left, fall_trail_left, rise_lead_left, rise_trail_left;
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input [TAPCNTRWIDTH-1:0] fall_lead_center, fall_trail_center, rise_lead_center, rise_trail_center;
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generate if (CCENABLE == 0) begin : no_characterization
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assign samples = SAMPLES[SAMPCNTRWIDTH:0];
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assign samps_solid_thresh = SAMPS_SOLID_THRESH[SAMPCNTRWIDTH:0];
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end else begin : characterization
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end endgenerate
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endmodule // mig_7series_v2_3_poc_cc
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