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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : rank_cntrl.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Tue Jun 30 2009
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// \___\/\___\
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//
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//Device : 7-Series
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//Design Name : DDR3 SDRAM
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//Purpose :
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//Reference :
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//Revision History :
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//*****************************************************************************
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//*****************************************************************************
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// This block is responsible for managing various rank level timing
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// parameters. For now, only Four Activate Window (FAW) and Write
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// To Read delay are implemented here.
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//
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// Each rank machine generates its own inhbt_act_faw_r and inhbt_rd.
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// These per rank machines are driven into the bank machines. Each
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// bank machines selects the correct inhibits based on the rank
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// of its current request.
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//*****************************************************************************
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`timescale 1 ps / 1 ps
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module mig_7series_v2_3_rank_cntrl #
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(
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parameter TCQ = 100, // clk->out delay (sim only)
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parameter BURST_MODE = "8", // Burst length
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parameter DQRD2DQWR_DLY = 2, // RD->WR DQ Bus Delay
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parameter CL = 5, // Read CAS latency
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parameter CWL = 5, // Write CAS latency
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parameter ID = 0, // Unique ID for each instance
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parameter nBANK_MACHS = 4, // # bank machines in MC
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parameter nCK_PER_CLK = 2, // DRAM clock : MC clock
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parameter nFAW = 30, // four activate window (CKs)
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parameter nREFRESH_BANK = 8, // # REF commands to pull-in
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parameter nRRD = 4, // ACT->ACT period (CKs)
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parameter nWTR = 4, // Internal write->read
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// delay (CKs)
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parameter PERIODIC_RD_TIMER_DIV = 20, // Maintenance prescaler divisor
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// for periodic read timer
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parameter RANK_BM_BV_WIDTH = 16, // Width required to broadcast a
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// single bit rank signal among
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// all the bank machines
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parameter RANK_WIDTH = 2, // # of bits to count ranks
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parameter RANKS = 4, // # of ranks of DRAM
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parameter REFRESH_TIMER_DIV = 39 // Maintenance prescaler divivor
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// for refresh timer
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)
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(
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// Maintenance requests
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output periodic_rd_request,
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output wire refresh_request,
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// Inhibit signals
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output reg inhbt_act_faw_r,
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output reg inhbt_rd,
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output reg inhbt_wr,
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// System Inputs
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input clk,
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input rst,
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// User maintenance requests
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input app_periodic_rd_req,
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input app_ref_req,
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// Inputs
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input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,
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input clear_periodic_rd_request,
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input col_rd_wr,
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input init_calib_complete,
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input insert_maint_r1,
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input maint_prescaler_tick_r,
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input [RANK_WIDTH-1:0] maint_rank_r,
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input maint_zq_r,
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input maint_sre_r,
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input maint_srx_r,
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input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,
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input refresh_tick,
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input [nBANK_MACHS-1:0] sending_col,
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input [nBANK_MACHS-1:0] sending_row,
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input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,
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input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r
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);
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//***************************************************************************
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// RRD configuration. The bank machines have a mechanism to prevent RAS to
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// RAS on adjacent fabric CLK states to the same rank. When
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// nCK_PER_CLK == 1, this translates to a minimum of 2 for nRRD, 4 for nRRD
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// when nCK_PER_CLK == 2 and 8 for nRRD when nCK_PER_CLK == 4. Some of the
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// higher clock rate DDR3 DRAMs have nRRD > 4. The additional RRD inhibit
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// is worked into the inhbt_faw signal.
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//***************************************************************************
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localparam nADD_RRD = nRRD -
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(
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(nCK_PER_CLK == 1) ? 2 :
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(nCK_PER_CLK == 2) ? 4 :
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/*(nCK_PER_CLK == 4)*/ 8
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);
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// divide by nCK_PER_CLK and add a cycle if there's a remainder
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localparam nRRD_CLKS =
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(nCK_PER_CLK == 1) ? nADD_RRD :
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(nCK_PER_CLK == 2) ? ((nADD_RRD/2)+(nADD_RRD%2)) :
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/*(nCK_PER_CLK == 4)*/ ((nADD_RRD/4)+((nADD_RRD%4) ? 1 : 0));
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// take binary log to obtain counter width and add a tick for the idle cycle
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localparam ADD_RRD_CNTR_WIDTH = clogb2(nRRD_CLKS + /* idle state */ 1);
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//***************************************************************************
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// Internal signals
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//***************************************************************************
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reg act_this_rank;
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integer i; // loop invariant
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//***************************************************************************
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// Function clogb2
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// Description:
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// This function performs binary logarithm and rounds up
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// Inputs:
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// size: integer to perform binary log upon
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// Outputs:
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// clogb2: result of binary logarithm, rounded up
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//***************************************************************************
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function integer clogb2 (input integer size);
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begin
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size = size - 1;
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// increment clogb2 from 1 for each bit in size
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for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1)
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size = size >> 1;
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end
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endfunction // clogb2
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//***************************************************************************
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// Determine if this rank has been activated. act_this_rank_r is a
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// registered bit vector from individual bank machines indicating the
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// corresponding bank machine is sending
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// an activate. Timing is improved with this method.
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//***************************************************************************
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always @(/*AS*/act_this_rank_r or sending_row) begin
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act_this_rank = 1'b0;
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for (i = 0; i < nBANK_MACHS; i = i + 1)
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act_this_rank =
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act_this_rank || (sending_row[i] && act_this_rank_r[(i*RANKS)+ID]);
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end
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reg add_rrd_inhbt = 1'b0;
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generate
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if (nADD_RRD > 0 && ADD_RRD_CNTR_WIDTH > 1) begin :add_rdd1
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reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;
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reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;
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always @(/*AS*/act_this_rank or add_rrd_r or rst) begin
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add_rrd_ns = add_rrd_r;
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if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};
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else
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if (act_this_rank)
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add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];
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else if (|add_rrd_r) add_rrd_ns =
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add_rrd_r - {{ADD_RRD_CNTR_WIDTH-1{1'b0}}, 1'b1};
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end
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always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;
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always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;
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end // add_rdd1
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else if (nADD_RRD > 0) begin :add_rdd0
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reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;
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reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;
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always @(/*AS*/act_this_rank or add_rrd_r or rst) begin
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add_rrd_ns = add_rrd_r;
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if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};
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else
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if (act_this_rank)
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add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];
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else if (|add_rrd_r) add_rrd_ns =
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add_rrd_r - {1'b1};
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end
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always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;
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always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;
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end // add_rdd0
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endgenerate
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// Compute inhbt_act_faw_r. Only allow a limited number of activates
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// in a window. Both the number of activates and the window are
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// configurable. This depends on the RRD mechanism to prevent
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// two consecutive activates to the same rank.
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//
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// Subtract three from the specified nFAW. Subtract three because:
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// -Zero for the delay into the SRL is really one state.
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// -Sending_row is used to trigger the delay. Sending_row is one
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// state delayed from the arb.
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// -inhbt_act_faw_r is registered to make timing work, hence the
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// generation needs to be one state early.
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localparam nFAW_CLKS = (nCK_PER_CLK == 1)
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? nFAW
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: (nCK_PER_CLK == 2) ? ((nFAW/2) + (nFAW%2)) :
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((nFAW/4) + ((nFAW%4) ? 1 : 0));
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generate
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begin : inhbt_act_faw
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wire act_delayed;
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wire [4:0] shift_depth = nFAW_CLKS[4:0] - 5'd3;
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SRLC32E #(.INIT(32'h00000000) ) SRLC32E0
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(.Q(act_delayed), // SRL data output
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.Q31(), // SRL cascade output pin
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.A(shift_depth), // 5-bit shift depth select input
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.CE(1'b1), // Clock enable input
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.CLK(clk), // Clock input
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.D(act_this_rank) // SRL data input
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);
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reg [2:0] faw_cnt_ns;
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reg [2:0] faw_cnt_r;
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reg inhbt_act_faw_ns;
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always @(/*AS*/act_delayed or act_this_rank or add_rrd_inhbt
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or faw_cnt_r or rst) begin
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if (rst) faw_cnt_ns = 3'b0;
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else begin
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faw_cnt_ns = faw_cnt_r;
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if (act_this_rank) faw_cnt_ns = faw_cnt_r + 3'b1;
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if (act_delayed) faw_cnt_ns = faw_cnt_ns - 3'b1;
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end
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inhbt_act_faw_ns = (faw_cnt_ns == 3'h4) || add_rrd_inhbt;
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end
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always @(posedge clk) faw_cnt_r <= #TCQ faw_cnt_ns;
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always @(posedge clk) inhbt_act_faw_r <= #TCQ inhbt_act_faw_ns;
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end // block: inhbt_act_faw
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endgenerate
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// In the DRAM spec, tWTR starts from CK following the end of the data
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// burst. Since we don't directly have that spec, the wtr timer is
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// based on when the CAS write command is sent to the DRAM.
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//
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// To compute the wtr timer value, first compute the time from the write command
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// to the read command. This is CWL + data_time + nWTR.
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//
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// Two is subtracted from the required wtr time since the timer
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// starts two states after the arbitration cycle.
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localparam ONE = 1;
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localparam TWO = 2;
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localparam CASWR2CASRD = CWL + (BURST_MODE == "4" ? 2 : 4) + nWTR;
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localparam CASWR2CASRD_CLKS = (nCK_PER_CLK == 1)
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? CASWR2CASRD :
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(nCK_PER_CLK == 2)
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? ((CASWR2CASRD / 2) + (CASWR2CASRD % 2)) :
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((CASWR2CASRD / 4) + ((CASWR2CASRD % 4) ? 1 :0));
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localparam WTR_CNT_WIDTH = clogb2(CASWR2CASRD_CLKS);
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generate
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begin : wtr_timer
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329 |
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|
reg write_this_rank;
|
330 |
|
|
always @(/*AS*/sending_col or wr_this_rank_r) begin
|
331 |
|
|
write_this_rank = 1'b0;
|
332 |
|
|
for (i = 0; i < nBANK_MACHS; i = i + 1)
|
333 |
|
|
write_this_rank =
|
334 |
|
|
write_this_rank || (sending_col[i] && wr_this_rank_r[(i*RANKS)+ID]);
|
335 |
|
|
end
|
336 |
|
|
|
337 |
|
|
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_r;
|
338 |
|
|
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_ns;
|
339 |
|
|
|
340 |
|
|
always @(/*AS*/rst or write_this_rank or wtr_cnt_r)
|
341 |
|
|
if (rst) wtr_cnt_ns = {WTR_CNT_WIDTH{1'b0}};
|
342 |
|
|
else begin
|
343 |
|
|
wtr_cnt_ns = wtr_cnt_r;
|
344 |
|
|
if (write_this_rank) wtr_cnt_ns =
|
345 |
|
|
CASWR2CASRD_CLKS[WTR_CNT_WIDTH-1:0] - ONE[WTR_CNT_WIDTH-1:0];
|
346 |
|
|
else if (|wtr_cnt_r) wtr_cnt_ns = wtr_cnt_r - ONE[WTR_CNT_WIDTH-1:0];
|
347 |
|
|
end
|
348 |
|
|
|
349 |
|
|
wire inhbt_rd_ns = |wtr_cnt_ns;
|
350 |
|
|
|
351 |
|
|
always @(posedge clk) wtr_cnt_r <= #TCQ wtr_cnt_ns;
|
352 |
|
|
always @(inhbt_rd_ns) inhbt_rd = inhbt_rd_ns;
|
353 |
|
|
|
354 |
|
|
end
|
355 |
|
|
endgenerate
|
356 |
|
|
|
357 |
|
|
// In the DRAM spec (with AL = 0), the read-to-write command delay is implied to
|
358 |
|
|
// be CL + data_time + 2 tCK - CWL. The CL + data_time - CWL terms ensure the
|
359 |
|
|
// read and write data do not collide on the DQ bus. The 2 tCK ensures a gap
|
360 |
|
|
// between them. Here, we allow the user to tune this fixed term via the
|
361 |
|
|
// DQRD2DQWR_DLY parameter. There's a potential for optimization by relocating
|
362 |
|
|
// this to the rank_common module, since this is a DQ/DQS bus-level requirement,
|
363 |
|
|
// not a per-rank requirement.
|
364 |
|
|
|
365 |
|
|
localparam CASRD2CASWR = CL + (BURST_MODE == "4" ? 2 : 4) + DQRD2DQWR_DLY - CWL;
|
366 |
|
|
localparam CASRD2CASWR_CLKS = (nCK_PER_CLK == 1)
|
367 |
|
|
? CASRD2CASWR :
|
368 |
|
|
(nCK_PER_CLK == 2)
|
369 |
|
|
? ((CASRD2CASWR / 2) + (CASRD2CASWR % 2)) :
|
370 |
|
|
((CASRD2CASWR / 4) + ((CASRD2CASWR % 4) ? 1 :0));
|
371 |
|
|
localparam RTW_CNT_WIDTH = clogb2(CASRD2CASWR_CLKS);
|
372 |
|
|
|
373 |
|
|
generate
|
374 |
|
|
begin : rtw_timer
|
375 |
|
|
|
376 |
|
|
reg read_this_rank;
|
377 |
|
|
always @(/*AS*/sending_col or rd_this_rank_r) begin
|
378 |
|
|
read_this_rank = 1'b0;
|
379 |
|
|
for (i = 0; i < nBANK_MACHS; i = i + 1)
|
380 |
|
|
read_this_rank =
|
381 |
|
|
read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);
|
382 |
|
|
end
|
383 |
|
|
|
384 |
|
|
reg [RTW_CNT_WIDTH-1:0] rtw_cnt_r;
|
385 |
|
|
reg [RTW_CNT_WIDTH-1:0] rtw_cnt_ns;
|
386 |
|
|
|
387 |
|
|
always @(/*AS*/rst or col_rd_wr or sending_col or rtw_cnt_r)
|
388 |
|
|
if (rst) rtw_cnt_ns = {RTW_CNT_WIDTH{1'b0}};
|
389 |
|
|
else begin
|
390 |
|
|
rtw_cnt_ns = rtw_cnt_r;
|
391 |
|
|
if (col_rd_wr && |sending_col) rtw_cnt_ns =
|
392 |
|
|
CASRD2CASWR_CLKS[RTW_CNT_WIDTH-1:0] - ONE[RTW_CNT_WIDTH-1:0];
|
393 |
|
|
else if (|rtw_cnt_r) rtw_cnt_ns = rtw_cnt_r - ONE[RTW_CNT_WIDTH-1:0];
|
394 |
|
|
end
|
395 |
|
|
|
396 |
|
|
wire inhbt_wr_ns = |rtw_cnt_ns;
|
397 |
|
|
|
398 |
|
|
always @(posedge clk) rtw_cnt_r <= #TCQ rtw_cnt_ns;
|
399 |
|
|
always @(inhbt_wr_ns) inhbt_wr = inhbt_wr_ns;
|
400 |
|
|
|
401 |
|
|
end
|
402 |
|
|
endgenerate
|
403 |
|
|
|
404 |
|
|
// Refresh request generation. Implement a "refresh bank". Referred
|
405 |
|
|
// to as pullin-in refresh in the JEDEC spec.
|
406 |
|
|
// The refresh_rank_r counter increments when a refresh to this
|
407 |
|
|
// rank has been decoded. In the up direction, the count saturates
|
408 |
|
|
// at nREFRESH_BANK. As specified in the JEDEC spec, nREFRESH_BANK
|
409 |
|
|
// is normally eight. The counter decrements with each refresh_tick,
|
410 |
|
|
// saturating at zero. A refresh will be requests when the rank is
|
411 |
|
|
// not busy and refresh_rank_r != nREFRESH_BANK, or refresh_rank_r
|
412 |
|
|
// equals zero.
|
413 |
|
|
|
414 |
|
|
localparam REFRESH_BANK_WIDTH = clogb2(nREFRESH_BANK + 1);
|
415 |
|
|
|
416 |
|
|
|
417 |
|
|
generate begin : refresh_generation
|
418 |
|
|
reg my_rank_busy;
|
419 |
|
|
always @(/*AS*/rank_busy_r) begin
|
420 |
|
|
my_rank_busy = 1'b0;
|
421 |
|
|
for (i=0; i < nBANK_MACHS; i=i+1)
|
422 |
|
|
my_rank_busy = my_rank_busy || rank_busy_r[(i*RANKS)+ID];
|
423 |
|
|
end
|
424 |
|
|
|
425 |
|
|
wire my_refresh =
|
426 |
|
|
insert_maint_r1 && ~maint_zq_r && ~maint_sre_r && ~maint_srx_r &&
|
427 |
|
|
(maint_rank_r == ID[RANK_WIDTH-1:0]);
|
428 |
|
|
|
429 |
|
|
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_r;
|
430 |
|
|
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_ns;
|
431 |
|
|
always @(/*AS*/app_ref_req or init_calib_complete or my_refresh
|
432 |
|
|
or refresh_bank_r or refresh_tick)
|
433 |
|
|
if (~init_calib_complete)
|
434 |
|
|
if (REFRESH_TIMER_DIV == 0)
|
435 |
|
|
refresh_bank_ns = nREFRESH_BANK[0+:REFRESH_BANK_WIDTH];
|
436 |
|
|
else refresh_bank_ns = {REFRESH_BANK_WIDTH{1'b0}};
|
437 |
|
|
else
|
438 |
|
|
case ({my_refresh, refresh_tick, app_ref_req})
|
439 |
|
|
3'b000, 3'b110, 3'b101, 3'b111 : refresh_bank_ns = refresh_bank_r;
|
440 |
|
|
3'b010, 3'b001, 3'b011 : refresh_bank_ns =
|
441 |
|
|
(|refresh_bank_r)?
|
442 |
|
|
refresh_bank_r - ONE[0+:REFRESH_BANK_WIDTH]:
|
443 |
|
|
refresh_bank_r;
|
444 |
|
|
3'b100 : refresh_bank_ns =
|
445 |
|
|
refresh_bank_r + ONE[0+:REFRESH_BANK_WIDTH];
|
446 |
|
|
endcase // case ({my_refresh, refresh_tick})
|
447 |
|
|
always @(posedge clk) refresh_bank_r <= #TCQ refresh_bank_ns;
|
448 |
|
|
|
449 |
|
|
`ifdef MC_SVA
|
450 |
|
|
refresh_bank_overflow: assert property (@(posedge clk)
|
451 |
|
|
(rst || (refresh_bank_r <= nREFRESH_BANK)));
|
452 |
|
|
refresh_bank_underflow: assert property (@(posedge clk)
|
453 |
|
|
(rst || ~(~|refresh_bank_r && ~my_refresh && refresh_tick)));
|
454 |
|
|
refresh_hi_priority: cover property (@(posedge clk)
|
455 |
|
|
(rst && ~|refresh_bank_ns && (refresh_bank_r ==
|
456 |
|
|
ONE[0+:REFRESH_BANK_WIDTH])));
|
457 |
|
|
refresh_bank_full: cover property (@(posedge clk)
|
458 |
|
|
(rst && (refresh_bank_r ==
|
459 |
|
|
nREFRESH_BANK[0+:REFRESH_BANK_WIDTH])));
|
460 |
|
|
`endif
|
461 |
|
|
|
462 |
|
|
assign refresh_request = init_calib_complete &&
|
463 |
|
|
(~|refresh_bank_r ||
|
464 |
|
|
((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && ~my_rank_busy));
|
465 |
|
|
|
466 |
|
|
end
|
467 |
|
|
endgenerate
|
468 |
|
|
|
469 |
|
|
// Periodic read request generation.
|
470 |
|
|
|
471 |
|
|
localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1);
|
472 |
|
|
|
473 |
|
|
|
474 |
|
|
generate begin : periodic_rd_generation
|
475 |
|
|
if ( PERIODIC_RD_TIMER_DIV != 0 ) begin // enable periodic reads
|
476 |
|
|
reg read_this_rank;
|
477 |
|
|
always @(/*AS*/rd_this_rank_r or sending_col) begin
|
478 |
|
|
read_this_rank = 1'b0;
|
479 |
|
|
for (i = 0; i < nBANK_MACHS; i = i + 1)
|
480 |
|
|
read_this_rank =
|
481 |
|
|
read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);
|
482 |
|
|
end
|
483 |
|
|
|
484 |
|
|
reg read_this_rank_r;
|
485 |
|
|
reg read_this_rank_r1;
|
486 |
|
|
always @(posedge clk) read_this_rank_r <= #TCQ read_this_rank;
|
487 |
|
|
always @(posedge clk) read_this_rank_r1 <= #TCQ read_this_rank_r;
|
488 |
|
|
wire int_read_this_rank = read_this_rank &&
|
489 |
|
|
(((nCK_PER_CLK == 4) && read_this_rank_r) ||
|
490 |
|
|
((nCK_PER_CLK != 4) && read_this_rank_r1));
|
491 |
|
|
|
492 |
|
|
reg periodic_rd_cntr1_ns;
|
493 |
|
|
reg periodic_rd_cntr1_r;
|
494 |
|
|
always @(/*AS*/clear_periodic_rd_request or periodic_rd_cntr1_r) begin
|
495 |
|
|
periodic_rd_cntr1_ns = periodic_rd_cntr1_r;
|
496 |
|
|
if (clear_periodic_rd_request)
|
497 |
|
|
periodic_rd_cntr1_ns = periodic_rd_cntr1_r + 1'b1;
|
498 |
|
|
end
|
499 |
|
|
always @(posedge clk) begin
|
500 |
|
|
if (rst) periodic_rd_cntr1_r <= #TCQ 1'b0;
|
501 |
|
|
else periodic_rd_cntr1_r <= #TCQ periodic_rd_cntr1_ns;
|
502 |
|
|
end
|
503 |
|
|
|
504 |
|
|
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r;
|
505 |
|
|
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_ns;
|
506 |
|
|
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r
|
507 |
|
|
or periodic_rd_timer_r or int_read_this_rank) begin
|
508 |
|
|
periodic_rd_timer_ns = periodic_rd_timer_r;
|
509 |
|
|
if (~init_calib_complete)
|
510 |
|
|
periodic_rd_timer_ns = {PERIODIC_RD_TIMER_WIDTH{1'b0}};
|
511 |
|
|
else if (int_read_this_rank)
|
512 |
|
|
periodic_rd_timer_ns =
|
513 |
|
|
PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH];
|
514 |
|
|
else if (|periodic_rd_timer_r && maint_prescaler_tick_r)
|
515 |
|
|
periodic_rd_timer_ns =
|
516 |
|
|
periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH];
|
517 |
|
|
end
|
518 |
|
|
always @(posedge clk) periodic_rd_timer_r <= #TCQ periodic_rd_timer_ns;
|
519 |
|
|
|
520 |
|
|
wire periodic_rd_timer_one = maint_prescaler_tick_r &&
|
521 |
|
|
(periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]);
|
522 |
|
|
|
523 |
|
|
reg periodic_rd_request_r;
|
524 |
|
|
wire periodic_rd_request_ns = ~rst &&
|
525 |
|
|
((app_periodic_rd_req && init_calib_complete) ||
|
526 |
|
|
((PERIODIC_RD_TIMER_DIV != 0) && ~init_calib_complete) ||
|
527 |
|
|
// (~(read_this_rank || clear_periodic_rd_request) &&
|
528 |
|
|
(~((int_read_this_rank) || (clear_periodic_rd_request && periodic_rd_cntr1_r)) &&
|
529 |
|
|
(periodic_rd_request_r || periodic_rd_timer_one)));
|
530 |
|
|
always @(posedge clk) periodic_rd_request_r <=
|
531 |
|
|
#TCQ periodic_rd_request_ns;
|
532 |
|
|
|
533 |
|
|
`ifdef MC_SVA
|
534 |
|
|
read_clears_periodic_rd_request: cover property (@(posedge clk)
|
535 |
|
|
(rst && (periodic_rd_request_r && read_this_rank)));
|
536 |
|
|
`endif
|
537 |
|
|
|
538 |
|
|
assign periodic_rd_request = init_calib_complete && periodic_rd_request_r;
|
539 |
|
|
end else
|
540 |
|
|
assign periodic_rd_request = 1'b0; //to disable periodic reads
|
541 |
|
|
|
542 |
|
|
end
|
543 |
|
|
endgenerate
|
544 |
|
|
|
545 |
|
|
|
546 |
|
|
endmodule
|