1 |
2 |
ZTEX |
//*****************************************************************************
|
2 |
|
|
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
3 |
|
|
//
|
4 |
|
|
// This file contains confidential and proprietary information
|
5 |
|
|
// of Xilinx, Inc. and is protected under U.S. and
|
6 |
|
|
// international copyright and other intellectual property
|
7 |
|
|
// laws.
|
8 |
|
|
//
|
9 |
|
|
// DISCLAIMER
|
10 |
|
|
// This disclaimer is not a license and does not grant any
|
11 |
|
|
// rights to the materials distributed herewith. Except as
|
12 |
|
|
// otherwise provided in a valid license issued to you by
|
13 |
|
|
// Xilinx, and to the maximum extent permitted by applicable
|
14 |
|
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
15 |
|
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
16 |
|
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
17 |
|
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
18 |
|
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
19 |
|
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
20 |
|
|
// including negligence, or under any other theory of
|
21 |
|
|
// liability) for any loss or damage of any kind or nature
|
22 |
|
|
// related to, arising under or in connection with these
|
23 |
|
|
// materials, including for any direct, or any indirect,
|
24 |
|
|
// special, incidental, or consequential loss or damage
|
25 |
|
|
// (including loss of data, profits, goodwill, or any type of
|
26 |
|
|
// loss or damage suffered as a result of any action brought
|
27 |
|
|
// by a third party) even if such damage or loss was
|
28 |
|
|
// reasonably foreseeable or Xilinx had been advised of the
|
29 |
|
|
// possibility of the same.
|
30 |
|
|
//
|
31 |
|
|
// CRITICAL APPLICATIONS
|
32 |
|
|
// Xilinx products are not designed or intended to be fail-
|
33 |
|
|
// safe, or for use in any application requiring fail-safe
|
34 |
|
|
// performance, such as life-support or safety devices or
|
35 |
|
|
// systems, Class III medical devices, nuclear facilities,
|
36 |
|
|
// applications related to the deployment of airbags, or any
|
37 |
|
|
// other applications that could lead to death, personal
|
38 |
|
|
// injury, or severe property or environmental damage
|
39 |
|
|
// (individually and collectively, "Critical
|
40 |
|
|
// Applications"). Customer assumes the sole risk and
|
41 |
|
|
// liability of any use of Xilinx products in Critical
|
42 |
|
|
// Applications, subject only to applicable laws and
|
43 |
|
|
// regulations governing limitations on product liability.
|
44 |
|
|
//
|
45 |
|
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
46 |
|
|
// PART OF THIS FILE AT ALL TIMES.
|
47 |
|
|
//
|
48 |
|
|
//*****************************************************************************
|
49 |
|
|
// ____ ____
|
50 |
|
|
// / /\/ /
|
51 |
|
|
// /___/ \ / Vendor: Xilinx
|
52 |
|
|
// \ \ \/ Version: %version
|
53 |
|
|
// \ \ Application: MIG
|
54 |
|
|
// / / Filename: ddr_phy_v2_3_phy_ocd_mux.v
|
55 |
|
|
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
|
56 |
|
|
// \ \ / \ Date Created: Aug 03 2009
|
57 |
|
|
// \___\/\___\
|
58 |
|
|
//
|
59 |
|
|
//Device: 7 Series
|
60 |
|
|
//Design Name: DDR3 SDRAM
|
61 |
|
|
//Purpose: The limit block and the _po_cntlr block both manipulate
|
62 |
|
|
// the phaser out and the POC. This block muxes those commands
|
63 |
|
|
// together, and encapsulates logic required for meeting phaser
|
64 |
|
|
// setup and wait times.
|
65 |
|
|
//
|
66 |
|
|
//Reference:
|
67 |
|
|
//Revision History:
|
68 |
|
|
//*****************************************************************************
|
69 |
|
|
|
70 |
|
|
`timescale 1ps/1ps
|
71 |
|
|
|
72 |
|
|
module mig_7series_v2_3_ddr_phy_ocd_mux #
|
73 |
|
|
(parameter DQS_CNT_WIDTH = 3,
|
74 |
|
|
parameter DQS_WIDTH = 8,
|
75 |
|
|
parameter TCQ = 100)
|
76 |
|
|
(/*AUTOARG*/
|
77 |
|
|
// Outputs
|
78 |
|
|
ktap_at_left_edge, ktap_at_right_edge, mmcm_edge_detect_rdy,
|
79 |
|
|
po_stg3_incdec, po_en_stg3, po_en_stg23, po_stg23_sel,
|
80 |
|
|
po_stg23_incdec, po_rdy, wl_po_fine_cnt_sel, oclk_prech_req,
|
81 |
|
|
// Inputs
|
82 |
|
|
clk, rst, ocd_ktap_right, ocd_ktap_left, lim2poc_ktap_right,
|
83 |
|
|
lim2poc_rdy, ocd_edge_detect_rdy, lim2stg2_inc, lim2stg2_dec,
|
84 |
|
|
lim2stg3_inc, lim2stg3_dec, ocd2stg2_inc, ocd2stg2_dec,
|
85 |
|
|
ocd_cntlr2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, wl_po_fine_cnt,
|
86 |
|
|
oclkdelay_calib_cnt, lim2init_prech_req, ocd_prech_req
|
87 |
|
|
);
|
88 |
|
|
|
89 |
|
|
function integer clogb2 (input integer size); // ceiling logb2
|
90 |
|
|
begin
|
91 |
|
|
size = size - 1;
|
92 |
|
|
for (clogb2=1; size>1; clogb2=clogb2+1)
|
93 |
|
|
size = size >> 1;
|
94 |
|
|
end
|
95 |
|
|
endfunction // clogb2
|
96 |
|
|
|
97 |
|
|
localparam PO_WAIT = 15;
|
98 |
|
|
localparam POW_WIDTH = clogb2(PO_WAIT);
|
99 |
|
|
localparam ONE = 1;
|
100 |
|
|
localparam TWO = 2;
|
101 |
|
|
|
102 |
|
|
input clk;
|
103 |
|
|
input rst;
|
104 |
|
|
|
105 |
|
|
input ocd_ktap_right, ocd_ktap_left;
|
106 |
|
|
input lim2poc_ktap_right;
|
107 |
|
|
output ktap_at_left_edge, ktap_at_right_edge;
|
108 |
|
|
assign ktap_at_left_edge = ocd_ktap_left;
|
109 |
|
|
assign ktap_at_right_edge = lim2poc_ktap_right || ocd_ktap_right;
|
110 |
|
|
|
111 |
|
|
input lim2poc_rdy;
|
112 |
|
|
input ocd_edge_detect_rdy;
|
113 |
|
|
output mmcm_edge_detect_rdy;
|
114 |
|
|
assign mmcm_edge_detect_rdy = lim2poc_rdy || ocd_edge_detect_rdy;
|
115 |
|
|
|
116 |
|
|
// po_stg3_incdec and po_en_stg3 are deprecated and should be removed.
|
117 |
|
|
output po_stg3_incdec;
|
118 |
|
|
output po_en_stg3;
|
119 |
|
|
assign po_stg3_incdec = 1'b0;
|
120 |
|
|
assign po_en_stg3 = 1'b0;
|
121 |
|
|
|
122 |
|
|
|
123 |
|
|
reg [1:0] po_setup_ns, po_setup_r;
|
124 |
|
|
always @(posedge clk) po_setup_r <= #TCQ po_setup_ns;
|
125 |
|
|
|
126 |
|
|
input lim2stg2_inc;
|
127 |
|
|
input lim2stg2_dec;
|
128 |
|
|
|
129 |
|
|
input lim2stg3_inc;
|
130 |
|
|
input lim2stg3_dec;
|
131 |
|
|
|
132 |
|
|
input ocd2stg2_inc;
|
133 |
|
|
input ocd2stg2_dec;
|
134 |
|
|
input ocd_cntlr2stg2_dec;
|
135 |
|
|
|
136 |
|
|
input ocd2stg3_inc;
|
137 |
|
|
input ocd2stg3_dec;
|
138 |
|
|
|
139 |
|
|
wire setup_po =
|
140 |
|
|
lim2stg2_inc || lim2stg2_dec || lim2stg3_inc || lim2stg3_dec ||
|
141 |
|
|
ocd2stg2_inc || ocd2stg2_dec || ocd2stg3_inc || ocd2stg3_dec || ocd_cntlr2stg2_dec;
|
142 |
|
|
|
143 |
|
|
always @(*) begin
|
144 |
|
|
po_setup_ns = po_setup_r;
|
145 |
|
|
if (rst) po_setup_ns = 2'b00;
|
146 |
|
|
else if (setup_po) po_setup_ns = 2'b11;
|
147 |
|
|
else if (|po_setup_r) po_setup_ns = po_setup_r - 2'b01;
|
148 |
|
|
end
|
149 |
|
|
|
150 |
|
|
reg po_en_stg23_r;
|
151 |
|
|
wire po_en_stg23_ns = ~rst && po_setup_r == 2'b01;
|
152 |
|
|
always @(posedge clk) po_en_stg23_r <= #TCQ po_en_stg23_ns;
|
153 |
|
|
output po_en_stg23;
|
154 |
|
|
assign po_en_stg23 = po_en_stg23_r;
|
155 |
|
|
|
156 |
|
|
wire sel_stg3 = lim2stg3_inc || lim2stg3_dec || ocd2stg3_inc || ocd2stg3_dec;
|
157 |
|
|
|
158 |
|
|
reg [POW_WIDTH-1:0] po_wait_r, po_wait_ns;
|
159 |
|
|
reg po_stg23_sel_r;
|
160 |
|
|
// Reset to zero at the end. Makes adjust stg2 at end of centering
|
161 |
|
|
// get the correct value of po_counter_read_val.
|
162 |
|
|
wire po_stg23_sel_ns = ~rst && (setup_po
|
163 |
|
|
? sel_stg3
|
164 |
|
|
? 1'b1
|
165 |
|
|
: 1'b0
|
166 |
|
|
: po_stg23_sel_r && !(po_wait_r == ONE[POW_WIDTH-1:0]));
|
167 |
|
|
always @(posedge clk) po_stg23_sel_r <= #TCQ po_stg23_sel_ns;
|
168 |
|
|
output po_stg23_sel;
|
169 |
|
|
assign po_stg23_sel = po_stg23_sel_r;
|
170 |
|
|
|
171 |
|
|
wire po_inc = lim2stg2_inc || lim2stg3_inc || ocd2stg2_inc || ocd2stg3_inc;
|
172 |
|
|
|
173 |
|
|
reg po_stg23_incdec_r;
|
174 |
|
|
wire po_stg23_incdec_ns = ~rst && (setup_po ? po_inc ? 1'b1 : 1'b0 : po_stg23_incdec_r);
|
175 |
|
|
always @(posedge clk) po_stg23_incdec_r <= #TCQ po_stg23_incdec_ns;
|
176 |
|
|
output po_stg23_incdec;
|
177 |
|
|
assign po_stg23_incdec = po_stg23_incdec_r;
|
178 |
|
|
|
179 |
|
|
|
180 |
|
|
always @(posedge clk) po_wait_r <= #TCQ po_wait_ns;
|
181 |
|
|
always @(*) begin
|
182 |
|
|
po_wait_ns = po_wait_r;
|
183 |
|
|
if (rst) po_wait_ns = {POW_WIDTH{1'b0}};
|
184 |
|
|
else if (po_en_stg23_r) po_wait_ns = PO_WAIT[POW_WIDTH-1:0] - ONE[POW_WIDTH-1:0];
|
185 |
|
|
else if (po_wait_r != {POW_WIDTH{1'b0}}) po_wait_ns = po_wait_r - ONE[POW_WIDTH-1:0];
|
186 |
|
|
end
|
187 |
|
|
|
188 |
|
|
wire po_rdy_ns = ~(setup_po || |po_setup_r || |po_wait_ns);
|
189 |
|
|
reg po_rdy_r;
|
190 |
|
|
always @(posedge clk) po_rdy_r <= #TCQ po_rdy_ns;
|
191 |
|
|
|
192 |
|
|
output po_rdy;
|
193 |
|
|
assign po_rdy = po_rdy_r;
|
194 |
|
|
|
195 |
|
|
input [6*DQS_WIDTH-1:0] wl_po_fine_cnt;
|
196 |
|
|
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
|
197 |
|
|
wire [6*DQS_WIDTH-1:0] wl_po_fine_shifted = wl_po_fine_cnt >> oclkdelay_calib_cnt*6;
|
198 |
|
|
output [5:0] wl_po_fine_cnt_sel;
|
199 |
|
|
assign wl_po_fine_cnt_sel = wl_po_fine_shifted[5:0];
|
200 |
|
|
|
201 |
|
|
input lim2init_prech_req;
|
202 |
|
|
input ocd_prech_req;
|
203 |
|
|
output oclk_prech_req;
|
204 |
|
|
assign oclk_prech_req = ocd_prech_req || lim2init_prech_req;
|
205 |
|
|
|
206 |
|
|
endmodule // mig_7series_v2_3_ddr_phy_ocd_mux
|
207 |
|
|
|