1 |
2 |
ZTEX |
# fxclk_in, 26 MHz (period of 38.75ns makes Vivado happy)
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2 |
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create_clock -period 38.75 -name fxclk_in [get_ports fxclk_in]
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3 |
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set_property PACKAGE_PIN P15 [get_ports fxclk_in]
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4 |
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set_property IOSTANDARD LVCMOS33 [get_ports fxclk_in]
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5 |
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6 |
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# IFCLK, 104 MHz
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7 |
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create_clock -name ifclk_in -period 9.615 [get_ports ifclk_in]
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8 |
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set_property PACKAGE_PIN P17 [get_ports ifclk_in]
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9 |
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set_property IOSTANDARD LVCMOS33 [get_ports ifclk_in]
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10 |
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11 |
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# GPIO
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12 |
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set_property PACKAGE_PIN V10 [get_ports gpio_n[0]]
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13 |
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set_property PACKAGE_PIN T14 [get_ports gpio_n[1]]
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14 |
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set_property PACKAGE_PIN V15 [get_ports gpio_n[2]]
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15 |
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set_property PACKAGE_PIN R16 [get_ports gpio_n[3]]
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16 |
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set_property IOSTANDARD LVCMOS33 [get_ports {gpio_n[*]}]
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17 |
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set_property DRIVE 4 [get_ports {gpio_n[*]}]
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18 |
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set_property PULLUP true [get_ports {gpio_n[*]}]
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19 |
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20 |
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# reset
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21 |
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set_property PACKAGE_PIN V16 [get_ports reset]
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22 |
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set_property IOSTANDARD LVCMOS33 [get_ports reset]
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23 |
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24 |
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# fd
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25 |
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set_property PACKAGE_PIN K17 [get_ports {fd[0]}]
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26 |
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set_property PACKAGE_PIN K18 [get_ports {fd[1]}]
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27 |
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set_property PACKAGE_PIN L14 [get_ports {fd[2]}]
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28 |
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set_property PACKAGE_PIN M14 [get_ports {fd[3]}]
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29 |
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set_property PACKAGE_PIN L18 [get_ports {fd[4]}]
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30 |
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set_property PACKAGE_PIN M18 [get_ports {fd[5]}]
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31 |
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set_property PACKAGE_PIN R12 [get_ports {fd[6]}]
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32 |
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set_property PACKAGE_PIN R13 [get_ports {fd[7]}]
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33 |
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set_property PACKAGE_PIN M13 [get_ports {fd[8]}]
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34 |
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set_property PACKAGE_PIN R18 [get_ports {fd[9]}]
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35 |
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set_property PACKAGE_PIN T18 [get_ports {fd[10]}]
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36 |
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set_property PACKAGE_PIN N14 [get_ports {fd[11]}]
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37 |
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set_property PACKAGE_PIN P14 [get_ports {fd[12]}]
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38 |
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set_property PACKAGE_PIN P18 [get_ports {fd[13]}]
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39 |
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set_property PACKAGE_PIN M16 [get_ports {fd[14]}]
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40 |
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set_property PACKAGE_PIN M17 [get_ports {fd[15]}]
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41 |
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set_property IOSTANDARD LVCMOS33 [get_ports {fd[*]}]
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42 |
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set_property DRIVE 4 [get_ports {fd[*]}]
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43 |
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44 |
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# EMPTY
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45 |
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set_property PACKAGE_PIN V11 [get_ports EMPTY_FLAG]
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46 |
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set_property IOSTANDARD LVCMOS33 [get_ports EMPTY_FLAG]
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47 |
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48 |
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# FULL
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49 |
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set_property PACKAGE_PIN V14 [get_ports FULL_FLAG]
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50 |
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set_property IOSTANDARD LVCMOS33 [get_ports FULL_FLAG]
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51 |
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52 |
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# SLOE
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53 |
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set_property PACKAGE_PIN U13 [get_ports SLOE]
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54 |
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set_property IOSTANDARD LVCMOS33 [get_ports SLOE]
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55 |
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56 |
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# SLWR/WE
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57 |
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set_property PACKAGE_PIN U11 [get_ports SLWR]
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58 |
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set_property IOSTANDARD LVCMOS33 [get_ports SLWR]
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59 |
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#set_property DRIVE 4 [get_ports SLWR]
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60 |
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#set_property SLEW FAST [get_ports SLWR]
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61 |
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62 |
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# PKTEND
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63 |
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set_property PACKAGE_PIN U12 [get_ports PKTEND]
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64 |
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set_property IOSTANDARD LVCMOS33 [get_ports PKTEND]
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65 |
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66 |
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# SLRD
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67 |
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set_property PACKAGE_PIN V12 [get_ports SLRD]
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68 |
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set_property IOSTANDARD LVCMOS33 [get_ports SLRD]
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69 |
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70 |
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71 |
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# I/O delays
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72 |
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set_input_delay -clock ifclk_in -min 0 [get_ports {*_FLAG fd[*]}]
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73 |
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set_input_delay -clock ifclk_in -max 3.5 [get_ports {*_FLAG fd[*]}]
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74 |
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set_output_delay -clock ifclk_in -min 0 [get_ports {SLRD SLWR PKTEND}]
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75 |
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set_output_delay -clock ifclk_in -max 7 [get_ports {SLRD SLWR PKTEND}]
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76 |
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77 |
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# LED's
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78 |
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set_property PACKAGE_PIN T11 [get_ports led]
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79 |
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set_property IOSTANDARD LVCMOS33 [get_ports led]
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80 |
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set_property DRIVE 12 [get_ports led]
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81 |
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82 |
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set_property PACKAGE_PIN H15 [get_ports {led1[0]}] ;# A6 / B21~IO_L21P_T3_DQS_16
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83 |
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set_property PACKAGE_PIN J13 [get_ports {led1[1]}] ;# B6 / A21~IO_L21N_T3_DQS_16
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84 |
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set_property PACKAGE_PIN J14 [get_ports {led1[2]}] ;# A7 / D20~IO_L19P_T3_16
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85 |
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set_property PACKAGE_PIN H14 [get_ports {led1[3]}] ;# B7 / C20~IO_L19N_T3_VREF_16
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86 |
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set_property PACKAGE_PIN H17 [get_ports {led1[4]}] ;# A8 / B20~IO_L16P_T2_16
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87 |
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set_property PACKAGE_PIN G14 [get_ports {led1[5]}] ;# B8 / A20~IO_L16N_T2_16
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88 |
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set_property PACKAGE_PIN G17 [get_ports {led1[6]}] ;# A9 / C19~IO_L13N_T2_MRCC_16
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89 |
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set_property PACKAGE_PIN G16 [get_ports {led1[7]}] ;# B9 / A19~IO_L17N_T2_16
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90 |
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set_property PACKAGE_PIN G18 [get_ports {led1[8]}] ;# A10 / C18~IO_L13P_T2_MRCC_16
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91 |
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set_property PACKAGE_PIN H16 [get_ports {led1[9]}] ;# B10 / A18~IO_L17P_T2_16
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92 |
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set_property IOSTANDARD LVCMOS33 [get_ports {led1[*]}]
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93 |
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set_property DRIVE 12 [get_ports {led1[*]}]
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94 |
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95 |
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set_property PACKAGE_PIN U9 [get_ports {led2[0]}] ;# C3 / AB17~IO_L2N_T0_13
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96 |
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set_property PACKAGE_PIN V9 [get_ports {led2[1]}] ;# D3 / AB16~IO_L2P_T0_13
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97 |
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set_property PACKAGE_PIN U8 [get_ports {led2[2]}] ;# C4 / Y16~IO_L1P_T0_13
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98 |
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set_property PACKAGE_PIN V7 [get_ports {led2[3]}] ;# D4 / AA16~IO_L1N_T0_13
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99 |
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set_property PACKAGE_PIN U7 [get_ports {led2[4]}] ;# C5 / AA15~IO_L4P_T0_13
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100 |
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set_property PACKAGE_PIN V6 [get_ports {led2[5]}] ;# D5 / AB15~IO_L4N_T0_13
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101 |
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set_property PACKAGE_PIN U6 [get_ports {led2[6]}] ;# C6 / Y13~IO_L5P_T0_13
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102 |
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set_property PACKAGE_PIN V5 [get_ports {led2[7]}] ;# D6 / AA14~IO_L5N_T0_13
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103 |
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set_property PACKAGE_PIN T8 [get_ports {led2[8]}] ;# C7 / W14~IO_L6P_T0_13
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104 |
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set_property PACKAGE_PIN V4 [get_ports {led2[9]}] ;# D7 / Y14~IO_L6N_T0_VREF_13
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105 |
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set_property PACKAGE_PIN R8 [get_ports {led2[10]}] ;# C8 / AA13~IO_L3P_T0_DQS_13
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106 |
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set_property PACKAGE_PIN T5 [get_ports {led2[11]}] ;# D8 / AB13~IO_L3N_T0_DQS_13
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107 |
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set_property PACKAGE_PIN R7 [get_ports {led2[12]}] ;# C9 / AB12~IO_L7N_T1_13
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108 |
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set_property PACKAGE_PIN T4 [get_ports {led2[13]}] ;# D9 / AB11~IO_L7P_T1_13
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109 |
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set_property PACKAGE_PIN T6 [get_ports {led2[14]}] ;# C10 / W12~IO_L12N_T1_MRCC_13
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110 |
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set_property PACKAGE_PIN U4 [get_ports {led2[15]}] ;# D10 / W11~IO_L12P_T1_MRCC_13
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111 |
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set_property PACKAGE_PIN R6 [get_ports {led2[16]}] ;# C11 / AA11~IO_L9N_T1_DQS_13
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112 |
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set_property PACKAGE_PIN U3 [get_ports {led2[17]}] ;# D11 / AA10~IO_L9P_T1_DQS_13
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113 |
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set_property PACKAGE_PIN R5 [get_ports {led2[18]}] ;# C12 / AA9~IO_L8P_T1_13
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114 |
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set_property PACKAGE_PIN V1 [get_ports {led2[19]}] ;# D12 / AB10~IO_L8N_T1_13
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115 |
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set_property IOSTANDARD LVCMOS33 [get_ports {led2[*]}]
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116 |
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set_property DRIVE 12 [get_ports {led2[*]}]
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117 |
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118 |
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# switches
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119 |
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#set_property PACKAGE_PIN F18 [get_ports SW7] ;# A11 / B18~IO_L11N_T1_SRCC_16
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120 |
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#set_property PACKAGE_PIN F16 [get_ports SW8] ;# B11 / D17~IO_L12P_T1_MRCC_16
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121 |
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#set_property PACKAGE_PIN E18 [get_ports SW9] ;# A12 / B17~IO_L11P_T1_SRCC_16
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122 |
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set_property PACKAGE_PIN F15 [get_ports SW10] ;# B12 / C17~IO_L12N_T1_MRCC_16
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123 |
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set_property IOSTANDARD LVCMOS33 [get_ports {SW*}]
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124 |
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set_property PULLUP true [get_ports {SW*}]
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125 |
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126 |
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# location constraints
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127 |
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#set_property LOC PLLE2_ADV_X1Y1 [get_cells dram_fifo_inst/dram_fifo_pll_inst]
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128 |
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129 |
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# TIG's
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130 |
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set_false_path -from [get_clocks *ifclk_out] -to [get_clocks *clk200_in]
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131 |
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set_false_path -from [get_clocks *ifclk_out] -to [get_clocks ]
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132 |
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set_false_path -from [get_clocks *clk_pll_i] -to [get_clocks *ifclk_out]
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133 |
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134 |
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# bitstream settings
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135 |
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set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
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136 |
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set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]
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137 |
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]
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138 |
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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