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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : bank_compare.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Tue Jun 30 2009
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// \___\/\___\
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//
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//Device : 7-Series
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//Design Name : DDR3 SDRAM
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//Purpose :
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//Reference :
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//Revision History :
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//*****************************************************************************
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// This block stores the request for this bank machine.
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//
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// All possible new requests are compared against the request stored
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// here. The compare results are shared with the bank machines and
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// is used to determine where to enqueue a new request.
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`timescale 1ps/1ps
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module mig_7series_v2_3_bank_compare #
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(parameter BANK_WIDTH = 3,
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parameter TCQ = 100,
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parameter BURST_MODE = "8",
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parameter COL_WIDTH = 12,
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parameter DATA_BUF_ADDR_WIDTH = 8,
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parameter ECC = "OFF",
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parameter RANK_WIDTH = 2,
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parameter RANKS = 4,
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parameter ROW_WIDTH = 16)
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(/*AUTOARG*/
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// Outputs
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req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r,
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req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r,
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rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr,
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req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r,
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// Inputs
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clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd,
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sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority,
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maint_rank_r, maint_zq_r, maint_sre_r, auto_pre_r, rd_half_rmw, act_wait_r
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);
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input clk;
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input idle_ns;
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input idle_r;
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input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;
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output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
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wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns =
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idle_r
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? data_buf_addr
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: req_data_buf_addr_r;
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always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns;
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input periodic_rd_insert;
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reg req_periodic_rd_r_lcl;
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wire req_periodic_rd_ns = idle_ns
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? periodic_rd_insert
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: req_periodic_rd_r_lcl;
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always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns;
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output wire req_periodic_rd_r;
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assign req_periodic_rd_r = req_periodic_rd_r_lcl;
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input size;
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wire req_size_r_lcl;
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generate
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if (BURST_MODE == "4") begin : burst_mode_4
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assign req_size_r_lcl = 1'b0;
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end
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else
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if (BURST_MODE == "8") begin : burst_mode_8
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assign req_size_r_lcl = 1'b1;
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end
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else
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if (BURST_MODE == "OTF") begin : burst_mode_otf
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reg req_size;
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wire req_size_ns = idle_ns
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? (periodic_rd_insert || size)
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: req_size;
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always @(posedge clk) req_size <= #TCQ req_size_ns;
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assign req_size_r_lcl = req_size;
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end
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endgenerate
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output wire req_size_r;
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assign req_size_r = req_size_r_lcl;
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input [2:0] cmd;
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reg [2:0] req_cmd_r;
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wire [2:0] req_cmd_ns = idle_ns
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? (periodic_rd_insert ? 3'b001 : cmd)
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: req_cmd_r;
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always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns;
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`ifdef MC_SVA
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rd_wr_only_wo_ecc: assert property
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(@(posedge clk) ((ECC != "OFF") || idle_ns || ~|req_cmd_ns[2:1]));
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`endif
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input sending_col;
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reg rd_wr_r_lcl;
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wire rd_wr_ns = idle_ns
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? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0])
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: ~sending_col && rd_wr_r_lcl;
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always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns;
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output wire rd_wr_r;
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assign rd_wr_r = rd_wr_r_lcl;
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input [RANK_WIDTH-1:0] rank;
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input [RANK_WIDTH-1:0] periodic_rd_rank_r;
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reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}};
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reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}};
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generate
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if (RANKS != 1) begin
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always @(/*AS*/idle_ns or periodic_rd_insert
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or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns
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? periodic_rd_insert
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? periodic_rd_rank_r
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: rank
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: req_rank_r_lcl;
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always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns;
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end
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endgenerate
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output wire [RANK_WIDTH-1:0] req_rank_r;
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assign req_rank_r = req_rank_r_lcl;
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input [BANK_WIDTH-1:0] bank;
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reg [BANK_WIDTH-1:0] req_bank_r_lcl;
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wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl;
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always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns;
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output wire[BANK_WIDTH-1:0] req_bank_r;
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assign req_bank_r = req_bank_r_lcl;
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input [ROW_WIDTH-1:0] row;
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reg [ROW_WIDTH-1:0] req_row_r_lcl;
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wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl;
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always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns;
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output wire [ROW_WIDTH-1:0] req_row_r;
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assign req_row_r = req_row_r_lcl;
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// Make req_col_r as wide as the max row address. This
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// makes it easier to deal with indexing different column widths.
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input [COL_WIDTH-1:0] col;
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reg [15:0] req_col_r = 16'b0;
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wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0];
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always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns;
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reg req_wr_r_lcl;
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wire req_wr_ns = idle_ns
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? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0])
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: req_wr_r_lcl;
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always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns;
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output wire req_wr_r;
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assign req_wr_r = req_wr_r_lcl;
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input hi_priority;
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output reg req_priority_r;
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wire req_priority_ns = idle_ns ? hi_priority : req_priority_r;
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always @(posedge clk) req_priority_r <= #TCQ req_priority_ns;
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wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert
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? periodic_rd_rank_r
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: rank));
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wire bank_hit = (req_bank_r_lcl == bank);
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wire rank_bank_hit = rank_hit && bank_hit;
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output reg rb_hit_busy_r; // rank-bank hit on non idle row machine
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wire rb_hit_busy_ns_lcl;
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assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns;
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output wire rb_hit_busy_ns;
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assign rb_hit_busy_ns = rb_hit_busy_ns_lcl;
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wire row_hit_ns = (req_row_r_lcl == row);
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output reg row_hit_r;
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always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl;
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always @(posedge clk) row_hit_r <= #TCQ row_hit_ns;
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input [RANK_WIDTH-1:0] maint_rank_r;
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input maint_zq_r;
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input maint_sre_r;
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output wire maint_hit;
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assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r || maint_sre_r;
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// Assemble column address. Structure to be the same
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// width as the row address. This makes it easier
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// for the downstream muxing. Depending on the sizes
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// of the row and column addresses, fill in as appropriate.
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input auto_pre_r;
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input rd_half_rmw;
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reg [15:0] col_addr_template = 16'b0;
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always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r
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or req_size_r_lcl) begin
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col_addr_template = req_col_r;
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col_addr_template[10] = auto_pre_r && ~rd_half_rmw;
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col_addr_template[11] = req_col_r[10];
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col_addr_template[12] = req_size_r_lcl;
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col_addr_template[13] = req_col_r[11];
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end
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output wire [ROW_WIDTH-1:0] col_addr;
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assign col_addr = col_addr_template[ROW_WIDTH-1:0];
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output wire req_ras;
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output wire req_cas;
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output wire row_cmd_wr;
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input act_wait_r;
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assign req_ras = 1'b0;
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assign req_cas = 1'b1;
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assign row_cmd_wr = act_wait_r;
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output reg [ROW_WIDTH-1:0] row_addr;
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always @(/*AS*/act_wait_r or req_row_r_lcl) begin
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row_addr = req_row_r_lcl;
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// This causes all precharges to be precharge single bank command.
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if (~act_wait_r) row_addr[10] = 1'b0;
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end
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// Indicate which, if any, rank this bank machine is busy with.
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// Not registering the result would probably be more accurate, but
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// would create timing issues. This is used for refresh banking, perfect
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// accuracy is not required.
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localparam ONE = 1;
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output reg [RANKS-1:0] rank_busy_r;
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wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns);
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always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns;
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endmodule // bank_compare
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