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//*****************************************************************************
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// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: ddr_calib_top.v
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// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:06 $
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// \ \ / \ Date Created: Aug 03 2009
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// \___\/\___\
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//
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//Device: 7 Series
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//Design Name: DDR3 SDRAM
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//Purpose:
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//Purpose:
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// Top-level for memory physical layer (PHY) interface
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// NOTES:
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// 1. Need to support multiple copies of CS outputs
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// 2. DFI_DRAM_CKE_DISABLE not supported
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//
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//Reference:
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//Revision History:
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//*****************************************************************************
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/******************************************************************************
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**$Id: ddr_calib_top.v,v 1.1 2011/06/02 08:35:06 mishra Exp $
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**$Date: 2011/06/02 08:35:06 $
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**$Author: mishra $
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**$Revision: 1.1 $
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**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_calib_top.v,v $
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******************************************************************************/
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`timescale 1ps/1ps
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module mig_7series_v2_3_ddr_calib_top #
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(
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parameter TCQ = 100,
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parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
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parameter tCK = 2500, // DDR3 SDRAM clock period
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parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3
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parameter CLK_PERIOD = 3333, // Internal clock period (in ps)
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parameter N_CTL_LANES = 3, // # of control byte lanes in the PHY
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parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
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parameter PRBS_WIDTH = 8, // The PRBS sequence is 2^PRBS_WIDTH
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parameter HIGHEST_LANE = 4,
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parameter HIGHEST_BANK = 3,
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parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
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// five fields, one per possible I/O bank, 4 bits in each field,
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// 1 per lane data=1/ctl=0
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parameter DATA_CTL_B0 = 4'hc,
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parameter DATA_CTL_B1 = 4'hf,
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parameter DATA_CTL_B2 = 4'hf,
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parameter DATA_CTL_B3 = 4'hf,
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parameter DATA_CTL_B4 = 4'hf,
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// defines the byte lanes in I/O banks being used in the interface
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// 1- Used, 0- Unused
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parameter BYTE_LANES_B0 = 4'b1111,
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parameter BYTE_LANES_B1 = 4'b0000,
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parameter BYTE_LANES_B2 = 4'b0000,
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parameter BYTE_LANES_B3 = 4'b0000,
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parameter BYTE_LANES_B4 = 4'b0000,
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parameter DQS_BYTE_MAP
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= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
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parameter CTL_BYTE_LANE = 8'hE4, // Control byte lane map
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parameter CTL_BANK = 3'b000, // Bank used for control byte lanes
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// Slot Conifg parameters
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parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
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// DRAM bus widths
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parameter BANK_WIDTH = 2, // # of bank bits
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parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
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parameter COL_WIDTH = 10, // column address width
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parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
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parameter DQ_WIDTH = 64, // # of DQ (data)
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parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
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parameter DQS_WIDTH = 8, // # of DQS (strobe)
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parameter DRAM_WIDTH = 8, // # of DQ per DQS
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parameter ROW_WIDTH = 14, // DRAM address bus width
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parameter RANKS = 1, // # of memory ranks in the interface
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parameter CS_WIDTH = 1, // # of CS# signals in the interface
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parameter CKE_WIDTH = 1, // # of cke outputs
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parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
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parameter PER_BIT_DESKEW = "ON",
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// calibration Address. The address given below will be used for calibration
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// read and write operations.
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parameter NUM_DQSFOUND_CAL = 1020, // # of iteration of DQSFOUND calib
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parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
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parameter CALIB_COL_ADD = 12'h000, // Calibration column address
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parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
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// DRAM mode settings
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parameter AL = "0", // Additive Latency option
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parameter TEST_AL = "0", // Additive Latency for internal use
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parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T"
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parameter BURST_MODE = "8", // Burst length
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parameter BURST_TYPE = "SEQ", // Burst type
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parameter nCL = 5, // Read CAS latency (in clk cyc)
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parameter nCWL = 5, // Write CAS latency (in clk cyc)
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parameter tRFC = 110000, // Refresh-to-command delay
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parameter tREFI = 7800000, // pS Refresh-to-Refresh delay
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parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
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parameter REG_CTRL = "ON", // "ON" for registered DIMM
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parameter RTT_NOM = "60", // ODT Nominal termination value
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parameter RTT_WR = "60", // ODT Write termination value
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parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA
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// 1 - ODT output from FPGA
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parameter WRLVL = "OFF", // Enable write leveling
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parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
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parameter POC_USE_METASTABLE_SAMP = "FALSE",
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// Simulation /debug options
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parameter SIM_INIT_OPTION = "NONE", // Performs all initialization steps
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parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
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parameter CKE_ODT_AUX = "FALSE",
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parameter IDELAY_ADJ = "ON",
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parameter FINE_PER_BIT = "ON",
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parameter CENTER_COMP_MODE = "ON",
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parameter PI_VAL_ADJ = "ON",
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parameter TAPSPERKCLK = 56,
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parameter DEBUG_PORT = "OFF" // Enable debug port
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)
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(
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input clk, // Internal (logic) clock
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input rst, // Reset sync'ed to CLK
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// Slot present inputs
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input [7:0] slot_0_present,
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input [7:0] slot_1_present,
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// Hard PHY signals
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// From PHY Ctrl Block
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input phy_ctl_ready,
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input phy_ctl_full,
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input phy_cmd_full,
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input phy_data_full,
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// To PHY Ctrl Block
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output write_calib,
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output read_calib,
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output calib_ctl_wren,
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output calib_cmd_wren,
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output [1:0] calib_seq,
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output [3:0] calib_aux_out,
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output [nCK_PER_CLK -1:0] calib_cke,
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output [1:0] calib_odt,
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output [2:0] calib_cmd,
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output calib_wrdata_en,
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output [1:0] calib_rank_cnt,
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output [1:0] calib_cas_slot,
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output [5:0] calib_data_offset_0,
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output [5:0] calib_data_offset_1,
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output [5:0] calib_data_offset_2,
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output [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,
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output [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,
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output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,
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output [nCK_PER_CLK-1:0] phy_ras_n,
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output [nCK_PER_CLK-1:0] phy_cas_n,
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output [nCK_PER_CLK-1:0] phy_we_n,
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output phy_reset_n,
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// To hard PHY wrapper
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output reg [5:0] calib_sel/* synthesis syn_maxfan = 10 */,
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output reg calib_in_common/* synthesis syn_maxfan = 10 */,
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output reg [HIGHEST_BANK-1:0] calib_zero_inputs/* synthesis syn_maxfan = 10 */,
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output reg [HIGHEST_BANK-1:0] calib_zero_ctrl,
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output phy_if_empty_def,
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output reg phy_if_reset,
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// output reg ck_addr_ctl_delay_done,
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// From DQS Phaser_In
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input pi_phaselocked,
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input pi_phase_locked_all,
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input pi_found_dqs,
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input pi_dqs_found_all,
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input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
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input [5:0] pi_counter_read_val,
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// To DQS Phaser_In
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output [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
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output pi_en_stg2_f,
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output pi_stg2_f_incdec,
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output pi_stg2_load,
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output [5:0] pi_stg2_reg_l,
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// To DQ IDELAY
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output idelay_ce,
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output idelay_inc,
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output idelay_ld,
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// To DQS Phaser_Out
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output [2:0] po_sel_stg2stg3 /* synthesis syn_maxfan = 3 */,
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output [2:0] po_stg2_c_incdec /* synthesis syn_maxfan = 3 */,
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output [2:0] po_en_stg2_c /* synthesis syn_maxfan = 3 */,
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output [2:0] po_stg2_f_incdec /* synthesis syn_maxfan = 3 */,
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output [2:0] po_en_stg2_f /* synthesis syn_maxfan = 3 */,
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output po_counter_load_en,
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input [8:0] po_counter_read_val,
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// To command Phaser_Out
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input phy_if_empty,
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input [4:0] idelaye2_init_val,
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input [5:0] oclkdelay_init_val,
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input tg_err,
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output rst_tg_mc,
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// Write data to OUT_FIFO
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output [2*nCK_PER_CLK*DQ_WIDTH-1:0]phy_wrdata,
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// To CNTVALUEIN input of DQ IDELAYs for perbit de-skew
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output [5*RANKS*DQ_WIDTH-1:0] dlyval_dq,
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// IN_FIFO read enable during write leveling, write calibration,
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// and read leveling
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// Read data from hard PHY fans out to mc and calib logic
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input[2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata,
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// To MC
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output [6*RANKS-1:0] calib_rd_data_offset_0,
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output [6*RANKS-1:0] calib_rd_data_offset_1,
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output [6*RANKS-1:0] calib_rd_data_offset_2,
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output phy_rddata_valid,
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output calib_writes,
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(* max_fanout = 50 *) output reg init_calib_complete/* synthesis syn_maxfan = 10 */,
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output init_wrcal_complete,
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output pi_phase_locked_err,
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output pi_dqsfound_err,
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output wrcal_err,
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input pd_out,
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// input mmcm_ps_clk, //phase shift clock
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// input oclkdelay_fb_clk, //Write DQS feedback clk
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//phase shift clock control
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output psen,
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output psincdec,
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input psdone,
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input poc_sample_pd,
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// Debug Port
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output dbg_pi_phaselock_start,
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output dbg_pi_dqsfound_start,
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output dbg_pi_dqsfound_done,
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output dbg_wrcal_start,
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output dbg_wrcal_done,
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output dbg_wrlvl_start,
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output dbg_wrlvl_done,
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output dbg_wrlvl_err,
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output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
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output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
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output [255:0] dbg_phy_wrlvl,
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output [5:0] dbg_tap_cnt_during_wrlvl,
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output dbg_wl_edge_detect_valid,
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output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
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// Write Calibration Logic
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output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
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output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
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output [99:0] dbg_phy_wrcal,
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// Read leveling logic
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output [1:0] dbg_rdlvl_start,
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output [1:0] dbg_rdlvl_done,
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output [1:0] dbg_rdlvl_err,
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output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
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output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
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|
|
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
|
298 |
|
|
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
|
299 |
|
|
|
300 |
|
|
// Delay control
|
301 |
|
|
input [11:0] device_temp,
|
302 |
|
|
input tempmon_sample_en,
|
303 |
|
|
input dbg_sel_pi_incdec,
|
304 |
|
|
input dbg_sel_po_incdec,
|
305 |
|
|
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
|
306 |
|
|
input dbg_pi_f_inc,
|
307 |
|
|
input dbg_pi_f_dec,
|
308 |
|
|
input dbg_po_f_inc,
|
309 |
|
|
input dbg_po_f_stg23_sel,
|
310 |
|
|
input dbg_po_f_dec,
|
311 |
|
|
input dbg_idel_up_all,
|
312 |
|
|
input dbg_idel_down_all,
|
313 |
|
|
input dbg_idel_up_cpt,
|
314 |
|
|
input dbg_idel_down_cpt,
|
315 |
|
|
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
|
316 |
|
|
input dbg_sel_all_idel_cpt,
|
317 |
|
|
output [255:0] dbg_phy_rdlvl, // Read leveling calibration
|
318 |
|
|
output [255:0] dbg_calib_top, // General PHY debug
|
319 |
|
|
output dbg_oclkdelay_calib_start,
|
320 |
|
|
output dbg_oclkdelay_calib_done,
|
321 |
|
|
output [255:0] dbg_phy_oclkdelay_cal,
|
322 |
|
|
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
|
323 |
|
|
output [255:0] dbg_phy_init,
|
324 |
|
|
output [255:0] dbg_prbs_rdlvl,
|
325 |
|
|
output [255:0] dbg_dqs_found_cal,
|
326 |
|
|
|
327 |
|
|
output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r,
|
328 |
|
|
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
|
329 |
|
|
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,
|
330 |
|
|
output reg [DQS_CNT_WIDTH:0] byte_sel_cnt,
|
331 |
|
|
output [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit
|
332 |
|
|
output fine_delay_sel
|
333 |
|
|
);
|
334 |
|
|
|
335 |
|
|
function integer clogb2 (input integer size);
|
336 |
|
|
begin
|
337 |
|
|
size = size - 1;
|
338 |
|
|
for (clogb2=1; size>1; clogb2=clogb2+1)
|
339 |
|
|
size = size >> 1;
|
340 |
|
|
end
|
341 |
|
|
endfunction
|
342 |
|
|
|
343 |
|
|
// Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center
|
344 |
|
|
// align DQ and DQS on writes. Round (up or down) value to nearest integer
|
345 |
|
|
// localparam integer SHIFT_TBY4_TAP
|
346 |
|
|
// = (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) /
|
347 |
|
|
// (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4);
|
348 |
|
|
|
349 |
|
|
// Calculate number of slots in the system
|
350 |
|
|
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
|
351 |
|
|
|
352 |
|
|
localparam OCAL_EN = ((SIM_CAL_OPTION == "FAST_CAL") || (tCK > 2500)) ? "OFF" : "ON";
|
353 |
|
|
|
354 |
|
|
// Different CTL_LANES value for DDR2. In DDR2 during DQS found all
|
355 |
|
|
// the add,ctl & data phaser out fine delays will be adjusted.
|
356 |
|
|
// In DDR3 only the add/ctrl lane delays will be adjusted
|
357 |
|
|
localparam DQS_FOUND_N_CTL_LANES = (DRAM_TYPE == "DDR3") ? N_CTL_LANES : 1;
|
358 |
|
|
|
359 |
|
|
localparam DQSFOUND_CAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && tCK > 2500)) ? "LEFT" : "RIGHT"; // IO Bank used for Memory I/F: "LEFT", "RIGHT"
|
360 |
|
|
|
361 |
|
|
localparam FIXED_VICTIM = (SIM_CAL_OPTION == "NONE") ? "FALSE" : "TRUE";
|
362 |
|
|
localparam VCCO_PAT_EN = 1; // Enable VCCO pattern during calibration
|
363 |
|
|
localparam VCCAUX_PAT_EN = 1; // Enable VCCAUX pattern during calibration
|
364 |
|
|
localparam ISI_PAT_EN = 1; // Enable VCCO pattern during calibration
|
365 |
|
|
|
366 |
|
|
//Per-bit deskew for higher freqency (>800Mhz)
|
367 |
|
|
//localparam FINE_DELAY = (tCK < 1250) ? "ON" : "OFF";
|
368 |
|
|
|
369 |
|
|
//BYPASS
|
370 |
|
|
localparam BYPASS_COMPLEX_RDLVL = (tCK > 2500) ? "TRUE": "FALSE"; //"TRUE";
|
371 |
|
|
localparam BYPASS_COMPLEX_OCAL = "TRUE";
|
372 |
|
|
//localparam BYPASS_COMPLEX_OCAL = ((DRAM_TYPE == "DDR2") || (nCK_PER_CLK == 2) || (OCAL_EN == "OFF")) ? "TRUE" : "FALSE";
|
373 |
|
|
|
374 |
|
|
// 8*tREFI in ps is divided by the fabric clock period in ps
|
375 |
|
|
// 270 fabric clock cycles is subtracted to account for PRECHARGE, WR, RD times
|
376 |
|
|
localparam REFRESH_TIMER = (SIM_CAL_OPTION == "NONE") ? (8*tREFI/(tCK*nCK_PER_CLK)) - 270 : 10795;
|
377 |
|
|
|
378 |
|
|
localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER);
|
379 |
|
|
|
380 |
|
|
wire [2*8*nCK_PER_CLK-1:0] prbs_seed;
|
381 |
|
|
//wire [2*8*nCK_PER_CLK-1:0] prbs_out;
|
382 |
|
|
wire [8*DQ_WIDTH-1:0] prbs_out;
|
383 |
|
|
wire [7:0] prbs_rise0;
|
384 |
|
|
wire [7:0] prbs_fall0;
|
385 |
|
|
wire [7:0] prbs_rise1;
|
386 |
|
|
wire [7:0] prbs_fall1;
|
387 |
|
|
wire [7:0] prbs_rise2;
|
388 |
|
|
wire [7:0] prbs_fall2;
|
389 |
|
|
wire [7:0] prbs_rise3;
|
390 |
|
|
wire [7:0] prbs_fall3;
|
391 |
|
|
//wire [2*8*nCK_PER_CLK-1:0] prbs_o;
|
392 |
|
|
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o;
|
393 |
|
|
wire dqsfound_retry;
|
394 |
|
|
wire dqsfound_retry_done;
|
395 |
|
|
wire phy_rddata_en;
|
396 |
|
|
wire prech_done;
|
397 |
|
|
wire rdlvl_stg1_done;
|
398 |
|
|
reg rdlvl_stg1_done_r1;
|
399 |
|
|
wire pi_dqs_found_done;
|
400 |
|
|
wire rdlvl_stg1_err;
|
401 |
|
|
wire pi_dqs_found_err;
|
402 |
|
|
wire wrcal_pat_resume;
|
403 |
|
|
wire wrcal_resume_w;
|
404 |
|
|
wire rdlvl_prech_req;
|
405 |
|
|
wire rdlvl_last_byte_done;
|
406 |
|
|
wire rdlvl_stg1_start;
|
407 |
|
|
wire rdlvl_stg1_rank_done;
|
408 |
|
|
wire rdlvl_assrt_common;
|
409 |
|
|
wire pi_dqs_found_start;
|
410 |
|
|
wire pi_dqs_found_rank_done;
|
411 |
|
|
wire wl_sm_start;
|
412 |
|
|
wire wrcal_start;
|
413 |
|
|
wire wrcal_rd_wait;
|
414 |
|
|
wire wrcal_prech_req;
|
415 |
|
|
wire wrcal_pat_err;
|
416 |
|
|
wire wrcal_done;
|
417 |
|
|
wire wrlvl_done;
|
418 |
|
|
wire wrlvl_err;
|
419 |
|
|
wire wrlvl_start;
|
420 |
|
|
wire ck_addr_cmd_delay_done;
|
421 |
|
|
wire po_ck_addr_cmd_delay_done;
|
422 |
|
|
wire pi_calib_done;
|
423 |
|
|
wire detect_pi_found_dqs;
|
424 |
|
|
wire [5:0] rd_data_offset_0;
|
425 |
|
|
wire [5:0] rd_data_offset_1;
|
426 |
|
|
wire [5:0] rd_data_offset_2;
|
427 |
|
|
wire [6*RANKS-1:0] rd_data_offset_ranks_0;
|
428 |
|
|
wire [6*RANKS-1:0] rd_data_offset_ranks_1;
|
429 |
|
|
wire [6*RANKS-1:0] rd_data_offset_ranks_2;
|
430 |
|
|
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_0;
|
431 |
|
|
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_1;
|
432 |
|
|
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_2;
|
433 |
|
|
wire cmd_po_stg2_f_incdec;
|
434 |
|
|
wire cmd_po_stg2_incdec_ddr2_c;
|
435 |
|
|
wire cmd_po_en_stg2_f;
|
436 |
|
|
wire cmd_po_en_stg2_ddr2_c;
|
437 |
|
|
wire cmd_po_stg2_c_incdec;
|
438 |
|
|
wire cmd_po_en_stg2_c;
|
439 |
|
|
wire po_stg2_ddr2_incdec;
|
440 |
|
|
wire po_en_stg2_ddr2;
|
441 |
|
|
wire dqs_po_stg2_f_incdec;
|
442 |
|
|
wire dqs_po_en_stg2_f;
|
443 |
|
|
wire dqs_wl_po_stg2_c_incdec;
|
444 |
|
|
wire wrcal_po_stg2_c_incdec;
|
445 |
|
|
wire dqs_wl_po_en_stg2_c;
|
446 |
|
|
wire wrcal_po_en_stg2_c;
|
447 |
|
|
wire [N_CTL_LANES-1:0] ctl_lane_cnt;
|
448 |
|
|
reg [N_CTL_LANES-1:0] ctl_lane_sel;
|
449 |
|
|
wire [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt;
|
450 |
|
|
wire [DQS_CNT_WIDTH:0] po_stg2_wl_cnt;
|
451 |
|
|
wire [DQS_CNT_WIDTH:0] po_stg2_ddr2_cnt;
|
452 |
|
|
wire [8:0] dqs_wl_po_stg2_reg_l;
|
453 |
|
|
wire dqs_wl_po_stg2_load;
|
454 |
|
|
wire [8:0] dqs_po_stg2_reg_l;
|
455 |
|
|
wire dqs_po_stg2_load;
|
456 |
|
|
wire dqs_po_dec_done;
|
457 |
|
|
wire pi_fine_dly_dec_done;
|
458 |
|
|
wire rdlvl_pi_stg2_f_incdec;
|
459 |
|
|
wire rdlvl_pi_stg2_f_en;
|
460 |
|
|
wire [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt;
|
461 |
|
|
//reg [DQS_CNT_WIDTH:0] byte_sel_cnt;
|
462 |
|
|
wire [3*DQS_WIDTH-1:0] wl_po_coarse_cnt;
|
463 |
|
|
wire [6*DQS_WIDTH-1:0] wl_po_fine_cnt;
|
464 |
|
|
wire phase_locked_err;
|
465 |
|
|
wire phy_ctl_rdy_dly;
|
466 |
|
|
wire idelay_ce_int;
|
467 |
|
|
wire idelay_inc_int;
|
468 |
|
|
reg idelay_ce_r1;
|
469 |
|
|
reg idelay_ce_r2;
|
470 |
|
|
reg idelay_inc_r1;
|
471 |
|
|
reg idelay_inc_r2 /* synthesis syn_maxfan = 30 */;
|
472 |
|
|
reg po_dly_req_r;
|
473 |
|
|
wire wrcal_read_req;
|
474 |
|
|
wire wrcal_act_req;
|
475 |
|
|
wire temp_wrcal_done;
|
476 |
|
|
wire tg_timer_done;
|
477 |
|
|
wire no_rst_tg_mc;
|
478 |
|
|
wire calib_complete;
|
479 |
|
|
reg reset_if_r1;
|
480 |
|
|
reg reset_if_r2;
|
481 |
|
|
reg reset_if_r3;
|
482 |
|
|
reg reset_if_r4;
|
483 |
|
|
reg reset_if_r5;
|
484 |
|
|
reg reset_if_r6;
|
485 |
|
|
reg reset_if_r7;
|
486 |
|
|
reg reset_if_r8;
|
487 |
|
|
reg reset_if_r9;
|
488 |
|
|
reg reset_if;
|
489 |
|
|
wire phy_if_reset_w;
|
490 |
|
|
wire pi_phaselock_start;
|
491 |
|
|
|
492 |
|
|
reg dbg_pi_f_inc_r;
|
493 |
|
|
reg dbg_pi_f_en_r;
|
494 |
|
|
reg dbg_sel_pi_incdec_r;
|
495 |
|
|
|
496 |
|
|
reg dbg_po_f_inc_r;
|
497 |
|
|
reg dbg_po_f_stg23_sel_r;
|
498 |
|
|
reg dbg_po_f_en_r;
|
499 |
|
|
reg dbg_sel_po_incdec_r;
|
500 |
|
|
|
501 |
|
|
reg tempmon_pi_f_inc_r;
|
502 |
|
|
reg tempmon_pi_f_en_r;
|
503 |
|
|
reg tempmon_sel_pi_incdec_r;
|
504 |
|
|
|
505 |
|
|
reg ck_addr_cmd_delay_done_r1;
|
506 |
|
|
reg ck_addr_cmd_delay_done_r2;
|
507 |
|
|
reg ck_addr_cmd_delay_done_r3;
|
508 |
|
|
reg ck_addr_cmd_delay_done_r4;
|
509 |
|
|
reg ck_addr_cmd_delay_done_r5;
|
510 |
|
|
reg ck_addr_cmd_delay_done_r6;
|
511 |
|
|
// wire oclk_init_delay_start;
|
512 |
|
|
wire oclk_prech_req;
|
513 |
|
|
wire oclk_calib_resume;
|
514 |
|
|
// wire oclk_init_delay_done;
|
515 |
|
|
wire [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
|
516 |
|
|
wire [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt;
|
517 |
|
|
wire oclkdelay_calib_start;
|
518 |
|
|
wire oclkdelay_calib_done;
|
519 |
|
|
wire complex_oclk_prech_req;
|
520 |
|
|
wire complex_oclk_calib_resume;
|
521 |
|
|
wire complex_oclkdelay_calib_start;
|
522 |
|
|
wire complex_oclkdelay_calib_done;
|
523 |
|
|
wire complex_ocal_num_samples_inc;
|
524 |
|
|
wire complex_ocal_num_samples_done_r;
|
525 |
|
|
wire [2:0] complex_ocal_rd_victim_sel;
|
526 |
|
|
wire complex_ocal_ref_req;
|
527 |
|
|
wire complex_ocal_ref_done;
|
528 |
|
|
wire [6*DQS_WIDTH-1:0] oclkdelay_left_edge_val;
|
529 |
|
|
wire [6*DQS_WIDTH-1:0] oclkdelay_right_edge_val;
|
530 |
|
|
|
531 |
|
|
wire wrlvl_final;
|
532 |
|
|
wire complex_wrlvl_final;
|
533 |
|
|
reg wrlvl_final_mux;
|
534 |
|
|
wire wrlvl_final_if_rst;
|
535 |
|
|
wire wrlvl_byte_redo;
|
536 |
|
|
wire wrlvl_byte_done;
|
537 |
|
|
wire early1_data;
|
538 |
|
|
wire early2_data;
|
539 |
|
|
//wire po_stg3_incdec;
|
540 |
|
|
//wire po_en_stg3;
|
541 |
|
|
wire po_stg23_sel;
|
542 |
|
|
wire po_stg23_incdec;
|
543 |
|
|
wire po_en_stg23;
|
544 |
|
|
wire complex_po_stg23_sel;
|
545 |
|
|
wire complex_po_stg23_incdec;
|
546 |
|
|
wire complex_po_en_stg23;
|
547 |
|
|
wire mpr_rdlvl_done;
|
548 |
|
|
wire mpr_rdlvl_start;
|
549 |
|
|
wire mpr_last_byte_done;
|
550 |
|
|
wire mpr_rnk_done;
|
551 |
|
|
wire mpr_end_if_reset;
|
552 |
|
|
wire mpr_rdlvl_err;
|
553 |
|
|
wire rdlvl_err;
|
554 |
|
|
wire prbs_rdlvl_start;
|
555 |
|
|
wire prbs_rdlvl_done;
|
556 |
|
|
reg prbs_rdlvl_done_r1;
|
557 |
|
|
wire prbs_last_byte_done;
|
558 |
|
|
wire prbs_rdlvl_prech_req;
|
559 |
|
|
wire prbs_pi_stg2_f_incdec;
|
560 |
|
|
wire prbs_pi_stg2_f_en;
|
561 |
|
|
wire complex_sample_cnt_inc;
|
562 |
|
|
wire complex_sample_cnt_inc_ocal;
|
563 |
|
|
wire [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt;
|
564 |
|
|
wire prbs_gen_clk_en;
|
565 |
|
|
wire prbs_gen_oclk_clk_en;
|
566 |
|
|
wire rd_data_offset_cal_done;
|
567 |
|
|
wire fine_adjust_done;
|
568 |
|
|
wire [N_CTL_LANES-1:0] fine_adjust_lane_cnt;
|
569 |
|
|
wire ck_po_stg2_f_indec;
|
570 |
|
|
wire ck_po_stg2_f_en;
|
571 |
|
|
wire dqs_found_prech_req;
|
572 |
|
|
wire tempmon_pi_f_inc;
|
573 |
|
|
wire tempmon_pi_f_dec;
|
574 |
|
|
wire tempmon_sel_pi_incdec;
|
575 |
|
|
wire wrcal_sanity_chk;
|
576 |
|
|
wire wrcal_sanity_chk_done;
|
577 |
|
|
wire wrlvl_done_w;
|
578 |
|
|
wire wrlvl_rank_done;
|
579 |
|
|
wire done_dqs_tap_inc;
|
580 |
|
|
wire [2:0] rd_victim_sel;
|
581 |
|
|
wire [2:0] victim_sel;
|
582 |
|
|
wire [DQS_CNT_WIDTH:0] victim_byte_cnt;
|
583 |
|
|
wire complex_wr_done;
|
584 |
|
|
wire complex_victim_inc;
|
585 |
|
|
|
586 |
|
|
wire reset_rd_addr;
|
587 |
|
|
wire read_pause;
|
588 |
|
|
wire complex_ocal_reset_rd_addr;
|
589 |
|
|
|
590 |
|
|
wire oclkdelay_center_calib_start;
|
591 |
|
|
wire poc_error;
|
592 |
|
|
|
593 |
|
|
wire prbs_ignore_first_byte;
|
594 |
|
|
wire prbs_ignore_last_bytes;
|
595 |
|
|
|
596 |
|
|
//stg3 tap values
|
597 |
|
|
// wire [6*DQS_WIDTH-1:0] oclkdelay_center_val;
|
598 |
|
|
|
599 |
|
|
//byte selection
|
600 |
|
|
// wire [DQS_CNT_WIDTH:0] oclkdelay_center_cnt;
|
601 |
|
|
|
602 |
|
|
//INC/DEC for stg3 taps
|
603 |
|
|
// wire ocal_ctr_po_stg23_sel;
|
604 |
|
|
// wire ocal_ctr_po_stg23_incdec;
|
605 |
|
|
// wire ocal_ctr_po_en_stg23;
|
606 |
|
|
|
607 |
|
|
//Write resume for DQS toggling
|
608 |
|
|
wire oclk_center_write_resume;
|
609 |
|
|
wire oclkdelay_center_calib_done;
|
610 |
|
|
|
611 |
|
|
//Write request to toggle DQS for limit module
|
612 |
|
|
wire lim2init_write_request;
|
613 |
|
|
wire lim_done;
|
614 |
|
|
|
615 |
|
|
// Bypass complex ocal
|
616 |
|
|
wire complex_oclkdelay_calib_start_w;
|
617 |
|
|
wire complex_oclkdelay_calib_done_w;
|
618 |
|
|
wire [2:0] complex_ocal_rd_victim_sel_w;
|
619 |
|
|
wire complex_wrlvl_final_w;
|
620 |
|
|
|
621 |
|
|
wire [255:0] dbg_ocd_lim;
|
622 |
|
|
|
623 |
|
|
//with MMCM phase detect logic
|
624 |
|
|
//wire mmcm_edge_detect_rdy; // ready for MMCM detect
|
625 |
|
|
//wire ktap_at_rightedge; // stg3 tap at right edge
|
626 |
|
|
//wire ktap_at_leftedge; // stg3 tap at left edge
|
627 |
|
|
//wire mmcm_tap_at_center; // indicate stg3 tap at center
|
628 |
|
|
//wire mmcm_ps_clkphase_ok; // ps clkphase is OK
|
629 |
|
|
//wire mmcm_edge_detect_done; // mmcm edge detect is done
|
630 |
|
|
//wire mmcm_lbclk_edges_aligned; // mmcm edge detect is done
|
631 |
|
|
//wire reset_mmcm; //mmcm detect logic reset per byte
|
632 |
|
|
|
633 |
|
|
// wire [255:0] dbg_phy_oclkdelay_center_cal;
|
634 |
|
|
|
635 |
|
|
|
636 |
|
|
//*****************************************************************************
|
637 |
|
|
// Assertions to check correctness of parameter values
|
638 |
|
|
//*****************************************************************************
|
639 |
|
|
// synthesis translate_off
|
640 |
|
|
initial
|
641 |
|
|
begin
|
642 |
|
|
if (RANKS == 0) begin
|
643 |
|
|
$display ("Error: Invalid RANKS parameter. Must be 1 or greater");
|
644 |
|
|
$finish;
|
645 |
|
|
end
|
646 |
|
|
if (phy_ctl_full == 1'b1) begin
|
647 |
|
|
$display ("Error: Incorrect phy_ctl_full input value in 2:1 or 4:1 mode");
|
648 |
|
|
$finish;
|
649 |
|
|
end
|
650 |
|
|
end
|
651 |
|
|
// synthesis translate_on
|
652 |
|
|
|
653 |
|
|
//***************************************************************************
|
654 |
|
|
// Debug
|
655 |
|
|
//***************************************************************************
|
656 |
|
|
|
657 |
|
|
assign dbg_pi_phaselock_start = pi_phaselock_start;
|
658 |
|
|
assign dbg_pi_dqsfound_start = pi_dqs_found_start;
|
659 |
|
|
assign dbg_pi_dqsfound_done = pi_dqs_found_done;
|
660 |
|
|
assign dbg_wrcal_start = wrcal_start;
|
661 |
|
|
assign dbg_wrcal_done = wrcal_done;
|
662 |
|
|
|
663 |
|
|
// Unused for now - use these as needed to bring up lower level signals
|
664 |
|
|
assign dbg_calib_top = dbg_ocd_lim;
|
665 |
|
|
|
666 |
|
|
// Write Level and write calibration debug observation ports
|
667 |
|
|
assign dbg_wrlvl_start = wrlvl_start;
|
668 |
|
|
assign dbg_wrlvl_done = wrlvl_done;
|
669 |
|
|
assign dbg_wrlvl_err = wrlvl_err;
|
670 |
|
|
|
671 |
|
|
// Read Level debug observation ports
|
672 |
|
|
assign dbg_rdlvl_start = {mpr_rdlvl_start, rdlvl_stg1_start};
|
673 |
|
|
assign dbg_rdlvl_done = {mpr_rdlvl_done, rdlvl_stg1_done};
|
674 |
|
|
assign dbg_rdlvl_err = {mpr_rdlvl_err, rdlvl_err};
|
675 |
|
|
|
676 |
|
|
assign dbg_oclkdelay_calib_done = oclkdelay_calib_done;
|
677 |
|
|
assign dbg_oclkdelay_calib_start = oclkdelay_calib_start;
|
678 |
|
|
|
679 |
|
|
//***************************************************************************
|
680 |
|
|
// Write leveling dependent signals
|
681 |
|
|
//***************************************************************************
|
682 |
|
|
|
683 |
|
|
assign wrcal_resume_w = (WRLVL == "ON") ? wrcal_pat_resume : 1'b0;
|
684 |
|
|
assign wrlvl_done_w = (WRLVL == "ON") ? wrlvl_done : 1'b1;
|
685 |
|
|
assign ck_addr_cmd_delay_done = (WRLVL == "ON") ? po_ck_addr_cmd_delay_done :
|
686 |
|
|
(po_ck_addr_cmd_delay_done
|
687 |
|
|
&& pi_fine_dly_dec_done) ;
|
688 |
|
|
|
689 |
|
|
generate
|
690 |
|
|
if((WRLVL == "ON") && (BYPASS_COMPLEX_OCAL=="FALSE")) begin: complex_oclk_calib
|
691 |
|
|
assign complex_oclkdelay_calib_start_w = complex_oclkdelay_calib_start;
|
692 |
|
|
assign complex_oclkdelay_calib_done_w = complex_oclkdelay_calib_done;
|
693 |
|
|
assign complex_ocal_rd_victim_sel_w = complex_ocal_rd_victim_sel;
|
694 |
|
|
assign complex_wrlvl_final_w = complex_wrlvl_final;
|
695 |
|
|
end else begin: bypass_complex_ocal
|
696 |
|
|
assign complex_oclkdelay_calib_start_w = 1'b0;
|
697 |
|
|
assign complex_oclkdelay_calib_done_w = prbs_rdlvl_done;
|
698 |
|
|
assign complex_ocal_rd_victim_sel_w = 'd0;
|
699 |
|
|
assign complex_wrlvl_final_w = 1'b0;
|
700 |
|
|
end
|
701 |
|
|
endgenerate
|
702 |
|
|
|
703 |
|
|
|
704 |
|
|
generate
|
705 |
|
|
genvar i;
|
706 |
|
|
for (i = 0; i <= 2; i = i+1) begin : bankwise_signal
|
707 |
|
|
|
708 |
|
|
assign po_sel_stg2stg3[i] = ((ck_addr_cmd_delay_done && ~oclkdelay_calib_done && mpr_rdlvl_done) ? po_stg23_sel :
|
709 |
|
|
(complex_oclkdelay_calib_start_w&&~complex_oclkdelay_calib_done_w? po_stg23_sel : 1'b0 )
|
710 |
|
|
// (~oclkdelay_center_calib_done? ocal_ctr_po_stg23_sel:1'b0))
|
711 |
|
|
) | dbg_po_f_stg23_sel_r;
|
712 |
|
|
|
713 |
|
|
assign po_stg2_c_incdec[i] = cmd_po_stg2_c_incdec ||
|
714 |
|
|
cmd_po_stg2_incdec_ddr2_c ||
|
715 |
|
|
dqs_wl_po_stg2_c_incdec;
|
716 |
|
|
|
717 |
|
|
assign po_en_stg2_c[i] = cmd_po_en_stg2_c ||
|
718 |
|
|
cmd_po_en_stg2_ddr2_c ||
|
719 |
|
|
dqs_wl_po_en_stg2_c;
|
720 |
|
|
|
721 |
|
|
assign po_stg2_f_incdec[i] = dqs_po_stg2_f_incdec ||
|
722 |
|
|
cmd_po_stg2_f_incdec ||
|
723 |
|
|
//po_stg3_incdec ||
|
724 |
|
|
ck_po_stg2_f_indec ||
|
725 |
|
|
po_stg23_incdec ||
|
726 |
|
|
// complex_po_stg23_incdec ||
|
727 |
|
|
// ocal_ctr_po_stg23_incdec ||
|
728 |
|
|
dbg_po_f_inc_r;
|
729 |
|
|
|
730 |
|
|
assign po_en_stg2_f[i] = dqs_po_en_stg2_f ||
|
731 |
|
|
cmd_po_en_stg2_f ||
|
732 |
|
|
//po_en_stg3 ||
|
733 |
|
|
ck_po_stg2_f_en ||
|
734 |
|
|
po_en_stg23 ||
|
735 |
|
|
// complex_po_en_stg23 ||
|
736 |
|
|
// ocal_ctr_po_en_stg23 ||
|
737 |
|
|
dbg_po_f_en_r;
|
738 |
|
|
|
739 |
|
|
end
|
740 |
|
|
endgenerate
|
741 |
|
|
|
742 |
|
|
assign pi_stg2_f_incdec = (dbg_pi_f_inc_r | rdlvl_pi_stg2_f_incdec | prbs_pi_stg2_f_incdec | tempmon_pi_f_inc_r);
|
743 |
|
|
assign pi_en_stg2_f = (dbg_pi_f_en_r | rdlvl_pi_stg2_f_en | prbs_pi_stg2_f_en | tempmon_pi_f_en_r);
|
744 |
|
|
|
745 |
|
|
assign idelay_ce = idelay_ce_r2;
|
746 |
|
|
assign idelay_inc = idelay_inc_r2;
|
747 |
|
|
|
748 |
|
|
assign po_counter_load_en = 1'b0;
|
749 |
|
|
|
750 |
|
|
assign complex_oclkdelay_calib_cnt = oclkdelay_calib_cnt;
|
751 |
|
|
assign complex_oclk_calib_resume = oclk_calib_resume;
|
752 |
|
|
assign complex_ocal_ref_req = oclk_prech_req;
|
753 |
|
|
|
754 |
|
|
|
755 |
|
|
// Added single stage flop to meet timing
|
756 |
|
|
always @(posedge clk)
|
757 |
|
|
init_calib_complete <= calib_complete;
|
758 |
|
|
|
759 |
|
|
assign calib_rd_data_offset_0 = rd_data_offset_ranks_mc_0;
|
760 |
|
|
assign calib_rd_data_offset_1 = rd_data_offset_ranks_mc_1;
|
761 |
|
|
assign calib_rd_data_offset_2 = rd_data_offset_ranks_mc_2;
|
762 |
|
|
|
763 |
|
|
//***************************************************************************
|
764 |
|
|
// Hard PHY signals
|
765 |
|
|
//***************************************************************************
|
766 |
|
|
|
767 |
|
|
assign pi_phase_locked_err = phase_locked_err;
|
768 |
|
|
assign pi_dqsfound_err = pi_dqs_found_err;
|
769 |
|
|
assign wrcal_err = wrcal_pat_err;
|
770 |
|
|
assign rst_tg_mc = 1'b0;
|
771 |
|
|
|
772 |
|
|
//Restart WRLVL after oclkdealy cal
|
773 |
|
|
always @ (posedge clk)
|
774 |
|
|
wrlvl_final_mux <= #TCQ complex_oclkdelay_calib_start_w? complex_wrlvl_final_w: wrlvl_final;
|
775 |
|
|
|
776 |
|
|
|
777 |
|
|
always @(posedge clk)
|
778 |
|
|
phy_if_reset <= #TCQ (phy_if_reset_w | mpr_end_if_reset |
|
779 |
|
|
reset_if | wrlvl_final_if_rst);
|
780 |
|
|
|
781 |
|
|
//***************************************************************************
|
782 |
|
|
// Phaser_IN inc dec control for debug
|
783 |
|
|
//***************************************************************************
|
784 |
|
|
|
785 |
|
|
always @(posedge clk) begin
|
786 |
|
|
if (rst) begin
|
787 |
|
|
dbg_pi_f_inc_r <= #TCQ 1'b0;
|
788 |
|
|
dbg_pi_f_en_r <= #TCQ 1'b0;
|
789 |
|
|
dbg_sel_pi_incdec_r <= #TCQ 1'b0;
|
790 |
|
|
end else begin
|
791 |
|
|
dbg_pi_f_inc_r <= #TCQ dbg_pi_f_inc;
|
792 |
|
|
dbg_pi_f_en_r <= #TCQ (dbg_pi_f_inc | dbg_pi_f_dec);
|
793 |
|
|
dbg_sel_pi_incdec_r <= #TCQ dbg_sel_pi_incdec;
|
794 |
|
|
end
|
795 |
|
|
end
|
796 |
|
|
|
797 |
|
|
//***************************************************************************
|
798 |
|
|
// Phaser_OUT inc dec control for debug
|
799 |
|
|
//***************************************************************************
|
800 |
|
|
|
801 |
|
|
always @(posedge clk) begin
|
802 |
|
|
if (rst) begin
|
803 |
|
|
dbg_po_f_inc_r <= #TCQ 1'b0;
|
804 |
|
|
dbg_po_f_stg23_sel_r<= #TCQ 1'b0;
|
805 |
|
|
dbg_po_f_en_r <= #TCQ 1'b0;
|
806 |
|
|
dbg_sel_po_incdec_r <= #TCQ 1'b0;
|
807 |
|
|
end else begin
|
808 |
|
|
dbg_po_f_inc_r <= #TCQ dbg_po_f_inc;
|
809 |
|
|
dbg_po_f_stg23_sel_r<= #TCQ dbg_po_f_stg23_sel;
|
810 |
|
|
dbg_po_f_en_r <= #TCQ (dbg_po_f_inc | dbg_po_f_dec);
|
811 |
|
|
dbg_sel_po_incdec_r <= #TCQ dbg_sel_po_incdec;
|
812 |
|
|
end
|
813 |
|
|
end
|
814 |
|
|
|
815 |
|
|
//***************************************************************************
|
816 |
|
|
// Phaser_IN inc dec control for temperature tracking
|
817 |
|
|
//***************************************************************************
|
818 |
|
|
|
819 |
|
|
always @(posedge clk) begin
|
820 |
|
|
if (rst) begin
|
821 |
|
|
tempmon_pi_f_inc_r <= #TCQ 1'b0;
|
822 |
|
|
tempmon_pi_f_en_r <= #TCQ 1'b0;
|
823 |
|
|
tempmon_sel_pi_incdec_r <= #TCQ 1'b0;
|
824 |
|
|
end else begin
|
825 |
|
|
tempmon_pi_f_inc_r <= #TCQ tempmon_pi_f_inc;
|
826 |
|
|
tempmon_pi_f_en_r <= #TCQ (tempmon_pi_f_inc | tempmon_pi_f_dec);
|
827 |
|
|
tempmon_sel_pi_incdec_r <= #TCQ tempmon_sel_pi_incdec;
|
828 |
|
|
end
|
829 |
|
|
end
|
830 |
|
|
|
831 |
|
|
//***************************************************************************
|
832 |
|
|
// OCLKDELAY calibration signals
|
833 |
|
|
//***************************************************************************
|
834 |
|
|
|
835 |
|
|
// Minimum of 5 'clk' cycles required between assertion of po_sel_stg2stg3
|
836 |
|
|
// and increment/decrement of Phaser_Out stage 3 delay
|
837 |
|
|
always @(posedge clk) begin
|
838 |
|
|
ck_addr_cmd_delay_done_r1 <= #TCQ ck_addr_cmd_delay_done;
|
839 |
|
|
ck_addr_cmd_delay_done_r2 <= #TCQ ck_addr_cmd_delay_done_r1;
|
840 |
|
|
ck_addr_cmd_delay_done_r3 <= #TCQ ck_addr_cmd_delay_done_r2;
|
841 |
|
|
ck_addr_cmd_delay_done_r4 <= #TCQ ck_addr_cmd_delay_done_r3;
|
842 |
|
|
ck_addr_cmd_delay_done_r5 <= #TCQ ck_addr_cmd_delay_done_r4;
|
843 |
|
|
ck_addr_cmd_delay_done_r6 <= #TCQ ck_addr_cmd_delay_done_r5;
|
844 |
|
|
end
|
845 |
|
|
|
846 |
|
|
|
847 |
|
|
|
848 |
|
|
|
849 |
|
|
//***************************************************************************
|
850 |
|
|
// MUX select logic to select current byte undergoing calibration
|
851 |
|
|
// Use DQS_CAL_MAP to determine the correlation between the physical
|
852 |
|
|
// byte numbering, and the byte numbering within the hard PHY
|
853 |
|
|
//***************************************************************************
|
854 |
|
|
generate
|
855 |
|
|
if (tCK > 2500) begin: gen_byte_sel_div2
|
856 |
|
|
|
857 |
|
|
always @(posedge clk) begin
|
858 |
|
|
if (rst) begin
|
859 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
860 |
|
|
ctl_lane_sel <= #TCQ 'd0;
|
861 |
|
|
calib_in_common <= #TCQ 1'b0;
|
862 |
|
|
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
|
863 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
864 |
|
|
calib_in_common <= #TCQ 1'b1;
|
865 |
|
|
end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin
|
866 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
867 |
|
|
ctl_lane_sel <= #TCQ 'd0;
|
868 |
|
|
calib_in_common <= #TCQ 1'b1;
|
869 |
|
|
end else if (~ck_addr_cmd_delay_done) begin
|
870 |
|
|
ctl_lane_sel <= #TCQ ctl_lane_cnt;
|
871 |
|
|
calib_in_common <= #TCQ 1'b0;
|
872 |
|
|
end else if (~fine_adjust_done && rd_data_offset_cal_done) begin
|
873 |
|
|
if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin
|
874 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
875 |
|
|
ctl_lane_sel <= #TCQ 'd0;
|
876 |
|
|
calib_in_common <= #TCQ 1'b1;
|
877 |
|
|
end else begin
|
878 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
879 |
|
|
ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;
|
880 |
|
|
calib_in_common <= #TCQ 1'b0;
|
881 |
|
|
end
|
882 |
|
|
end else if (~pi_calib_done) begin
|
883 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
884 |
|
|
calib_in_common <= #TCQ 1'b1;
|
885 |
|
|
end else if (~pi_dqs_found_done) begin
|
886 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
887 |
|
|
calib_in_common <= #TCQ 1'b1;
|
888 |
|
|
end else if (~wrlvl_done_w) begin
|
889 |
|
|
if (SIM_CAL_OPTION != "FAST_CAL") begin
|
890 |
|
|
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
|
891 |
|
|
calib_in_common <= #TCQ 1'b0;
|
892 |
|
|
end else begin
|
893 |
|
|
// Special case for FAST_CAL simulation only to ensure that
|
894 |
|
|
// calib_in_common isn't asserted too soon
|
895 |
|
|
if (!phy_ctl_rdy_dly) begin
|
896 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
897 |
|
|
calib_in_common <= #TCQ 1'b0;
|
898 |
|
|
end else begin
|
899 |
|
|
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
|
900 |
|
|
calib_in_common <= #TCQ 1'b1;
|
901 |
|
|
end
|
902 |
|
|
end
|
903 |
|
|
end else if (~mpr_rdlvl_done) begin
|
904 |
|
|
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
|
905 |
|
|
calib_in_common <= #TCQ 1'b0;
|
906 |
|
|
end else if (~oclkdelay_calib_done) begin
|
907 |
|
|
byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;
|
908 |
|
|
calib_in_common <= #TCQ 1'b0;
|
909 |
|
|
end else if (~rdlvl_stg1_done && pi_calib_done) begin
|
910 |
|
|
if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin
|
911 |
|
|
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
|
912 |
|
|
calib_in_common <= #TCQ 1'b1;
|
913 |
|
|
end else begin
|
914 |
|
|
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
|
915 |
|
|
calib_in_common <= #TCQ 1'b0;
|
916 |
|
|
end
|
917 |
|
|
end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin
|
918 |
|
|
byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;
|
919 |
|
|
calib_in_common <= #TCQ 1'b0;
|
920 |
|
|
end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin
|
921 |
|
|
byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt;
|
922 |
|
|
calib_in_common <= #TCQ 1'b0;
|
923 |
|
|
end else if (~wrcal_done) begin
|
924 |
|
|
byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;
|
925 |
|
|
calib_in_common <= #TCQ 1'b0;
|
926 |
|
|
end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin
|
927 |
|
|
byte_sel_cnt <= #TCQ dbg_byte_sel;
|
928 |
|
|
calib_in_common <= #TCQ 1'b0;
|
929 |
|
|
end else if (tempmon_sel_pi_incdec) begin
|
930 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
931 |
|
|
calib_in_common <= #TCQ 1'b1;
|
932 |
|
|
end
|
933 |
|
|
end
|
934 |
|
|
end else begin: gen_byte_sel_div1
|
935 |
|
|
|
936 |
|
|
always @(posedge clk) begin
|
937 |
|
|
if (rst) begin
|
938 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
939 |
|
|
ctl_lane_sel <= #TCQ 'd0;
|
940 |
|
|
calib_in_common <= #TCQ 1'b0;
|
941 |
|
|
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
|
942 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
943 |
|
|
calib_in_common <= #TCQ 1'b1;
|
944 |
|
|
end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin
|
945 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
946 |
|
|
ctl_lane_sel <= #TCQ 'd0;
|
947 |
|
|
calib_in_common <= #TCQ 1'b1;
|
948 |
|
|
end else if (~ck_addr_cmd_delay_done) begin
|
949 |
|
|
ctl_lane_sel <= #TCQ ctl_lane_cnt;
|
950 |
|
|
calib_in_common <= #TCQ 1'b0;
|
951 |
|
|
end else if (~fine_adjust_done && rd_data_offset_cal_done) begin
|
952 |
|
|
if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin
|
953 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
954 |
|
|
ctl_lane_sel <= #TCQ 'd0;
|
955 |
|
|
calib_in_common <= #TCQ 1'b1;
|
956 |
|
|
end else begin
|
957 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
958 |
|
|
ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;
|
959 |
|
|
calib_in_common <= #TCQ 1'b0;
|
960 |
|
|
end
|
961 |
|
|
end else if (~pi_calib_done) begin
|
962 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
963 |
|
|
calib_in_common <= #TCQ 1'b1;
|
964 |
|
|
end else if (~pi_dqs_found_done) begin
|
965 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
966 |
|
|
calib_in_common <= #TCQ 1'b1;
|
967 |
|
|
end else if (~wrlvl_done_w) begin
|
968 |
|
|
if (SIM_CAL_OPTION != "FAST_CAL") begin
|
969 |
|
|
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
|
970 |
|
|
calib_in_common <= #TCQ 1'b0;
|
971 |
|
|
end else begin
|
972 |
|
|
// Special case for FAST_CAL simulation only to ensure that
|
973 |
|
|
// calib_in_common isn't asserted too soon
|
974 |
|
|
if (!phy_ctl_rdy_dly) begin
|
975 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
976 |
|
|
calib_in_common <= #TCQ 1'b0;
|
977 |
|
|
end else begin
|
978 |
|
|
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
|
979 |
|
|
calib_in_common <= #TCQ 1'b1;
|
980 |
|
|
end
|
981 |
|
|
end
|
982 |
|
|
end else if (~mpr_rdlvl_done) begin
|
983 |
|
|
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
|
984 |
|
|
calib_in_common <= #TCQ 1'b0;
|
985 |
|
|
end else if (~oclkdelay_calib_done) begin
|
986 |
|
|
byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;
|
987 |
|
|
calib_in_common <= #TCQ 1'b0;
|
988 |
|
|
end else if ((~wrcal_done)&& (DRAM_TYPE == "DDR3")) begin
|
989 |
|
|
byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;
|
990 |
|
|
calib_in_common <= #TCQ 1'b0;
|
991 |
|
|
end else if (~rdlvl_stg1_done && pi_calib_done) begin
|
992 |
|
|
if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin
|
993 |
|
|
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
|
994 |
|
|
calib_in_common <= #TCQ 1'b1;
|
995 |
|
|
end else begin
|
996 |
|
|
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
|
997 |
|
|
calib_in_common <= #TCQ 1'b0;
|
998 |
|
|
end
|
999 |
|
|
end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin
|
1000 |
|
|
byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;
|
1001 |
|
|
calib_in_common <= #TCQ 1'b0;
|
1002 |
|
|
end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin
|
1003 |
|
|
byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt;
|
1004 |
|
|
calib_in_common <= #TCQ 1'b0;
|
1005 |
|
|
end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin
|
1006 |
|
|
byte_sel_cnt <= #TCQ dbg_byte_sel;
|
1007 |
|
|
calib_in_common <= #TCQ 1'b0;
|
1008 |
|
|
end else if (tempmon_sel_pi_incdec) begin
|
1009 |
|
|
byte_sel_cnt <= #TCQ 'd0;
|
1010 |
|
|
calib_in_common <= #TCQ 1'b1;
|
1011 |
|
|
end
|
1012 |
|
|
end
|
1013 |
|
|
|
1014 |
|
|
end
|
1015 |
|
|
endgenerate
|
1016 |
|
|
|
1017 |
|
|
// verilint STARC-2.2.3.3 off
|
1018 |
|
|
always @(posedge clk) begin
|
1019 |
|
|
if (rst || (calib_complete && ~ (dbg_sel_pi_incdec_r|dbg_sel_po_incdec_r|tempmon_sel_pi_incdec) )) begin
|
1020 |
|
|
calib_sel <= #TCQ 6'b000100;
|
1021 |
|
|
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
|
1022 |
|
|
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
|
1023 |
|
|
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
|
1024 |
|
|
calib_sel[2] <= #TCQ 1'b0;
|
1025 |
|
|
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
|
1026 |
|
|
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
|
1027 |
|
|
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
|
1028 |
|
|
if (~dqs_po_dec_done && (WRLVL != "ON"))
|
1029 |
|
|
//if (~dqs_po_dec_done && ((SIM_CAL_OPTION == "FAST_CAL") ||(WRLVL != "ON")))
|
1030 |
|
|
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};
|
1031 |
|
|
else
|
1032 |
|
|
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
|
1033 |
|
|
end else if (~ck_addr_cmd_delay_done || (~fine_adjust_done && rd_data_offset_cal_done)) begin
|
1034 |
|
|
if(WRLVL =="ON") begin
|
1035 |
|
|
calib_sel[2] <= #TCQ 1'b0;
|
1036 |
|
|
calib_sel[1:0] <= #TCQ CTL_BYTE_LANE[(ctl_lane_sel*2)+:2];
|
1037 |
|
|
calib_sel[5:3] <= #TCQ CTL_BANK;
|
1038 |
|
|
if (|pi_rst_stg1_cal) begin
|
1039 |
|
|
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
|
1040 |
|
|
end else begin
|
1041 |
|
|
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
|
1042 |
|
|
calib_zero_inputs[1*CTL_BANK] <= #TCQ 1'b0;
|
1043 |
|
|
end
|
1044 |
|
|
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
|
1045 |
|
|
end else begin // if (WRLVL =="ON")
|
1046 |
|
|
calib_sel[2] <= #TCQ 1'b0;
|
1047 |
|
|
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
|
1048 |
|
|
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
|
1049 |
|
|
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
|
1050 |
|
|
if(~ck_addr_cmd_delay_done)
|
1051 |
|
|
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
|
1052 |
|
|
else
|
1053 |
|
|
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};
|
1054 |
|
|
end // else: !if(WRLVL =="ON")
|
1055 |
|
|
end else if ((~wrlvl_done_w) && (SIM_CAL_OPTION == "FAST_CAL")) begin
|
1056 |
|
|
calib_sel[2] <= #TCQ 1'b0;
|
1057 |
|
|
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
|
1058 |
|
|
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
|
1059 |
|
|
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
|
1060 |
|
|
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
|
1061 |
|
|
end else if (~rdlvl_stg1_done && (SIM_CAL_OPTION == "FAST_CAL") &&
|
1062 |
|
|
rdlvl_assrt_common) begin
|
1063 |
|
|
calib_sel[2] <= #TCQ 1'b0;
|
1064 |
|
|
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
|
1065 |
|
|
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
|
1066 |
|
|
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
|
1067 |
|
|
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
|
1068 |
|
|
end else if (tempmon_sel_pi_incdec) begin
|
1069 |
|
|
calib_sel[2] <= #TCQ 1'b0;
|
1070 |
|
|
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
|
1071 |
|
|
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
|
1072 |
|
|
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
|
1073 |
|
|
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
|
1074 |
|
|
end else begin
|
1075 |
|
|
calib_sel[2] <= #TCQ 1'b0;
|
1076 |
|
|
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
|
1077 |
|
|
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
|
1078 |
|
|
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
|
1079 |
|
|
if (~calib_in_common) begin
|
1080 |
|
|
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
|
1081 |
|
|
calib_zero_inputs[(1*DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3])] <= #TCQ 1'b0;
|
1082 |
|
|
end else
|
1083 |
|
|
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
|
1084 |
|
|
end
|
1085 |
|
|
end
|
1086 |
|
|
// verilint STARC-2.2.3.3 on
|
1087 |
|
|
// Logic to reset IN_FIFO flags to account for the possibility that
|
1088 |
|
|
// one or more PHASER_IN's have not correctly found the DQS preamble
|
1089 |
|
|
// If this happens, we can still complete read leveling, but the # of
|
1090 |
|
|
// words written into the IN_FIFO's may be an odd #, so that if the
|
1091 |
|
|
// IN_FIFO is used in 2:1 mode ("8:4 mode"), there may be a "half" word
|
1092 |
|
|
// of data left that can only be flushed out by reseting the IN_FIFO
|
1093 |
|
|
always @(posedge clk) begin
|
1094 |
|
|
rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done;
|
1095 |
|
|
prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done;
|
1096 |
|
|
reset_if_r1 <= #TCQ reset_if;
|
1097 |
|
|
reset_if_r2 <= #TCQ reset_if_r1;
|
1098 |
|
|
reset_if_r3 <= #TCQ reset_if_r2;
|
1099 |
|
|
reset_if_r4 <= #TCQ reset_if_r3;
|
1100 |
|
|
reset_if_r5 <= #TCQ reset_if_r4;
|
1101 |
|
|
reset_if_r6 <= #TCQ reset_if_r5;
|
1102 |
|
|
reset_if_r7 <= #TCQ reset_if_r6;
|
1103 |
|
|
reset_if_r8 <= #TCQ reset_if_r7;
|
1104 |
|
|
reset_if_r9 <= #TCQ reset_if_r8;
|
1105 |
|
|
end
|
1106 |
|
|
|
1107 |
|
|
always @(posedge clk) begin
|
1108 |
|
|
if (rst || reset_if_r9)
|
1109 |
|
|
reset_if <= #TCQ 1'b0;
|
1110 |
|
|
else if ((rdlvl_stg1_done && ~rdlvl_stg1_done_r1) ||
|
1111 |
|
|
(prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
|
1112 |
|
|
reset_if <= #TCQ 1'b1;
|
1113 |
|
|
end
|
1114 |
|
|
|
1115 |
|
|
assign phy_if_empty_def = 1'b0;
|
1116 |
|
|
|
1117 |
|
|
// DQ IDELAY tap inc and ce signals registered to control calib_in_common
|
1118 |
|
|
// signal during read leveling in FAST_CAL mode. The calib_in_common signal
|
1119 |
|
|
// is only asserted for IDELAY tap increments not Phaser_IN tap increments
|
1120 |
|
|
// in FAST_CAL mode. For Phaser_IN tap increments the Phaser_IN counter load
|
1121 |
|
|
// inputs are used.
|
1122 |
|
|
always @(posedge clk) begin
|
1123 |
|
|
if (rst) begin
|
1124 |
|
|
idelay_ce_r1 <= #TCQ 1'b0;
|
1125 |
|
|
idelay_ce_r2 <= #TCQ 1'b0;
|
1126 |
|
|
idelay_inc_r1 <= #TCQ 1'b0;
|
1127 |
|
|
idelay_inc_r2 <= #TCQ 1'b0;
|
1128 |
|
|
end else begin
|
1129 |
|
|
idelay_ce_r1 <= #TCQ idelay_ce_int;
|
1130 |
|
|
idelay_ce_r2 <= #TCQ idelay_ce_r1;
|
1131 |
|
|
idelay_inc_r1 <= #TCQ idelay_inc_int;
|
1132 |
|
|
idelay_inc_r2 <= #TCQ idelay_inc_r1;
|
1133 |
|
|
end
|
1134 |
|
|
end
|
1135 |
|
|
|
1136 |
|
|
//***************************************************************************
|
1137 |
|
|
// Delay all Outputs using Phaser_Out fine taps
|
1138 |
|
|
//***************************************************************************
|
1139 |
|
|
|
1140 |
|
|
assign init_wrcal_complete = 1'b0;
|
1141 |
|
|
|
1142 |
|
|
//***************************************************************************
|
1143 |
|
|
// PRBS Generator for Read Leveling Stage 1 - read window detection and
|
1144 |
|
|
// DQS Centering
|
1145 |
|
|
//***************************************************************************
|
1146 |
|
|
|
1147 |
|
|
// Assign initial seed (used for 1st data word in 8-burst sequence); use alternating 1/0 pat
|
1148 |
|
|
assign prbs_seed = 64'h9966aa559966aa55;
|
1149 |
|
|
|
1150 |
|
|
// A single PRBS generator
|
1151 |
|
|
// writes 64-bits every 4to1 fabric clock cycle and
|
1152 |
|
|
// write 32-bits every 2to1 fabric clock cycle
|
1153 |
|
|
// used for complex read leveling and complex oclkdealy calib
|
1154 |
|
|
mig_7series_v2_3_ddr_prbs_gen #
|
1155 |
|
|
(
|
1156 |
|
|
.TCQ (TCQ),
|
1157 |
|
|
.PRBS_WIDTH (2*8*nCK_PER_CLK),
|
1158 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
1159 |
|
|
.DQ_WIDTH (DQ_WIDTH),
|
1160 |
|
|
.VCCO_PAT_EN (VCCO_PAT_EN),
|
1161 |
|
|
.VCCAUX_PAT_EN (VCCAUX_PAT_EN),
|
1162 |
|
|
.ISI_PAT_EN (ISI_PAT_EN),
|
1163 |
|
|
.FIXED_VICTIM (FIXED_VICTIM)
|
1164 |
|
|
)
|
1165 |
|
|
u_ddr_prbs_gen
|
1166 |
|
|
(.prbs_ignore_first_byte (prbs_ignore_first_byte),
|
1167 |
|
|
.prbs_ignore_last_bytes (prbs_ignore_last_bytes),
|
1168 |
|
|
.clk_i (clk),
|
1169 |
|
|
.clk_en_i (prbs_gen_clk_en | prbs_gen_oclk_clk_en),
|
1170 |
|
|
.rst_i (rst),
|
1171 |
|
|
.prbs_o (prbs_out),
|
1172 |
|
|
.prbs_seed_i (prbs_seed),
|
1173 |
|
|
.phy_if_empty (phy_if_empty),
|
1174 |
|
|
.prbs_rdlvl_start (prbs_rdlvl_start),
|
1175 |
|
|
.prbs_rdlvl_done (prbs_rdlvl_done),
|
1176 |
|
|
.complex_wr_done (complex_wr_done),
|
1177 |
|
|
.victim_sel (victim_sel),
|
1178 |
|
|
.byte_cnt (victim_byte_cnt),
|
1179 |
|
|
.dbg_prbs_gen (),
|
1180 |
|
|
.reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr)
|
1181 |
|
|
);
|
1182 |
|
|
|
1183 |
|
|
|
1184 |
|
|
// PRBS data slice that decides the Rise0, Fall0, Rise1, Fall1,
|
1185 |
|
|
// Rise2, Fall2, Rise3, Fall3 data
|
1186 |
|
|
generate
|
1187 |
|
|
if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4
|
1188 |
|
|
assign prbs_o = prbs_out;
|
1189 |
|
|
/*assign prbs_rise0 = prbs_out[7:0];
|
1190 |
|
|
assign prbs_fall0 = prbs_out[15:8];
|
1191 |
|
|
assign prbs_rise1 = prbs_out[23:16];
|
1192 |
|
|
assign prbs_fall1 = prbs_out[31:24];
|
1193 |
|
|
assign prbs_rise2 = prbs_out[39:32];
|
1194 |
|
|
assign prbs_fall2 = prbs_out[47:40];
|
1195 |
|
|
assign prbs_rise3 = prbs_out[55:48];
|
1196 |
|
|
assign prbs_fall3 = prbs_out[63:56];
|
1197 |
|
|
assign prbs_o = {prbs_fall3, prbs_rise3, prbs_fall2, prbs_rise2,
|
1198 |
|
|
prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/
|
1199 |
|
|
end else begin :gen_ck_per_clk2
|
1200 |
|
|
assign prbs_o = prbs_out[4*DQ_WIDTH-1:0];
|
1201 |
|
|
/*assign prbs_rise0 = prbs_out[7:0];
|
1202 |
|
|
assign prbs_fall0 = prbs_out[15:8];
|
1203 |
|
|
assign prbs_rise1 = prbs_out[23:16];
|
1204 |
|
|
assign prbs_fall1 = prbs_out[31:24];
|
1205 |
|
|
assign prbs_o = {prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/
|
1206 |
|
|
end
|
1207 |
|
|
endgenerate
|
1208 |
|
|
|
1209 |
|
|
|
1210 |
|
|
//***************************************************************************
|
1211 |
|
|
// Initialization / Master PHY state logic (overall control during memory
|
1212 |
|
|
// init, timing leveling)
|
1213 |
|
|
//***************************************************************************
|
1214 |
|
|
|
1215 |
|
|
mig_7series_v2_3_ddr_phy_init #
|
1216 |
|
|
(
|
1217 |
|
|
.tCK (tCK),
|
1218 |
|
|
.DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
|
1219 |
|
|
.TCQ (TCQ),
|
1220 |
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
1221 |
|
|
.CLK_PERIOD (CLK_PERIOD),
|
1222 |
|
|
.DRAM_TYPE (DRAM_TYPE),
|
1223 |
|
|
.PRBS_WIDTH (PRBS_WIDTH),
|
1224 |
|
|
.BANK_WIDTH (BANK_WIDTH),
|
1225 |
|
|
.CA_MIRROR (CA_MIRROR),
|
1226 |
|
|
.COL_WIDTH (COL_WIDTH),
|
1227 |
|
|
.nCS_PER_RANK (nCS_PER_RANK),
|
1228 |
|
|
.DQ_WIDTH (DQ_WIDTH),
|
1229 |
|
|
.DQS_WIDTH (DQS_WIDTH),
|
1230 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
1231 |
|
|
.ROW_WIDTH (ROW_WIDTH),
|
1232 |
|
|
.CS_WIDTH (CS_WIDTH),
|
1233 |
|
|
.RANKS (RANKS),
|
1234 |
|
|
.CKE_WIDTH (CKE_WIDTH),
|
1235 |
|
|
.CALIB_ROW_ADD (CALIB_ROW_ADD),
|
1236 |
|
|
.CALIB_COL_ADD (CALIB_COL_ADD),
|
1237 |
|
|
.CALIB_BA_ADD (CALIB_BA_ADD),
|
1238 |
|
|
.AL (AL),
|
1239 |
|
|
.BURST_MODE (BURST_MODE),
|
1240 |
|
|
.BURST_TYPE (BURST_TYPE),
|
1241 |
|
|
.nCL (nCL),
|
1242 |
|
|
.nCWL (nCWL),
|
1243 |
|
|
.tRFC (tRFC),
|
1244 |
|
|
.REFRESH_TIMER (REFRESH_TIMER),
|
1245 |
|
|
.REFRESH_TIMER_WIDTH (REFRESH_TIMER_WIDTH),
|
1246 |
|
|
.OUTPUT_DRV (OUTPUT_DRV),
|
1247 |
|
|
.REG_CTRL (REG_CTRL),
|
1248 |
|
|
.ADDR_CMD_MODE (ADDR_CMD_MODE),
|
1249 |
|
|
.RTT_NOM (RTT_NOM),
|
1250 |
|
|
.RTT_WR (RTT_WR),
|
1251 |
|
|
.WRLVL (WRLVL),
|
1252 |
|
|
.USE_ODT_PORT (USE_ODT_PORT),
|
1253 |
|
|
.DDR2_DQSN_ENABLE(DDR2_DQSN_ENABLE),
|
1254 |
|
|
.nSLOTS (nSLOTS),
|
1255 |
|
|
.SIM_INIT_OPTION (SIM_INIT_OPTION),
|
1256 |
|
|
.SIM_CAL_OPTION (SIM_CAL_OPTION),
|
1257 |
|
|
.CKE_ODT_AUX (CKE_ODT_AUX),
|
1258 |
|
|
.PRE_REV3ES (PRE_REV3ES),
|
1259 |
|
|
.TEST_AL (TEST_AL),
|
1260 |
|
|
.FIXED_VICTIM (FIXED_VICTIM),
|
1261 |
|
|
.BYPASS_COMPLEX_OCAL(BYPASS_COMPLEX_OCAL)
|
1262 |
|
|
)
|
1263 |
|
|
u_ddr_phy_init
|
1264 |
|
|
(
|
1265 |
|
|
.clk (clk),
|
1266 |
|
|
.rst (rst),
|
1267 |
|
|
.prbs_o (prbs_o),
|
1268 |
|
|
.ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),
|
1269 |
|
|
.delay_incdec_done (ck_addr_cmd_delay_done),
|
1270 |
|
|
.pi_phase_locked_all (pi_phase_locked_all),
|
1271 |
|
|
.pi_phaselock_start (pi_phaselock_start),
|
1272 |
|
|
.pi_phase_locked_err (phase_locked_err),
|
1273 |
|
|
.pi_calib_done (pi_calib_done),
|
1274 |
|
|
.phy_if_empty (phy_if_empty),
|
1275 |
|
|
.phy_ctl_ready (phy_ctl_ready),
|
1276 |
|
|
.phy_ctl_full (phy_ctl_full),
|
1277 |
|
|
.phy_cmd_full (phy_cmd_full),
|
1278 |
|
|
.phy_data_full (phy_data_full),
|
1279 |
|
|
.calib_ctl_wren (calib_ctl_wren),
|
1280 |
|
|
.calib_cmd_wren (calib_cmd_wren),
|
1281 |
|
|
.calib_wrdata_en (calib_wrdata_en),
|
1282 |
|
|
.calib_seq (calib_seq),
|
1283 |
|
|
.calib_aux_out (calib_aux_out),
|
1284 |
|
|
.calib_rank_cnt (calib_rank_cnt),
|
1285 |
|
|
.calib_cas_slot (calib_cas_slot),
|
1286 |
|
|
.calib_data_offset_0 (calib_data_offset_0),
|
1287 |
|
|
.calib_data_offset_1 (calib_data_offset_1),
|
1288 |
|
|
.calib_data_offset_2 (calib_data_offset_2),
|
1289 |
|
|
.calib_cmd (calib_cmd),
|
1290 |
|
|
.calib_cke (calib_cke),
|
1291 |
|
|
.calib_odt (calib_odt),
|
1292 |
|
|
.write_calib (write_calib),
|
1293 |
|
|
.read_calib (read_calib),
|
1294 |
|
|
.wrlvl_done (wrlvl_done),
|
1295 |
|
|
.wrlvl_rank_done (wrlvl_rank_done),
|
1296 |
|
|
.wrlvl_byte_done (wrlvl_byte_done),
|
1297 |
|
|
.wrlvl_byte_redo (wrlvl_byte_redo),
|
1298 |
|
|
.wrlvl_final (wrlvl_final_mux),
|
1299 |
|
|
.wrlvl_final_if_rst (wrlvl_final_if_rst),
|
1300 |
|
|
.oclkdelay_calib_start (oclkdelay_calib_start),
|
1301 |
|
|
.oclkdelay_calib_done (oclkdelay_calib_done),
|
1302 |
|
|
.oclk_prech_req (oclk_prech_req),
|
1303 |
|
|
.oclk_calib_resume (oclk_calib_resume),
|
1304 |
|
|
.lim_wr_req (lim2init_write_request),
|
1305 |
|
|
.lim_done (lim_done),
|
1306 |
|
|
.complex_oclkdelay_calib_start (complex_oclkdelay_calib_start),
|
1307 |
|
|
.complex_oclkdelay_calib_done (complex_oclkdelay_calib_done_w),
|
1308 |
|
|
.complex_oclk_calib_resume (complex_oclk_calib_resume),
|
1309 |
|
|
.complex_oclkdelay_calib_cnt (complex_oclkdelay_calib_cnt),
|
1310 |
|
|
.complex_sample_cnt_inc_ocal (complex_sample_cnt_inc_ocal),
|
1311 |
|
|
.complex_ocal_num_samples_inc (complex_ocal_num_samples_inc),
|
1312 |
|
|
.complex_ocal_num_samples_done_r (complex_ocal_num_samples_done_r),
|
1313 |
|
|
.complex_ocal_reset_rd_addr (complex_ocal_reset_rd_addr),
|
1314 |
|
|
.complex_ocal_ref_req (complex_ocal_ref_req),
|
1315 |
|
|
.complex_ocal_ref_done (complex_ocal_ref_done),
|
1316 |
|
|
.done_dqs_tap_inc (done_dqs_tap_inc),
|
1317 |
|
|
.wl_sm_start (wl_sm_start),
|
1318 |
|
|
.wr_lvl_start (wrlvl_start),
|
1319 |
|
|
.slot_0_present (slot_0_present),
|
1320 |
|
|
.slot_1_present (slot_1_present),
|
1321 |
|
|
.mpr_rdlvl_done (mpr_rdlvl_done),
|
1322 |
|
|
.mpr_rdlvl_start (mpr_rdlvl_start),
|
1323 |
|
|
.mpr_last_byte_done (mpr_last_byte_done),
|
1324 |
|
|
.mpr_rnk_done (mpr_rnk_done),
|
1325 |
|
|
.mpr_end_if_reset (mpr_end_if_reset),
|
1326 |
|
|
.rdlvl_stg1_done (rdlvl_stg1_done),
|
1327 |
|
|
.rdlvl_stg1_rank_done (rdlvl_stg1_rank_done),
|
1328 |
|
|
.rdlvl_stg1_start (rdlvl_stg1_start),
|
1329 |
|
|
.rdlvl_prech_req (rdlvl_prech_req),
|
1330 |
|
|
.rdlvl_last_byte_done (rdlvl_last_byte_done),
|
1331 |
|
|
.prbs_rdlvl_start (prbs_rdlvl_start),
|
1332 |
|
|
.complex_wr_done (complex_wr_done),
|
1333 |
|
|
.prbs_rdlvl_done (prbs_rdlvl_done),
|
1334 |
|
|
.prbs_last_byte_done (prbs_last_byte_done),
|
1335 |
|
|
.prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),
|
1336 |
|
|
.complex_victim_inc (complex_victim_inc),
|
1337 |
|
|
.rd_victim_sel (rd_victim_sel),
|
1338 |
|
|
.complex_ocal_rd_victim_sel (complex_ocal_rd_victim_sel),
|
1339 |
|
|
.pi_stg2_prbs_rdlvl_cnt(pi_stg2_prbs_rdlvl_cnt),
|
1340 |
|
|
.victim_sel (victim_sel),
|
1341 |
|
|
.victim_byte_cnt (victim_byte_cnt),
|
1342 |
|
|
.prbs_gen_clk_en (prbs_gen_clk_en),
|
1343 |
|
|
.prbs_gen_oclk_clk_en (prbs_gen_oclk_clk_en),
|
1344 |
|
|
.complex_sample_cnt_inc(complex_sample_cnt_inc),
|
1345 |
|
|
.pi_dqs_found_start (pi_dqs_found_start),
|
1346 |
|
|
.dqsfound_retry (dqsfound_retry),
|
1347 |
|
|
.dqs_found_prech_req (dqs_found_prech_req),
|
1348 |
|
|
.pi_dqs_found_rank_done(pi_dqs_found_rank_done),
|
1349 |
|
|
.pi_dqs_found_done (pi_dqs_found_done),
|
1350 |
|
|
.detect_pi_found_dqs (detect_pi_found_dqs),
|
1351 |
|
|
.rd_data_offset_0 (rd_data_offset_0),
|
1352 |
|
|
.rd_data_offset_1 (rd_data_offset_1),
|
1353 |
|
|
.rd_data_offset_2 (rd_data_offset_2),
|
1354 |
|
|
.rd_data_offset_ranks_0(rd_data_offset_ranks_0),
|
1355 |
|
|
.rd_data_offset_ranks_1(rd_data_offset_ranks_1),
|
1356 |
|
|
.rd_data_offset_ranks_2(rd_data_offset_ranks_2),
|
1357 |
|
|
.wrcal_start (wrcal_start),
|
1358 |
|
|
.wrcal_rd_wait (wrcal_rd_wait),
|
1359 |
|
|
.wrcal_prech_req (wrcal_prech_req),
|
1360 |
|
|
.wrcal_resume (wrcal_resume_w),
|
1361 |
|
|
.wrcal_read_req (wrcal_read_req),
|
1362 |
|
|
.wrcal_act_req (wrcal_act_req),
|
1363 |
|
|
.wrcal_sanity_chk (wrcal_sanity_chk),
|
1364 |
|
|
.temp_wrcal_done (temp_wrcal_done),
|
1365 |
|
|
.wrcal_sanity_chk_done (wrcal_sanity_chk_done),
|
1366 |
|
|
.tg_timer_done (tg_timer_done),
|
1367 |
|
|
.no_rst_tg_mc (no_rst_tg_mc),
|
1368 |
|
|
.wrcal_done (wrcal_done),
|
1369 |
|
|
.prech_done (prech_done),
|
1370 |
|
|
.calib_writes (calib_writes),
|
1371 |
|
|
.init_calib_complete (calib_complete),
|
1372 |
|
|
.phy_address (phy_address),
|
1373 |
|
|
.phy_bank (phy_bank),
|
1374 |
|
|
.phy_cas_n (phy_cas_n),
|
1375 |
|
|
.phy_cs_n (phy_cs_n),
|
1376 |
|
|
.phy_ras_n (phy_ras_n),
|
1377 |
|
|
.phy_reset_n (phy_reset_n),
|
1378 |
|
|
.phy_we_n (phy_we_n),
|
1379 |
|
|
.phy_wrdata (phy_wrdata),
|
1380 |
|
|
.phy_rddata_en (phy_rddata_en),
|
1381 |
|
|
.phy_rddata_valid (phy_rddata_valid),
|
1382 |
|
|
.dbg_phy_init (dbg_phy_init),
|
1383 |
|
|
.read_pause (read_pause),
|
1384 |
|
|
.reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr),
|
1385 |
|
|
.oclkdelay_center_calib_start (oclkdelay_center_calib_start),
|
1386 |
|
|
.oclk_center_write_resume (oclk_center_write_resume),
|
1387 |
|
|
.oclkdelay_center_calib_done (oclkdelay_center_calib_done)
|
1388 |
|
|
);
|
1389 |
|
|
|
1390 |
|
|
|
1391 |
|
|
//*****************************************************************
|
1392 |
|
|
// Write Calibration
|
1393 |
|
|
//*****************************************************************
|
1394 |
|
|
|
1395 |
|
|
mig_7series_v2_3_ddr_phy_wrcal #
|
1396 |
|
|
(
|
1397 |
|
|
.TCQ (TCQ),
|
1398 |
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
1399 |
|
|
.CLK_PERIOD (CLK_PERIOD),
|
1400 |
|
|
.DQ_WIDTH (DQ_WIDTH),
|
1401 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
1402 |
|
|
.DQS_WIDTH (DQS_WIDTH),
|
1403 |
|
|
.DRAM_WIDTH (DRAM_WIDTH),
|
1404 |
|
|
.SIM_CAL_OPTION (SIM_CAL_OPTION)
|
1405 |
|
|
)
|
1406 |
|
|
u_ddr_phy_wrcal
|
1407 |
|
|
(
|
1408 |
|
|
.clk (clk),
|
1409 |
|
|
.rst (rst),
|
1410 |
|
|
.wrcal_start (wrcal_start),
|
1411 |
|
|
.wrcal_rd_wait (wrcal_rd_wait),
|
1412 |
|
|
.wrcal_sanity_chk (wrcal_sanity_chk),
|
1413 |
|
|
.dqsfound_retry_done (pi_dqs_found_done),
|
1414 |
|
|
.dqsfound_retry (dqsfound_retry),
|
1415 |
|
|
.wrcal_read_req (wrcal_read_req),
|
1416 |
|
|
.wrcal_act_req (wrcal_act_req),
|
1417 |
|
|
.phy_rddata_en (phy_rddata_en),
|
1418 |
|
|
.wrcal_done (wrcal_done),
|
1419 |
|
|
.wrcal_pat_err (wrcal_pat_err),
|
1420 |
|
|
.wrcal_prech_req (wrcal_prech_req),
|
1421 |
|
|
.temp_wrcal_done (temp_wrcal_done),
|
1422 |
|
|
.wrcal_sanity_chk_done (wrcal_sanity_chk_done),
|
1423 |
|
|
.prech_done (prech_done),
|
1424 |
|
|
.rd_data (phy_rddata),
|
1425 |
|
|
.wrcal_pat_resume (wrcal_pat_resume),
|
1426 |
|
|
.po_stg2_wrcal_cnt (po_stg2_wrcal_cnt),
|
1427 |
|
|
.phy_if_reset (phy_if_reset_w),
|
1428 |
|
|
.wl_po_coarse_cnt (wl_po_coarse_cnt),
|
1429 |
|
|
.wl_po_fine_cnt (wl_po_fine_cnt),
|
1430 |
|
|
.wrlvl_byte_redo (wrlvl_byte_redo),
|
1431 |
|
|
.wrlvl_byte_done (wrlvl_byte_done),
|
1432 |
|
|
.early1_data (early1_data),
|
1433 |
|
|
.early2_data (early2_data),
|
1434 |
|
|
.idelay_ld (idelay_ld),
|
1435 |
|
|
.dbg_phy_wrcal (dbg_phy_wrcal),
|
1436 |
|
|
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
|
1437 |
|
|
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt)
|
1438 |
|
|
);
|
1439 |
|
|
|
1440 |
|
|
|
1441 |
|
|
|
1442 |
|
|
//***************************************************************************
|
1443 |
|
|
// Write-leveling calibration logic
|
1444 |
|
|
//***************************************************************************
|
1445 |
|
|
|
1446 |
|
|
generate
|
1447 |
|
|
if (WRLVL == "ON") begin: mb_wrlvl_inst
|
1448 |
|
|
|
1449 |
|
|
mig_7series_v2_3_ddr_phy_wrlvl #
|
1450 |
|
|
(
|
1451 |
|
|
.TCQ (TCQ),
|
1452 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
1453 |
|
|
.DQ_WIDTH (DQ_WIDTH),
|
1454 |
|
|
.DQS_WIDTH (DQS_WIDTH),
|
1455 |
|
|
.DRAM_WIDTH (DRAM_WIDTH),
|
1456 |
|
|
.RANKS (1),
|
1457 |
|
|
.CLK_PERIOD (CLK_PERIOD),
|
1458 |
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
1459 |
|
|
.SIM_CAL_OPTION (SIM_CAL_OPTION)
|
1460 |
|
|
)
|
1461 |
|
|
u_ddr_phy_wrlvl
|
1462 |
|
|
(
|
1463 |
|
|
.clk (clk),
|
1464 |
|
|
.rst (rst),
|
1465 |
|
|
.phy_ctl_ready (phy_ctl_ready),
|
1466 |
|
|
.wr_level_start (wrlvl_start),
|
1467 |
|
|
.wl_sm_start (wl_sm_start),
|
1468 |
|
|
.wrlvl_byte_redo (wrlvl_byte_redo),
|
1469 |
|
|
.wrcal_cnt (po_stg2_wrcal_cnt),
|
1470 |
|
|
.early1_data (early1_data),
|
1471 |
|
|
.early2_data (early2_data),
|
1472 |
|
|
.wrlvl_final (wrlvl_final_mux),
|
1473 |
|
|
.oclkdelay_calib_cnt (oclkdelay_calib_cnt),
|
1474 |
|
|
.wrlvl_byte_done (wrlvl_byte_done),
|
1475 |
|
|
.oclkdelay_calib_done (oclkdelay_calib_done),
|
1476 |
|
|
.rd_data_rise0 (phy_rddata[DQ_WIDTH-1:0]),
|
1477 |
|
|
.dqs_po_dec_done (dqs_po_dec_done),
|
1478 |
|
|
.phy_ctl_rdy_dly (phy_ctl_rdy_dly),
|
1479 |
|
|
.wr_level_done (wrlvl_done),
|
1480 |
|
|
.wrlvl_rank_done (wrlvl_rank_done),
|
1481 |
|
|
.done_dqs_tap_inc (done_dqs_tap_inc),
|
1482 |
|
|
.dqs_po_stg2_f_incdec (dqs_po_stg2_f_incdec),
|
1483 |
|
|
.dqs_po_en_stg2_f (dqs_po_en_stg2_f),
|
1484 |
|
|
.dqs_wl_po_stg2_c_incdec (dqs_wl_po_stg2_c_incdec),
|
1485 |
|
|
.dqs_wl_po_en_stg2_c (dqs_wl_po_en_stg2_c),
|
1486 |
|
|
.po_counter_read_val (po_counter_read_val),
|
1487 |
|
|
.po_stg2_wl_cnt (po_stg2_wl_cnt),
|
1488 |
|
|
.wrlvl_err (wrlvl_err),
|
1489 |
|
|
.wl_po_coarse_cnt (wl_po_coarse_cnt),
|
1490 |
|
|
.wl_po_fine_cnt (wl_po_fine_cnt),
|
1491 |
|
|
.dbg_wl_tap_cnt (dbg_tap_cnt_during_wrlvl),
|
1492 |
|
|
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
|
1493 |
|
|
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
|
1494 |
|
|
.dbg_dqs_count (),
|
1495 |
|
|
.dbg_wl_state (),
|
1496 |
|
|
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
|
1497 |
|
|
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
|
1498 |
|
|
.dbg_phy_wrlvl (dbg_phy_wrlvl)
|
1499 |
|
|
);
|
1500 |
|
|
|
1501 |
|
|
|
1502 |
|
|
mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay #
|
1503 |
|
|
(
|
1504 |
|
|
.TCQ (TCQ),
|
1505 |
|
|
.tCK (tCK),
|
1506 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
1507 |
|
|
.N_CTL_LANES (N_CTL_LANES),
|
1508 |
|
|
.SIM_CAL_OPTION(SIM_CAL_OPTION)
|
1509 |
|
|
)
|
1510 |
|
|
u_ddr_phy_ck_addr_cmd_delay
|
1511 |
|
|
(
|
1512 |
|
|
.clk (clk),
|
1513 |
|
|
.rst (rst),
|
1514 |
|
|
.cmd_delay_start (dqs_po_dec_done & pi_fine_dly_dec_done),
|
1515 |
|
|
.ctl_lane_cnt (ctl_lane_cnt),
|
1516 |
|
|
.po_stg2_f_incdec (cmd_po_stg2_f_incdec),
|
1517 |
|
|
.po_en_stg2_f (cmd_po_en_stg2_f),
|
1518 |
|
|
.po_stg2_c_incdec (cmd_po_stg2_c_incdec),
|
1519 |
|
|
.po_en_stg2_c (cmd_po_en_stg2_c),
|
1520 |
|
|
.po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done)
|
1521 |
|
|
);
|
1522 |
|
|
|
1523 |
|
|
assign cmd_po_stg2_incdec_ddr2_c = 1'b0;
|
1524 |
|
|
assign cmd_po_en_stg2_ddr2_c = 1'b0;
|
1525 |
|
|
|
1526 |
|
|
end else begin: mb_wrlvl_off
|
1527 |
|
|
|
1528 |
|
|
mig_7series_v2_3_ddr_phy_wrlvl_off_delay #
|
1529 |
|
|
(
|
1530 |
|
|
.TCQ (TCQ),
|
1531 |
|
|
.tCK (tCK),
|
1532 |
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
1533 |
|
|
.CLK_PERIOD (CLK_PERIOD),
|
1534 |
|
|
.PO_INITIAL_DLY(60),
|
1535 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
1536 |
|
|
.DQS_WIDTH (DQS_WIDTH),
|
1537 |
|
|
.N_CTL_LANES (N_CTL_LANES)
|
1538 |
|
|
)
|
1539 |
|
|
u_phy_wrlvl_off_delay
|
1540 |
|
|
(
|
1541 |
|
|
.clk (clk),
|
1542 |
|
|
.rst (rst),
|
1543 |
|
|
.pi_fine_dly_dec_done (pi_fine_dly_dec_done),
|
1544 |
|
|
.cmd_delay_start (phy_ctl_ready),
|
1545 |
|
|
.ctl_lane_cnt (ctl_lane_cnt),
|
1546 |
|
|
.po_s2_incdec_f (cmd_po_stg2_f_incdec),
|
1547 |
|
|
.po_en_s2_f (cmd_po_en_stg2_f),
|
1548 |
|
|
.po_s2_incdec_c (cmd_po_stg2_incdec_ddr2_c),
|
1549 |
|
|
.po_en_s2_c (cmd_po_en_stg2_ddr2_c),
|
1550 |
|
|
.po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done),
|
1551 |
|
|
.po_dec_done (dqs_po_dec_done),
|
1552 |
|
|
.phy_ctl_rdy_dly (phy_ctl_rdy_dly)
|
1553 |
|
|
);
|
1554 |
|
|
|
1555 |
|
|
assign wrlvl_byte_done = 1'b1;
|
1556 |
|
|
assign wrlvl_rank_done = 1'b1;
|
1557 |
|
|
assign po_stg2_wl_cnt = 'h0;
|
1558 |
|
|
assign wl_po_coarse_cnt = 'h0;
|
1559 |
|
|
assign wl_po_fine_cnt = 'h0;
|
1560 |
|
|
assign dbg_tap_cnt_during_wrlvl = 'h0;
|
1561 |
|
|
assign dbg_wl_edge_detect_valid = 'h0;
|
1562 |
|
|
assign dbg_rd_data_edge_detect = 'h0;
|
1563 |
|
|
assign dbg_wrlvl_fine_tap_cnt = 'h0;
|
1564 |
|
|
assign dbg_wrlvl_coarse_tap_cnt = 'h0;
|
1565 |
|
|
assign dbg_phy_wrlvl = 'h0;
|
1566 |
|
|
|
1567 |
|
|
assign wrlvl_done = 1'b1;
|
1568 |
|
|
assign wrlvl_err = 1'b0;
|
1569 |
|
|
assign dqs_po_stg2_f_incdec = 1'b0;
|
1570 |
|
|
assign dqs_po_en_stg2_f = 1'b0;
|
1571 |
|
|
assign dqs_wl_po_en_stg2_c = 1'b0;
|
1572 |
|
|
assign cmd_po_stg2_c_incdec = 1'b0;
|
1573 |
|
|
assign dqs_wl_po_stg2_c_incdec = 1'b0;
|
1574 |
|
|
assign cmd_po_en_stg2_c = 1'b0;
|
1575 |
|
|
|
1576 |
|
|
end
|
1577 |
|
|
endgenerate
|
1578 |
|
|
|
1579 |
|
|
generate
|
1580 |
|
|
if((WRLVL == "ON") && (OCAL_EN == "ON")) begin: oclk_calib
|
1581 |
|
|
|
1582 |
|
|
localparam SAMPCNTRWIDTH = 17;
|
1583 |
|
|
localparam SAMPLES = (SIM_CAL_OPTION=="NONE") ? 2048 : 4;
|
1584 |
|
|
localparam TAPCNTRWIDTH = clogb2(TAPSPERKCLK);
|
1585 |
|
|
localparam MMCM_SAMP_WAIT = (SIM_CAL_OPTION=="NONE") ? 256 : 10;
|
1586 |
|
|
localparam OCAL_SIMPLE_SCAN_SAMPS = (SIM_CAL_OPTION=="NONE") ? 2048 : 1;
|
1587 |
|
|
localparam POC_PCT_SAMPS_SOLID = 80;
|
1588 |
|
|
localparam SCAN_PCT_SAMPS_SOLID = 95;
|
1589 |
|
|
|
1590 |
|
|
mig_7series_v2_3_ddr_phy_oclkdelay_cal #
|
1591 |
|
|
(/*AUTOINSTPARAM*/
|
1592 |
|
|
// Parameters
|
1593 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
1594 |
|
|
.DQS_WIDTH (DQS_WIDTH),
|
1595 |
|
|
.DQ_WIDTH (DQ_WIDTH),
|
1596 |
|
|
//.DRAM_TYPE (DRAM_TYPE),
|
1597 |
|
|
.DRAM_WIDTH (DRAM_WIDTH),
|
1598 |
|
|
//.OCAL_EN (OCAL_EN),
|
1599 |
|
|
.OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS),
|
1600 |
|
|
.PCT_SAMPS_SOLID (POC_PCT_SAMPS_SOLID),
|
1601 |
|
|
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP),
|
1602 |
|
|
.SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID),
|
1603 |
|
|
.SAMPCNTRWIDTH (SAMPCNTRWIDTH),
|
1604 |
|
|
.SAMPLES (SAMPLES),
|
1605 |
|
|
.MMCM_SAMP_WAIT (MMCM_SAMP_WAIT),
|
1606 |
|
|
.SIM_CAL_OPTION (SIM_CAL_OPTION),
|
1607 |
|
|
.TAPCNTRWIDTH (TAPCNTRWIDTH),
|
1608 |
|
|
.TAPSPERKCLK (TAPSPERKCLK),
|
1609 |
|
|
.TCQ (TCQ),
|
1610 |
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
1611 |
|
|
.BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL)
|
1612 |
|
|
//.tCK (tCK)
|
1613 |
|
|
)
|
1614 |
|
|
u_ddr_phy_oclkdelay_cal
|
1615 |
|
|
(/*AUTOINST*/
|
1616 |
|
|
// Outputs
|
1617 |
|
|
.prbs_ignore_first_byte (prbs_ignore_first_byte),
|
1618 |
|
|
.prbs_ignore_last_bytes (prbs_ignore_last_bytes),
|
1619 |
|
|
.complex_oclkdelay_calib_done (complex_oclkdelay_calib_done),
|
1620 |
|
|
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data[16*DRAM_WIDTH-1:0]),
|
1621 |
|
|
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal[255:0]),
|
1622 |
|
|
.lim2init_write_request (lim2init_write_request),
|
1623 |
|
|
.lim_done (lim_done),
|
1624 |
|
|
.oclk_calib_resume (oclk_calib_resume),
|
1625 |
|
|
//.oclk_init_delay_done (oclk_init_delay_done),
|
1626 |
|
|
.oclk_prech_req (oclk_prech_req),
|
1627 |
|
|
.oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),
|
1628 |
|
|
.oclkdelay_calib_done (oclkdelay_calib_done),
|
1629 |
|
|
.po_en_stg23 (po_en_stg23),
|
1630 |
|
|
//.po_en_stg3 (po_en_stg3),
|
1631 |
|
|
.po_stg23_incdec (po_stg23_incdec),
|
1632 |
|
|
.po_stg23_sel (po_stg23_sel),
|
1633 |
|
|
//.po_stg3_incdec (po_stg3_incdec),
|
1634 |
|
|
.psen (psen),
|
1635 |
|
|
.psincdec (psincdec),
|
1636 |
|
|
.wrlvl_final (wrlvl_final),
|
1637 |
|
|
.rd_victim_sel (complex_ocal_rd_victim_sel),
|
1638 |
|
|
.ocal_num_samples_done_r (complex_ocal_num_samples_done_r),
|
1639 |
|
|
.complex_wrlvl_final (complex_wrlvl_final),
|
1640 |
|
|
.poc_error (poc_error),
|
1641 |
|
|
// Inputs
|
1642 |
|
|
.clk (clk),
|
1643 |
|
|
.complex_oclkdelay_calib_start (complex_oclkdelay_calib_start_w),
|
1644 |
|
|
.metaQ (pd_out),
|
1645 |
|
|
//.oclk_init_delay_start (oclk_init_delay_start),
|
1646 |
|
|
.po_counter_read_val (po_counter_read_val),
|
1647 |
|
|
.oclkdelay_calib_start (oclkdelay_calib_start),
|
1648 |
|
|
.oclkdelay_init_val (oclkdelay_init_val[5:0]),
|
1649 |
|
|
.poc_sample_pd (poc_sample_pd),
|
1650 |
|
|
.phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]),
|
1651 |
|
|
.phy_rddata_en (phy_rddata_en),
|
1652 |
|
|
.prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]),
|
1653 |
|
|
.prech_done (prech_done),
|
1654 |
|
|
.psdone (psdone),
|
1655 |
|
|
.rst (rst),
|
1656 |
|
|
.wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0]),
|
1657 |
|
|
.ocal_num_samples_inc (complex_ocal_num_samples_inc),
|
1658 |
|
|
.oclkdelay_center_calib_start (oclkdelay_center_calib_start),
|
1659 |
|
|
.oclk_center_write_resume (oclk_center_write_resume),
|
1660 |
|
|
.oclkdelay_center_calib_done (oclkdelay_center_calib_done),
|
1661 |
|
|
.dbg_ocd_lim (dbg_ocd_lim));
|
1662 |
|
|
|
1663 |
|
|
end else begin : oclk_calib_disabled
|
1664 |
|
|
|
1665 |
|
|
assign wrlvl_final = 'b0;
|
1666 |
|
|
assign psen = 'b0;
|
1667 |
|
|
assign psincdec = 'b0;
|
1668 |
|
|
assign po_stg23_sel = 'b0;
|
1669 |
|
|
assign po_stg23_incdec = 'b0;
|
1670 |
|
|
assign po_en_stg23 = 'b0;
|
1671 |
|
|
//assign oclk_init_delay_done = 1'b1;
|
1672 |
|
|
assign oclkdelay_calib_cnt = 'b0;
|
1673 |
|
|
assign oclk_prech_req = 'b0;
|
1674 |
|
|
assign oclk_calib_resume = 'b0;
|
1675 |
|
|
assign oclkdelay_calib_done = 1'b1;
|
1676 |
|
|
assign dbg_phy_oclkdelay_cal = 'h0;
|
1677 |
|
|
assign dbg_oclkdelay_rd_data = 'h0;
|
1678 |
|
|
|
1679 |
|
|
end
|
1680 |
|
|
endgenerate
|
1681 |
|
|
//***************************************************************************
|
1682 |
|
|
// Read data-offset calibration required for Phaser_In
|
1683 |
|
|
//***************************************************************************
|
1684 |
|
|
|
1685 |
|
|
generate
|
1686 |
|
|
if(DQSFOUND_CAL == "RIGHT") begin: dqsfind_calib_right
|
1687 |
|
|
mig_7series_v2_3_ddr_phy_dqs_found_cal #
|
1688 |
|
|
(
|
1689 |
|
|
.TCQ (TCQ),
|
1690 |
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
1691 |
|
|
.nCL (nCL),
|
1692 |
|
|
.AL (AL),
|
1693 |
|
|
.nCWL (nCWL),
|
1694 |
|
|
//.RANKS (RANKS),
|
1695 |
|
|
.RANKS (1),
|
1696 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
1697 |
|
|
.DQS_WIDTH (DQS_WIDTH),
|
1698 |
|
|
.DRAM_WIDTH (DRAM_WIDTH),
|
1699 |
|
|
.REG_CTRL (REG_CTRL),
|
1700 |
|
|
.SIM_CAL_OPTION (SIM_CAL_OPTION),
|
1701 |
|
|
.DRAM_TYPE (DRAM_TYPE),
|
1702 |
|
|
.NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),
|
1703 |
|
|
.N_CTL_LANES (DQS_FOUND_N_CTL_LANES),
|
1704 |
|
|
.HIGHEST_LANE (HIGHEST_LANE),
|
1705 |
|
|
.HIGHEST_BANK (HIGHEST_BANK),
|
1706 |
|
|
.BYTE_LANES_B0 (BYTE_LANES_B0),
|
1707 |
|
|
.BYTE_LANES_B1 (BYTE_LANES_B1),
|
1708 |
|
|
.BYTE_LANES_B2 (BYTE_LANES_B2),
|
1709 |
|
|
.BYTE_LANES_B3 (BYTE_LANES_B3),
|
1710 |
|
|
.BYTE_LANES_B4 (BYTE_LANES_B4),
|
1711 |
|
|
.DATA_CTL_B0 (DATA_CTL_B0),
|
1712 |
|
|
.DATA_CTL_B1 (DATA_CTL_B1),
|
1713 |
|
|
.DATA_CTL_B2 (DATA_CTL_B2),
|
1714 |
|
|
.DATA_CTL_B3 (DATA_CTL_B3),
|
1715 |
|
|
.DATA_CTL_B4 (DATA_CTL_B4)
|
1716 |
|
|
)
|
1717 |
|
|
u_ddr_phy_dqs_found_cal
|
1718 |
|
|
(
|
1719 |
|
|
.clk (clk),
|
1720 |
|
|
.rst (rst),
|
1721 |
|
|
.pi_dqs_found_start (pi_dqs_found_start),
|
1722 |
|
|
.dqsfound_retry (dqsfound_retry),
|
1723 |
|
|
.detect_pi_found_dqs (detect_pi_found_dqs),
|
1724 |
|
|
.prech_done (prech_done),
|
1725 |
|
|
.pi_dqs_found_lanes (pi_dqs_found_lanes),
|
1726 |
|
|
.pi_rst_stg1_cal (pi_rst_stg1_cal),
|
1727 |
|
|
.rd_data_offset_0 (rd_data_offset_0),
|
1728 |
|
|
.rd_data_offset_1 (rd_data_offset_1),
|
1729 |
|
|
.rd_data_offset_2 (rd_data_offset_2),
|
1730 |
|
|
.pi_dqs_found_rank_done (pi_dqs_found_rank_done),
|
1731 |
|
|
.pi_dqs_found_done (pi_dqs_found_done),
|
1732 |
|
|
.dqsfound_retry_done (dqsfound_retry_done),
|
1733 |
|
|
.dqs_found_prech_req (dqs_found_prech_req),
|
1734 |
|
|
.pi_dqs_found_err (pi_dqs_found_err),
|
1735 |
|
|
.rd_data_offset_ranks_0 (rd_data_offset_ranks_0),
|
1736 |
|
|
.rd_data_offset_ranks_1 (rd_data_offset_ranks_1),
|
1737 |
|
|
.rd_data_offset_ranks_2 (rd_data_offset_ranks_2),
|
1738 |
|
|
.rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),
|
1739 |
|
|
.rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),
|
1740 |
|
|
.rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),
|
1741 |
|
|
.po_counter_read_val (po_counter_read_val),
|
1742 |
|
|
.rd_data_offset_cal_done (rd_data_offset_cal_done),
|
1743 |
|
|
.fine_adjust_done (fine_adjust_done),
|
1744 |
|
|
.fine_adjust_lane_cnt (fine_adjust_lane_cnt),
|
1745 |
|
|
.ck_po_stg2_f_indec (ck_po_stg2_f_indec),
|
1746 |
|
|
.ck_po_stg2_f_en (ck_po_stg2_f_en),
|
1747 |
|
|
.dbg_dqs_found_cal (dbg_dqs_found_cal)
|
1748 |
|
|
);
|
1749 |
|
|
end else begin: dqsfind_calib_left
|
1750 |
|
|
mig_7series_v2_3_ddr_phy_dqs_found_cal_hr #
|
1751 |
|
|
(
|
1752 |
|
|
.TCQ (TCQ),
|
1753 |
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
1754 |
|
|
.nCL (nCL),
|
1755 |
|
|
.AL (AL),
|
1756 |
|
|
.nCWL (nCWL),
|
1757 |
|
|
//.RANKS (RANKS),
|
1758 |
|
|
.RANKS (1),
|
1759 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
1760 |
|
|
.DQS_WIDTH (DQS_WIDTH),
|
1761 |
|
|
.DRAM_WIDTH (DRAM_WIDTH),
|
1762 |
|
|
.REG_CTRL (REG_CTRL),
|
1763 |
|
|
.SIM_CAL_OPTION (SIM_CAL_OPTION),
|
1764 |
|
|
.DRAM_TYPE (DRAM_TYPE),
|
1765 |
|
|
.NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),
|
1766 |
|
|
.N_CTL_LANES (DQS_FOUND_N_CTL_LANES),
|
1767 |
|
|
.HIGHEST_LANE (HIGHEST_LANE),
|
1768 |
|
|
.HIGHEST_BANK (HIGHEST_BANK),
|
1769 |
|
|
.BYTE_LANES_B0 (BYTE_LANES_B0),
|
1770 |
|
|
.BYTE_LANES_B1 (BYTE_LANES_B1),
|
1771 |
|
|
.BYTE_LANES_B2 (BYTE_LANES_B2),
|
1772 |
|
|
.BYTE_LANES_B3 (BYTE_LANES_B3),
|
1773 |
|
|
.BYTE_LANES_B4 (BYTE_LANES_B4),
|
1774 |
|
|
.DATA_CTL_B0 (DATA_CTL_B0),
|
1775 |
|
|
.DATA_CTL_B1 (DATA_CTL_B1),
|
1776 |
|
|
.DATA_CTL_B2 (DATA_CTL_B2),
|
1777 |
|
|
.DATA_CTL_B3 (DATA_CTL_B3),
|
1778 |
|
|
.DATA_CTL_B4 (DATA_CTL_B4)
|
1779 |
|
|
)
|
1780 |
|
|
u_ddr_phy_dqs_found_cal_hr
|
1781 |
|
|
(
|
1782 |
|
|
.clk (clk),
|
1783 |
|
|
.rst (rst),
|
1784 |
|
|
.pi_dqs_found_start (pi_dqs_found_start),
|
1785 |
|
|
.dqsfound_retry (dqsfound_retry),
|
1786 |
|
|
.detect_pi_found_dqs (detect_pi_found_dqs),
|
1787 |
|
|
.prech_done (prech_done),
|
1788 |
|
|
.pi_dqs_found_lanes (pi_dqs_found_lanes),
|
1789 |
|
|
.pi_rst_stg1_cal (pi_rst_stg1_cal),
|
1790 |
|
|
.rd_data_offset_0 (rd_data_offset_0),
|
1791 |
|
|
.rd_data_offset_1 (rd_data_offset_1),
|
1792 |
|
|
.rd_data_offset_2 (rd_data_offset_2),
|
1793 |
|
|
.pi_dqs_found_rank_done (pi_dqs_found_rank_done),
|
1794 |
|
|
.pi_dqs_found_done (pi_dqs_found_done),
|
1795 |
|
|
.dqsfound_retry_done (dqsfound_retry_done),
|
1796 |
|
|
.dqs_found_prech_req (dqs_found_prech_req),
|
1797 |
|
|
.pi_dqs_found_err (pi_dqs_found_err),
|
1798 |
|
|
.rd_data_offset_ranks_0 (rd_data_offset_ranks_0),
|
1799 |
|
|
.rd_data_offset_ranks_1 (rd_data_offset_ranks_1),
|
1800 |
|
|
.rd_data_offset_ranks_2 (rd_data_offset_ranks_2),
|
1801 |
|
|
.rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),
|
1802 |
|
|
.rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),
|
1803 |
|
|
.rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),
|
1804 |
|
|
.po_counter_read_val (po_counter_read_val),
|
1805 |
|
|
.rd_data_offset_cal_done (rd_data_offset_cal_done),
|
1806 |
|
|
.fine_adjust_done (fine_adjust_done),
|
1807 |
|
|
.fine_adjust_lane_cnt (fine_adjust_lane_cnt),
|
1808 |
|
|
.ck_po_stg2_f_indec (ck_po_stg2_f_indec),
|
1809 |
|
|
.ck_po_stg2_f_en (ck_po_stg2_f_en),
|
1810 |
|
|
.dbg_dqs_found_cal (dbg_dqs_found_cal)
|
1811 |
|
|
);
|
1812 |
|
|
end
|
1813 |
|
|
endgenerate
|
1814 |
|
|
|
1815 |
|
|
//***************************************************************************
|
1816 |
|
|
// Read-leveling calibration logic
|
1817 |
|
|
//***************************************************************************
|
1818 |
|
|
|
1819 |
|
|
mig_7series_v2_3_ddr_phy_rdlvl #
|
1820 |
|
|
(
|
1821 |
|
|
.TCQ (TCQ),
|
1822 |
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
1823 |
|
|
.CLK_PERIOD (CLK_PERIOD),
|
1824 |
|
|
.DQ_WIDTH (DQ_WIDTH),
|
1825 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
1826 |
|
|
.DQS_WIDTH (DQS_WIDTH),
|
1827 |
|
|
.DRAM_WIDTH (DRAM_WIDTH),
|
1828 |
|
|
.RANKS (1),
|
1829 |
|
|
.PER_BIT_DESKEW (PER_BIT_DESKEW),
|
1830 |
|
|
.SIM_CAL_OPTION (SIM_CAL_OPTION),
|
1831 |
|
|
.DEBUG_PORT (DEBUG_PORT),
|
1832 |
|
|
.DRAM_TYPE (DRAM_TYPE),
|
1833 |
|
|
.OCAL_EN (OCAL_EN),
|
1834 |
|
|
.IDELAY_ADJ (IDELAY_ADJ)
|
1835 |
|
|
)
|
1836 |
|
|
u_ddr_phy_rdlvl
|
1837 |
|
|
(
|
1838 |
|
|
.clk (clk),
|
1839 |
|
|
.rst (rst),
|
1840 |
|
|
.mpr_rdlvl_done (mpr_rdlvl_done),
|
1841 |
|
|
.mpr_rdlvl_start (mpr_rdlvl_start),
|
1842 |
|
|
.mpr_last_byte_done (mpr_last_byte_done),
|
1843 |
|
|
.mpr_rnk_done (mpr_rnk_done),
|
1844 |
|
|
.rdlvl_stg1_start (rdlvl_stg1_start),
|
1845 |
|
|
.rdlvl_stg1_done (rdlvl_stg1_done),
|
1846 |
|
|
.rdlvl_stg1_rnk_done (rdlvl_stg1_rank_done),
|
1847 |
|
|
.rdlvl_stg1_err (rdlvl_stg1_err),
|
1848 |
|
|
.mpr_rdlvl_err (mpr_rdlvl_err),
|
1849 |
|
|
.rdlvl_err (rdlvl_err),
|
1850 |
|
|
.rdlvl_prech_req (rdlvl_prech_req),
|
1851 |
|
|
.rdlvl_last_byte_done (rdlvl_last_byte_done),
|
1852 |
|
|
.rdlvl_assrt_common (rdlvl_assrt_common),
|
1853 |
|
|
.prech_done (prech_done),
|
1854 |
|
|
.phy_if_empty (phy_if_empty),
|
1855 |
|
|
.idelaye2_init_val (idelaye2_init_val),
|
1856 |
|
|
.rd_data (phy_rddata),
|
1857 |
|
|
.pi_en_stg2_f (rdlvl_pi_stg2_f_en),
|
1858 |
|
|
.pi_stg2_f_incdec (rdlvl_pi_stg2_f_incdec),
|
1859 |
|
|
.pi_stg2_load (pi_stg2_load),
|
1860 |
|
|
.pi_stg2_reg_l (pi_stg2_reg_l),
|
1861 |
|
|
.dqs_po_dec_done (dqs_po_dec_done),
|
1862 |
|
|
.pi_counter_read_val (pi_counter_read_val),
|
1863 |
|
|
.pi_fine_dly_dec_done (pi_fine_dly_dec_done),
|
1864 |
|
|
.idelay_ce (idelay_ce_int),
|
1865 |
|
|
.idelay_inc (idelay_inc_int),
|
1866 |
|
|
.idelay_ld (idelay_ld),
|
1867 |
|
|
.wrcal_cnt (po_stg2_wrcal_cnt),
|
1868 |
|
|
.pi_stg2_rdlvl_cnt (pi_stg2_rdlvl_cnt),
|
1869 |
|
|
.dlyval_dq (dlyval_dq),
|
1870 |
|
|
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
|
1871 |
|
|
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
|
1872 |
|
|
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
|
1873 |
|
|
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
|
1874 |
|
|
.dbg_idel_up_all (dbg_idel_up_all),
|
1875 |
|
|
.dbg_idel_down_all (dbg_idel_down_all),
|
1876 |
|
|
.dbg_idel_up_cpt (dbg_idel_up_cpt),
|
1877 |
|
|
.dbg_idel_down_cpt (dbg_idel_down_cpt),
|
1878 |
|
|
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
|
1879 |
|
|
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
|
1880 |
|
|
.dbg_phy_rdlvl (dbg_phy_rdlvl)
|
1881 |
|
|
);
|
1882 |
|
|
|
1883 |
|
|
|
1884 |
|
|
generate
|
1885 |
|
|
if((DRAM_TYPE == "DDR3") && (nCK_PER_CLK == 4) && (BYPASS_COMPLEX_RDLVL=="FALSE")) begin:ddr_phy_prbs_rdlvl_gen
|
1886 |
|
|
mig_7series_v2_3_ddr_phy_prbs_rdlvl #
|
1887 |
|
|
(
|
1888 |
|
|
.TCQ (TCQ),
|
1889 |
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
1890 |
|
|
.DQ_WIDTH (DQ_WIDTH),
|
1891 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
1892 |
|
|
.DQS_WIDTH (DQS_WIDTH),
|
1893 |
|
|
.DRAM_WIDTH (DRAM_WIDTH),
|
1894 |
|
|
.RANKS (1),
|
1895 |
|
|
.SIM_CAL_OPTION (SIM_CAL_OPTION),
|
1896 |
|
|
.PRBS_WIDTH (PRBS_WIDTH),
|
1897 |
|
|
.FIXED_VICTIM (FIXED_VICTIM),
|
1898 |
|
|
.FINE_PER_BIT (FINE_PER_BIT),
|
1899 |
|
|
.CENTER_COMP_MODE (CENTER_COMP_MODE),
|
1900 |
|
|
.PI_VAL_ADJ (PI_VAL_ADJ)
|
1901 |
|
|
)
|
1902 |
|
|
u_ddr_phy_prbs_rdlvl
|
1903 |
|
|
(
|
1904 |
|
|
.clk (clk),
|
1905 |
|
|
.rst (rst),
|
1906 |
|
|
.prbs_rdlvl_start (prbs_rdlvl_start),
|
1907 |
|
|
.prbs_rdlvl_done (prbs_rdlvl_done),
|
1908 |
|
|
.prbs_last_byte_done (prbs_last_byte_done),
|
1909 |
|
|
.prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),
|
1910 |
|
|
.complex_sample_cnt_inc (complex_sample_cnt_inc),
|
1911 |
|
|
.prech_done (prech_done),
|
1912 |
|
|
.phy_if_empty (phy_if_empty),
|
1913 |
|
|
.rd_data (phy_rddata),
|
1914 |
|
|
.compare_data (prbs_o),
|
1915 |
|
|
.pi_counter_read_val (pi_counter_read_val),
|
1916 |
|
|
.pi_en_stg2_f (prbs_pi_stg2_f_en),
|
1917 |
|
|
.pi_stg2_f_incdec (prbs_pi_stg2_f_incdec),
|
1918 |
|
|
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
|
1919 |
|
|
.pi_stg2_prbs_rdlvl_cnt (pi_stg2_prbs_rdlvl_cnt),
|
1920 |
|
|
.prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r),
|
1921 |
|
|
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),
|
1922 |
|
|
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps),
|
1923 |
|
|
.rd_victim_sel (rd_victim_sel),
|
1924 |
|
|
.complex_victim_inc (complex_victim_inc),
|
1925 |
|
|
.reset_rd_addr (reset_rd_addr),
|
1926 |
|
|
.read_pause (read_pause),
|
1927 |
|
|
.fine_delay_incdec_pb (fine_delay_incdec_pb),
|
1928 |
|
|
.fine_delay_sel (fine_delay_sel)
|
1929 |
|
|
);
|
1930 |
|
|
end else begin:ddr_phy_prbs_rdlvl_off
|
1931 |
|
|
|
1932 |
|
|
assign prbs_rdlvl_done = rdlvl_stg1_done ;
|
1933 |
|
|
//assign prbs_last_byte_done = rdlvl_stg1_rank_done ;
|
1934 |
|
|
assign prbs_last_byte_done = rdlvl_stg1_done;
|
1935 |
|
|
assign read_pause = 1'b0;
|
1936 |
|
|
assign reset_rd_addr = 1'b0;
|
1937 |
|
|
assign prbs_rdlvl_prech_req = 1'b0 ;
|
1938 |
|
|
assign prbs_pi_stg2_f_en = 1'b0 ;
|
1939 |
|
|
assign prbs_pi_stg2_f_incdec = 1'b0 ;
|
1940 |
|
|
assign pi_stg2_prbs_rdlvl_cnt = 'b0 ;
|
1941 |
|
|
assign dbg_prbs_rdlvl = 'h0 ;
|
1942 |
|
|
assign prbs_final_dqs_tap_cnt_r = {(6*DQS_WIDTH*RANKS){1'b0}};
|
1943 |
|
|
assign dbg_prbs_first_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}};
|
1944 |
|
|
assign dbg_prbs_second_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}};
|
1945 |
|
|
|
1946 |
|
|
end
|
1947 |
|
|
endgenerate
|
1948 |
|
|
|
1949 |
|
|
//***************************************************************************
|
1950 |
|
|
// Temperature induced PI tap adjustment logic
|
1951 |
|
|
//***************************************************************************
|
1952 |
|
|
|
1953 |
|
|
mig_7series_v2_3_ddr_phy_tempmon #
|
1954 |
|
|
(
|
1955 |
|
|
.TCQ (TCQ)
|
1956 |
|
|
)
|
1957 |
|
|
ddr_phy_tempmon_0
|
1958 |
|
|
(
|
1959 |
|
|
.rst (rst),
|
1960 |
|
|
.clk (clk),
|
1961 |
|
|
.calib_complete (calib_complete),
|
1962 |
|
|
.tempmon_pi_f_inc (tempmon_pi_f_inc),
|
1963 |
|
|
.tempmon_pi_f_dec (tempmon_pi_f_dec),
|
1964 |
|
|
.tempmon_sel_pi_incdec (tempmon_sel_pi_incdec),
|
1965 |
|
|
.device_temp (device_temp),
|
1966 |
|
|
.tempmon_sample_en (tempmon_sample_en)
|
1967 |
|
|
);
|
1968 |
|
|
|
1969 |
|
|
endmodule
|