URL
https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk
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1 |
2 |
ZTEX |
SET_FLAG MODE BATCH
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2 |
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SET_FLAG STANDALONE_MODE TRUE
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3 |
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SET_PREFERENCE upgrade_mode yes
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4 |
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SET_PREFERENCE ipi_mode no
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5 |
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SET_PREFERENCE devicefamily artix7
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6 |
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SET_PREFERENCE device xc7a35t
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7 |
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SET_PREFERENCE speedgrade -1
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8 |
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SET_PREFERENCE package csg324
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9 |
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SET_PREFERENCE verilogsim true
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10 |
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SET_PREFERENCE vhdlsim false
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11 |
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SET_PREFERENCE designentry Verilog
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12 |
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SET_PREFERENCE outputdirectory /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.14/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
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13 |
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SET_PREFERENCE subworkingdirectory /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.14/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
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14 |
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SET_PREFERENCE flowvendor Other
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15 |
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SET_PREFERENCE tool vivado
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16 |
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SET_PREFERENCE compnamestatus 0
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17 |
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SET_PARAMETER component_name mig_7series_0
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18 |
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SET_PARAMETER xml_input_file /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.14/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
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19 |
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SET_PARAMETER data_dir_path /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_2
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20 |
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SET_CORE_NAME Memory Interface Generator (MIG 7 Series)
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21 |
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SET_CORE_VERSION 2.2
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22 |
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SET_CORE_VLNV xilinx.com:ip:mig_7series:2.2
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23 |
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SET_CORE_PATH /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_2
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24 |
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SET_CORE_DATASHEET /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_2/data/docs/ds176_7series_MIS.pdf
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