1 |
2 |
ZTEX |
/*%
|
2 |
|
|
ZTEX Firmware Kit for EZ-USB FX3 Microcontrollers
|
3 |
|
|
Copyright (C) 2009-2017 ZTEX GmbH.
|
4 |
|
|
http://www.ztex.de
|
5 |
|
|
|
6 |
|
|
This Source Code Form is subject to the terms of the Mozilla Public
|
7 |
|
|
License, v. 2.0. If a copy of the MPL was not distributed with this file,
|
8 |
|
|
You can obtain one at http://mozilla.org/MPL/2.0/.
|
9 |
|
|
|
10 |
|
|
Alternatively, the contents of this file may be used under the terms
|
11 |
|
|
of the GNU General Public License Version 3, as described below:
|
12 |
|
|
|
13 |
|
|
This program is free software; you can redistribute it and/or modify
|
14 |
|
|
it under the terms of the GNU General Public License version 3 as
|
15 |
|
|
published by the Free Software Foundation.
|
16 |
|
|
|
17 |
|
|
This program is distributed in the hope that it will be useful, but
|
18 |
|
|
WITHOUT ANY WARRANTY; without even the implied warranty of
|
19 |
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
20 |
|
|
General Public License for more details.
|
21 |
|
|
|
22 |
|
|
You should have received a copy of the GNU General Public License
|
23 |
|
|
along with this program; if not, see http://www.gnu.org/licenses/.
|
24 |
|
|
%*/
|
25 |
|
|
/*
|
26 |
|
|
GPIF-II waveform for ezusb_io module for the high speed interface of default firmware.
|
27 |
|
|
The GPIF-II project can be found in ../default/fpga-fx3/ezusb_iocydsn
|
28 |
|
|
*/
|
29 |
|
|
|
30 |
|
|
#ifndef _ZTEX_EZUSB_IO1_C_
|
31 |
|
|
#define _ZTEX_EZUSB_IO1_C_
|
32 |
|
|
|
33 |
|
|
#include "cyu3types.h"
|
34 |
|
|
#include "cyu3gpif.h"
|
35 |
|
|
|
36 |
|
|
//Transition function values used in the state machine.
|
37 |
|
|
uint16_t ztex_ezusb_io1_gpif_transition[] = {
|
38 |
|
|
0x0000, 0xAAAA, 0x5555, 0x1111, 0x8888, 0x7777
|
39 |
|
|
};
|
40 |
|
|
|
41 |
|
|
/* Table containing the transition information for various states.
|
42 |
|
|
This table has to be stored in the WAVEFORM Registers.
|
43 |
|
|
This array consists of non-replicated waveform descriptors and acts as a
|
44 |
|
|
waveform table. */
|
45 |
|
|
CyU3PGpifWaveData ztex_ezusb_io1_gpif_wavedata[] = {
|
46 |
|
|
{{0x1E738301,0x040100C4,0x80000000},{0x00000000,0x00000000,0x00000000}},
|
47 |
|
|
{{0x2E738302,0x04000000,0x80000000},{0x00000000,0x00000000,0x00000000}},
|
48 |
|
|
{{0x1E738301,0x040100C4,0x80000000},{0x5E702004,0x20000000,0xC0100000}},
|
49 |
|
|
{{0x00000000,0x00000000,0x00000000},{0x00000000,0x00000000,0x00000000}},
|
50 |
|
|
{{0x00000000,0x00000000,0x00000000},{0x2E738005,0x00000000,0xC0100000}},
|
51 |
|
|
{{0x00000000,0x00000000,0x00000000},{0x3E702003,0x20010008,0x80000000}},
|
52 |
|
|
{{0x00000000,0x00000000,0x00000000},{0x5E702004,0x20000000,0xC0100000}}
|
53 |
|
|
};
|
54 |
|
|
|
55 |
|
|
// Table that maps state indexes to the descriptor table indexes.
|
56 |
|
|
uint8_t ztex_ezusb_io1_gpif_wavedata_position[] = {
|
57 |
|
|
0,1,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
58 |
|
|
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
59 |
|
|
0,4,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
60 |
|
|
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
61 |
|
|
0,5,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
62 |
|
|
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
63 |
|
|
0,6,0,2,0,0
|
64 |
|
|
};
|
65 |
|
|
|
66 |
|
|
// GPIF II configuration register values.
|
67 |
|
|
uint32_t ztex_ezusb_io1_gpif_reg_value[] = {
|
68 |
|
|
0x800083B0, /* CY_U3P_PIB_GPIF_CONFIG */
|
69 |
|
|
0x00001467, /* CY_U3P_PIB_GPIF_BUS_CONFIG */
|
70 |
|
|
0x01000002, /* CY_U3P_PIB_GPIF_BUS_CONFIG2 */
|
71 |
|
|
0x00000044, /* CY_U3P_PIB_GPIF_AD_CONFIG */
|
72 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_STATUS */
|
73 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_INTR */
|
74 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_INTR_MASK */
|
75 |
|
|
0x00000082, /* CY_U3P_PIB_GPIF_SERIAL_IN_CONFIG */
|
76 |
|
|
0x00000782, /* CY_U3P_PIB_GPIF_SERIAL_OUT_CONFIG */
|
77 |
|
|
0x00000500, /* CY_U3P_PIB_GPIF_CTRL_BUS_DIRECTION */
|
78 |
|
|
0x0000FFFF, /* CY_U3P_PIB_GPIF_CTRL_BUS_DEFAULT */
|
79 |
|
|
0x0000003F, /* CY_U3P_PIB_GPIF_CTRL_BUS_POLARITY */
|
80 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_TOGGLE */
|
81 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
82 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
83 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
84 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
85 |
|
|
0x00000011, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
86 |
|
|
0x00000010, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
87 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
88 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
89 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
90 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
91 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
92 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
93 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
94 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
95 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
96 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
|
97 |
|
|
0x00000006, /* CY_U3P_PIB_GPIF_CTRL_COUNT_CONFIG */
|
98 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COUNT_RESET */
|
99 |
|
|
0x0000FFFF, /* CY_U3P_PIB_GPIF_CTRL_COUNT_LIMIT */
|
100 |
|
|
0x0000010A, /* CY_U3P_PIB_GPIF_ADDR_COUNT_CONFIG */
|
101 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COUNT_RESET */
|
102 |
|
|
0x0000FFFF, /* CY_U3P_PIB_GPIF_ADDR_COUNT_LIMIT */
|
103 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_STATE_COUNT_CONFIG */
|
104 |
|
|
0x0000FFFF, /* CY_U3P_PIB_GPIF_STATE_COUNT_LIMIT */
|
105 |
|
|
0x0000010A, /* CY_U3P_PIB_GPIF_DATA_COUNT_CONFIG */
|
106 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_DATA_COUNT_RESET */
|
107 |
|
|
0x0000FFFF, /* CY_U3P_PIB_GPIF_DATA_COUNT_LIMIT */
|
108 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_VALUE */
|
109 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_MASK */
|
110 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_VALUE */
|
111 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_MASK */
|
112 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_VALUE */
|
113 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_MASK */
|
114 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_DATA_CTRL */
|
115 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
|
116 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
|
117 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
|
118 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
|
119 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
|
120 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
|
121 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
|
122 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
|
123 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
|
124 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
|
125 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
|
126 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
|
127 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
|
128 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
|
129 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
|
130 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
|
131 |
|
|
0x80010400, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
|
132 |
|
|
0x80010401, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
|
133 |
|
|
0x80010402, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
|
134 |
|
|
0x80010403, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
|
135 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_LAMBDA_STAT */
|
136 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_ALPHA_STAT */
|
137 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_BETA_STAT */
|
138 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_CTRL_STAT */
|
139 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH */
|
140 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH_TIMEOUT */
|
141 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CRC_CONFIG */
|
142 |
|
|
0x00000000, /* CY_U3P_PIB_GPIF_CRC_DATA */
|
143 |
|
|
0xFFFFFFC1 /* CY_U3P_PIB_GPIF_BETA_DEASSERT */
|
144 |
|
|
};
|
145 |
|
|
|
146 |
|
|
const CyU3PGpifConfig_t ztex_ezusb_io1_gpif_data = {
|
147 |
|
|
(uint16_t)(sizeof(ztex_ezusb_io1_gpif_wavedata_position)/sizeof(uint8_t)),
|
148 |
|
|
ztex_ezusb_io1_gpif_wavedata,
|
149 |
|
|
ztex_ezusb_io1_gpif_wavedata_position,
|
150 |
|
|
(uint16_t)(sizeof(ztex_ezusb_io1_gpif_transition)/sizeof(uint16_t)),
|
151 |
|
|
ztex_ezusb_io1_gpif_transition,
|
152 |
|
|
(uint16_t)(sizeof(ztex_ezusb_io1_gpif_reg_value)/sizeof(uint32_t)),
|
153 |
|
|
ztex_ezusb_io1_gpif_reg_value
|
154 |
|
|
};
|
155 |
|
|
|
156 |
|
|
uint8_t ztex_ezusb_io1_start(CyU3PDmaSocketId_t in_socket, CyU3PDmaSocketId_t out_socket) {
|
157 |
|
|
// load and start gpif
|
158 |
|
|
ZTEX_REC_RET( CyU3PGpifLoad ( &ztex_ezusb_io1_gpif_data ) );
|
159 |
|
|
|
160 |
|
|
// CyU3PDmaChannel* ch = CyU3PDmaChannelGetHandle(out_socket);
|
161 |
|
|
// ZTEX_LOG("channel size: %d", ch->count*ch->size);
|
162 |
|
|
// ZTEX_REC( CyU3PGpifSocketConfigure(0, out_socket, ch->count*ch->size-3, CyFalse, 1) ); // thread 0 is output socket: FPGA --> EZUSB, AFULL_FLAG
|
163 |
|
|
ZTEX_REC( CyU3PGpifSocketConfigure(0, out_socket, 2, CyFalse, 1) ); // thread 0 is output socket: FPGA --> EZUSB, FULL_FLAG
|
164 |
|
|
ZTEX_REC( CyU3PGpifSocketConfigure(1, in_socket, 2, CyFalse, 1) ); // thread 1 is input socket: EZUSB --> FPGA, EMPTY_FLAG
|
165 |
|
|
|
166 |
|
|
ZTEX_REC_RET( CyU3PGpifSMStart (0, 0) );
|
167 |
|
|
|
168 |
|
|
return 0;
|
169 |
|
|
}
|
170 |
|
|
|
171 |
|
|
uint8_t ztex_ezusb_io1_stop() {
|
172 |
|
|
CyU3PGpifDisable(CyTrue);
|
173 |
|
|
return 0;
|
174 |
|
|
}
|
175 |
|
|
|
176 |
|
|
#endif // _ZTEX_EZUSB_IO1_C_
|
177 |
|
|
|