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[/] [usb_fpga_2_16/] [trunk/] [include/] [ztex.h] - Blame information for rev 2

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1 2 ZTEX
/*!
2
   ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
3
   Copyright (C) 2009-2011 ZTEX GmbH.
4
   http://www.ztex.de
5
 
6
   This program is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License version 3 as
8
   published by the Free Software Foundation.
9
 
10
   This program is distributed in the hope that it will be useful, but
11
   WITHOUT ANY WARRANTY; without even the implied warranty of
12
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13
   General Public License for more details.
14
 
15
   You should have received a copy of the GNU General Public License
16
   along with this program; if not, see http://www.gnu.org/licenses/.
17
!*/
18
 
19
/*
20
   Puts everything together.
21
*/
22
 
23
#ifndef[ZTEX_H]
24
#define[ZTEX_H]
25
 
26
#define[INIT_CMDS;][]
27
 
28
#ifneq[PRODUCT_IS][UFM-1_15]
29
#define[UFM_1_15X_DETECTION_ENABLED][0]
30
#endif
31
 
32
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
33
__xdata BYTE is_ufm_1_15x;
34
#endif
35
 
36
/* *********************************************************************
37
   ***** include the basic functions ***********************************
38
   ********************************************************************* */
39
#include[ztex-utils.h]
40
 
41
/* *********************************************************************
42
   ***** I2C helper functions, EEPROM and MAC EEPROM support ***********
43
   ********************************************************************* */
44
#ifneq[EEPROM_DISABLED][1]
45
 
46
#ifneq[EEPROM_MAC_DISABLED][1]
47
#ifeq[PRODUCT_IS][UFM-1_15]
48
#define[MAC_EEPROM_ENABLED]
49
#endif // PRODUCT_IS=UFM-1_15
50
#ifeq[PRODUCT_IS][UFM-1_15Y]
51
#define[MAC_EEPROM_ENABLED]
52
#endif // PRODUCT_IS=UFM-1_15Y
53
#ifeq[PRODUCT_IS][UFM-2_16]
54
#define[MAC_EEPROM_ENABLED]
55
#endif // PRODUCT_IS=UFM-2_16
56
#ifeq[PRODUCT_IS][UFM-2_13]
57
#define[MAC_EEPROM_ENABLED]
58
#endif // PRODUCT_IS=UFM-2_13
59
#endif // EEPROM_MAC_DISABLED
60
 
61
#include[ztex-eeprom.h]
62
 
63
#endif // EEPROM_DISABLED
64
 
65
 
66
/* *********************************************************************
67
   ***** Flash memory support ******************************************
68
   ********************************************************************* */
69
#ifeq[FLASH_ENABLED][1]
70
 
71
#ifeq[PRODUCT_IS][UFM-1_1]
72
#define[MMC_PORT][E]
73
#define[MMC_BIT_CS][7]
74
#define[MMC_BIT_DI][6]
75
#define[MMC_BIT_DO][4]
76
#define[MMC_BIT_CLK][5]
77
#include[ztex-flash1.h]
78
 
79
#elifeq[PRODUCT_IS][UFM-1_2]
80
#define[MMC_PORT][E]
81
#define[MMC_BIT_CS][7]
82
#define[MMC_BIT_DI][6]
83
#define[MMC_BIT_DO][4]
84
#define[MMC_BIT_CLK][5]
85
#include[ztex-flash1.h]
86
 
87
#elifeq[PRODUCT_IS][UM-1_0]
88
#define[MMC_PORT][C]
89
#define[MMC_BIT_CS][7]
90
#define[MMC_BIT_DI][6]
91
#define[MMC_BIT_DO][4]
92
#define[MMC_BIT_CLK][5]
93
#include[ztex-flash1.h]
94
 
95
#elifeq[PRODUCT_IS][UFM-1_10]
96
#define[MMC_PORT][A]
97
#define[MMC__PORT_DO][D]
98
#define[MMC_BIT_DO][0]
99
#define[MMC_BIT_CS][5]
100
#define[MMC_BIT_DI][6]
101
#define[MMC_BIT_CLK][7]
102
#include[ztex-flash1.h]
103
 
104
#elifeq[PRODUCT_IS][UFM-1_11]
105
#define[MMC_PORT][C]
106
#define[MMC__PORT_DO][D]
107
#define[MMC_BIT_DO][0]
108
#define[MMC_BIT_CS][5]
109
#define[MMC_BIT_DI][7]
110
#define[MMC_BIT_CLK][6]
111
#include[ztex-flash1.h]
112
 
113
#elifeq[PRODUCT_IS][UFM-1_15]
114
#define[MMC_PORT][C]
115
#define[MMC_BIT_DO][4]
116
#define[MMC_BIT_CS][5]
117
#define[MMC_BIT_DI][7]
118
#define[MMC_BIT_CLK][6]
119
#include[ztex-flash1.h]
120
 
121
#elifeq[PRODUCT_IS][UXM-1_0]
122
#define[MMC_PORT][C]
123
#define[MMC_BIT_CS][7]
124
#define[MMC_BIT_DI][6]
125
#define[MMC_BIT_DO][4]
126
#define[MMC_BIT_CLK][5]
127
#include[ztex-flash1.h]
128
 
129
#elifeq[PRODUCT_IS][UFM-2_16]
130
#define[SPI_PORT][C]
131
#define[SPI_BIT_DO][4]
132
#define[SPI_BIT_CS][5]
133
#define[SPI_BIT_CLK][6]
134
#define[SPI_BIT_DI][7]
135
#include[ztex-flash2.h]
136
 
137
#elifeq[PRODUCT_IS][UFM-2_13]
138
#define[SPI_PORT][C]
139
#define[SPI_BIT_DO][4]
140
#define[SPI_BIT_CS][5]
141
#define[SPI_BIT_CLK][6]
142
#define[SPI_BIT_DI][7]
143
#include[ztex-flash2.h]
144
 
145
#else
146
#warning[Flash memory access is not supported by this product]
147
#define[FLASH_ENABLED][0]
148
#endif
149
#endif
150
 
151
/* *********************************************************************
152
   ***** FPGA configuration support ************************************
153
   ********************************************************************* */
154
#ifeq[PRODUCT_IS][UFM-1_0]
155
#include[ztex-fpga1.h]
156
#elifeq[PRODUCT_IS][UFM-1_1]
157
#include[ztex-fpga1.h]
158
#elifeq[PRODUCT_IS][UFM-1_2]
159
#include[ztex-fpga1.h]
160
#elifeq[PRODUCT_IS][UFM-1_10]
161
#include[ztex-fpga2.h]
162
#elifeq[PRODUCT_IS][UFM-1_11]
163
#include[ztex-fpga3.h]
164
#elifeq[PRODUCT_IS][UFM-1_15]
165
#include[ztex-fpga4.h]
166
#elifeq[PRODUCT_IS][UFM-1_15Y]
167
#include[ztex-fpga5.h]
168
#elifeq[PRODUCT_IS][UFM-2_16]
169
#include[ztex-fpga6.h]
170
#elifeq[PRODUCT_IS][UFM-2_13]
171
#include[ztex-fpga6.h]
172
#endif
173
 
174
 
175
/* *********************************************************************
176
   ***** DEBUG helper functions ****************************************
177
   ********************************************************************* */
178
#ifeq[DEBUG_ENABLED][1]
179
#include[ztex-debug.h]
180
#endif
181
 
182
 
183
/* *********************************************************************
184
   ***** XMEGA support *************************************************
185
   ********************************************************************* */
186
#ifneq[XMEGA_DISABLED][1]
187
 
188
#ifeq[PRODUCT_IS][UXM-1_0]
189
#define[PDI_PORT][A]
190
#define[PDI_BIT_CLK][0]
191
#define[PDI_BIT_DATA][1]
192
#include[ztex-xmega.h]
193
#endif
194
 
195
#ifeq[EXP_1_10_ENABLED][1]
196
#ifneq[PRODUCT_IS][UFM-1_0]
197
#elifneq[PRODUCT_IS][UFM-1_1]
198
#elifneq[PRODUCT_IS][UFM-1_2]
199
#elifneq[PRODUCT_IS][UFM-1_10]
200
#elifneq[PRODUCT_IS][UFM-1_11]
201
#elifneq[PRODUCT_IS][UFM-1_15]
202
#warning[ZTEX Experimental Board 1.10 is not supported by this product.]
203
#endif
204
#define[PDI_PORT][E]
205
#define[PDI_BIT_CLK][5]
206
#define[PDI_BIT_DATA][4]
207
#include[ztex-xmega.h]
208
#endif
209
 
210
#endif
211
 
212
/* *********************************************************************
213
   ***** define the descriptors ****************************************
214
   ********************************************************************* */
215
#include[ztex-descriptors.h]
216
 
217
 
218
/* *********************************************************************
219
   ***** Temperature sensor support ************************************
220
   ********************************************************************* */
221
#ifneq[EEPROM_DISABLED][1]
222
#ifneq[TEMP_SENSOR_DISABLED][1]
223
#ifeq[PRODUCT_IS][UFM-1_15Y]
224
#include[ztex-temp1.h]
225
#endif
226
 
227
#endif // TEMP_SENSOR_DISABLED
228
#endif // EEPROM_DISABLED
229
 
230
 
231
/* *********************************************************************
232
   ***** interrupt routines ********************************************
233
   ********************************************************************* */
234
#include[ztex-isr.h]
235
 
236
 
237
/* *********************************************************************
238
   ***** mac_eeprom_init ***********************************************
239
   ********************************************************************* */
240
#ifdef[@CAPABILITY_MAC_EEPROM;]
241
void mac_eeprom_init ( ) {
242
    BYTE b,c,d;
243
    __xdata BYTE buf[5];
244
    __code char hexdigits[] = "0123456789ABCDEF";
245
 
246
    mac_eeprom_read ( buf, 0, 3 );       // read signature
247
    if ( buf[0]==67 && buf[1]==68 && buf[2]==48 ) {
248
        config_data_valid = 1;
249
        mac_eeprom_read ( SN_STRING, 16, 10 );  // copy serial number
250
    }
251
    else {
252
        config_data_valid = 0;
253
    }
254
 
255
    for (b=0; b<10; b++) {       // abort if SN != "0000000000"
256
        if ( SN_STRING[b] != 48 )
257
            return;
258
    }
259
 
260
    mac_eeprom_read ( buf, 0xfb, 5 );   // read the last 5 MAC digits
261
 
262
    c=0;
263
    for (b=0; b<5; b++) {        // convert to MAC to SN string
264
        d = buf[b];
265
        SN_STRING[c] = hexdigits[d>>4];
266
        c++;
267
        SN_STRING[c] = hexdigits[d & 15];
268
        c++;
269
    }
270
}
271
#endif
272
 
273
 
274
/* *********************************************************************
275
   ***** init_USB ******************************************************
276
   ********************************************************************* */
277
#define[EPXCFG(][);][    EP$0CFG = 
278
#ifeq[EP$0_DIR][IN]
279
        bmBIT7 | bmBIT6
280
#elifeq[EP$0_DIR][OUT]
281
        bmBIT7
282
#else
283
 
284
#endif
285
#ifeq[EP$0_TYPE][BULK]
286
        | bmBIT5
287
#elifeq[EP$0_TYPE][ISO]
288
        | bmBIT4
289
#elifeq[EP$0_TYPE][INT]
290
        | bmBIT5 | bmBIT4
291
#endif
292
#ifeq[EP$0_SIZE][1024]
293
        | bmBIT3
294
#endif
295
#ifeq[EP$0_BUFFERS][2]
296
        | bmBIT1
297
#elifeq[EP$0_BUFFERS][3]
298
        | bmBIT1 | bmBIT0
299
#endif  
300
        ;
301
        SYNCDELAY;
302
]
303
 
304
#define[EP1XCFG(][);][#ifeq[EP$0_TYPE][BULK]
305
        EP$0CFG = bmBIT7 | bmBIT5;
306
#elifeq[EP$0_TYPE][ISO]
307
        EP$0CFG = bmBIT7 | bmBIT4;
308
#elifeq[EP$0_TYPE][INT]
309
        EP$0CFG = bmBIT7 | bmBIT5 | bmBIT4;
310
#else   
311
        EP$0CFG = 0;
312
#endif
313
        SYNCDELAY;
314
]
315
 
316
 
317
void init_USB ()
318
{
319
    USBCS |= bmBIT3;
320
 
321
    CPUCS = bmBIT4 | bmBIT1;
322
    wait(2);
323
    CKCON &= ~7;
324
 
325
#ifeq[PRODUCT_IS][UFM-1_0]
326
    IOA1 = 1;
327
    OEA |= bmBIT1;
328
#elifeq[PRODUCT_IS][UFM-1_1]
329
    IOA1 = 1;
330
    OEA |= bmBIT1;
331
#elifeq[PRODUCT_IS][UFM-1_2]
332
    IOA1 = 1;
333
    OEA |= bmBIT1;
334
#elifeq[PRODUCT_IS][UFM-1_10]
335
    IOA1 = 1;
336
    OEA |= bmBIT1;
337
#elifeq[PRODUCT_IS][UFM-1_11]
338
    IOA1 = 1;
339
    OEA |= bmBIT1;
340
#elifeq[PRODUCT_IS][UFM-1_15]
341
    IOA1 = 1;
342
    OEA |= bmBIT1;
343
#elifeq[PRODUCT_IS][UFM-1_15Y]
344
    init_fpga();
345
#elifeq[PRODUCT_IS][UFM-2_16]
346
    init_fpga();
347
#elifeq[PRODUCT_IS][UFM-2_13]
348
    init_fpga();
349
#endif
350
 
351
    INIT_CMDS;
352
 
353
    EA = 0;
354
    EUSB = 0;
355
 
356
    ENABLE_AVUSB;
357
 
358
    INIT_INTERRUPT_VECTOR(INTVEC_SUDAV, SUDAV_ISR);
359
    INIT_INTERRUPT_VECTOR(INTVEC_SOF, SOF_ISR);
360
    INIT_INTERRUPT_VECTOR(INTVEC_SUTOK, SUTOK_ISR);
361
    INIT_INTERRUPT_VECTOR(INTVEC_SUSPEND, SUSP_ISR);
362
    INIT_INTERRUPT_VECTOR(INTVEC_USBRESET, URES_ISR);
363
    INIT_INTERRUPT_VECTOR(INTVEC_HISPEED, HSGRANT_ISR);
364
    INIT_INTERRUPT_VECTOR(INTVEC_EP0ACK, EP0ACK_ISR);
365
 
366
    INIT_INTERRUPT_VECTOR(INTVEC_EP0IN, EP0IN_ISR);
367
    INIT_INTERRUPT_VECTOR(INTVEC_EP0OUT, EP0OUT_ISR);
368
    INIT_INTERRUPT_VECTOR(INTVEC_EP1IN, EP1IN_ISR);
369
    INIT_INTERRUPT_VECTOR(INTVEC_EP1OUT, EP1OUT_ISR);
370
    INIT_INTERRUPT_VECTOR(INTVEC_EP2, EP2_ISR);
371
    INIT_INTERRUPT_VECTOR(INTVEC_EP4, EP4_ISR);
372
    INIT_INTERRUPT_VECTOR(INTVEC_EP6, EP6_ISR);
373
    INIT_INTERRUPT_VECTOR(INTVEC_EP8, EP8_ISR);
374
 
375
    EXIF &= ~bmBIT4;
376
    USBIRQ = 0x7f;
377
    USBIE |= 0x7f;
378
    EPIRQ = 0xff;
379
    EPIE = 0xff;
380
 
381
    EUSB = 1;
382
    EA = 1;
383
 
384
    EP1XCFG(1IN);
385
    EP1XCFG(1OUT);
386
    EPXCFG(2);
387
    EPXCFG(4);
388
    EPXCFG(6);
389
    EPXCFG(8);
390
 
391
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
392
    OEA &= ~bmBIT3;
393
    if ( IOA3 ) {
394
        is_ufm_1_15x = 0;
395
    } else {
396
        is_ufm_1_15x = 1;
397
//      INTERFACE_CAPABILITIES[0] &= ~32;
398
    }
399
#endif    
400
 
401
#ifeq[FLASH_ENABLED][1]
402
    flash_init();
403
#endif
404
#ifeq[DEBUG_ENABLED][1]
405
    debug_init();
406
#endif
407
#ifeq[XMEGA_ENABLED][1]
408
    xmega_init();
409
#endif
410
#ifdef[@CAPABILITY_MAC_EEPROM;]
411
    mac_eeprom_init();
412
#endif
413
#ifeq[TEMP1_ENABLED][1]
414
    temp1_init();
415
#endif
416
#ifeq[FLASH_BITSTREAM_ENABLED][1]
417
    fpga_configure_from_flash_init();
418
#endif
419
 
420
    USBCS |= bmBIT7 | bmBIT1;
421
    wait(10);
422
//    wait(250);
423
    USBCS &= ~bmBIT3;
424
}
425
 
426
 
427
#endif   /* ZTEX_H */

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