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URL https://opencores.org/ocsvn/usb_ft232h_avalon-mm_interface/usb_ft232h_avalon-mm_interface/trunk

Subversion Repositories usb_ft232h_avalon-mm_interface

[/] [usb_ft232h_avalon-mm_interface/] [trunk/] [hw/] [usb_ft232h.sv] - Blame information for rev 2

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1 2 melman701 
/*
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 *      Если error срабатывает на последнем байте пакета, то он не будет отправлен, пока
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 * не придет следующий пакет
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 */
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`define WRDATA_ADDR             0
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`define RDDATA_ADDR             1
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`define TXSTATUSL_ADDR  2
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`define TXSTATUSH_ADDR  3
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`define RXSTATUSL_ADDR  4
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`define RXSTATUSH_ADDR  5
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module usb_ft232h (
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        //Avalon-MM Slave
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        clk,
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        reset,
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        address,
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        read,
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        readdata,
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        write,
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        writedata,
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        //FT232H
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        usb_clk,
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        usb_data,
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        usb_rxf_n,
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        usb_txe_n,
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        usb_rd_n,
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        usb_wr_n,
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        usb_oe_n
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);
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parameter FIFO_DEPTH = 512;
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parameter FIFO_WIDTHU = 9;
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input logic clk;
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input logic reset;
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input logic [3:0]address;
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input logic read;
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output logic [7:0]readdata;
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input logic write;
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input logic [7:0]writedata;
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input logic usb_clk;
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inout logic [7:0]usb_data;
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input logic usb_rxf_n;
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input logic usb_txe_n;
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output logic usb_rd_n;
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output logic usb_wr_n;
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output logic usb_oe_n;
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logic [15:0]txstatus;
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logic [15:0]rxstatus;
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logic [3:0]addr;
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reg reg_usb_rd_n;
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reg reg_usb_oe_n;
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reg reg_usb_wr_n;
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reg reg_rxf_wrreq;
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reg reg_txf_rdreq;
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reg error;
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logic [7:0]txf_wrdata;
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logic txf_wrclk;
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logic txf_wrreq;
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logic txf_wrfull;
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logic [FIFO_WIDTHU-1:0]txf_wrusedw;
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logic txf_rdclk;
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logic txf_rdreq;
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logic [7:0]txf_rddata;
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logic txf_rdempty;
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logic [7:0]rxf_wrdata;
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logic rxf_wrclk;
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logic rxf_wrreq;
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logic rxf_wrfull;
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logic [FIFO_WIDTHU-1:0]rxf_rdusedw;
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logic rxf_rdclk;
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logic rxf_rdreq;
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logic [7:0]rxf_rddata;
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logic rxf_rdempty;
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logic rxf_rdfull;
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87 
 
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assign usb_data = usb_oe_n ? txf_rddata : {8{1'bZ}};
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assign rxf_wrdata = usb_oe_n ? 8'b0 : usb_data;
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assign usb_oe_n = (~usb_rxf_n & ~rxf_wrfull) ? reg_usb_oe_n : 1'b1;
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assign usb_rd_n = (~usb_rxf_n & ~rxf_wrfull) ? reg_usb_rd_n : 1'b1;
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assign usb_wr_n = (usb_oe_n & ~usb_txe_n) ? reg_usb_wr_n : 1'b1;
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assign rxf_wrreq = (~usb_rxf_n & ~rxf_wrfull) ? reg_rxf_wrreq : 1'b0;
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assign txf_rdreq = (reg_txf_rdreq & (~error));
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assign txstatus[15] = ~txf_wrfull; //can write
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assign txstatus[14:FIFO_WIDTHU+1] = 0;
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assign txstatus[FIFO_WIDTHU] = txf_wrfull;
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assign txstatus[FIFO_WIDTHU-1:0] = txf_wrusedw;
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assign rxstatus[15] = ~rxf_rdempty; //can read
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assign rxstatus[14:FIFO_WIDTHU+1] = 0;
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assign rxstatus[FIFO_WIDTHU] = rxf_rdfull;
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assign rxstatus[FIFO_WIDTHU-1:0] = rxf_rdusedw;
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assign txf_wrclk = ~clk;
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assign txf_wrreq = (~txf_wrfull & (address == `WRDATA_ADDR)) ? write : 0;
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assign txf_wrdata = writedata;
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assign txf_rdclk = usb_clk;
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113 
assign rxf_wrclk = usb_clk;
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assign rxf_rdclk = ~clk;
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assign rxf_rdreq = (address == `RDDATA_ADDR) ? read : 0;
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117 
 
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dcfifo  txfifo (
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                                .aclr (reset),
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                                .data (txf_wrdata),
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                                .rdclk (txf_rdclk),
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                                .rdreq (txf_rdreq),
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                                .wrclk (txf_wrclk),
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                                .wrreq (txf_wrreq),
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                                .q (txf_rddata),
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                                .rdempty (txf_rdempty),
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                                .wrfull (txf_wrfull),
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                                .wrusedw (txf_wrusedw),
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                                .eccstatus (),
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                                .rdfull (),
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                                .rdusedw (),
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                                .wrempty ());
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        defparam
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                txfifo.intended_device_family = "Cyclone IV E",
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                txfifo.lpm_numwords = FIFO_DEPTH,
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                txfifo.lpm_showahead = "OFF",
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                txfifo.lpm_type = "dcfifo",
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                txfifo.lpm_width = 8,
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                txfifo.lpm_widthu = FIFO_WIDTHU,
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                txfifo.overflow_checking = "ON",
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                txfifo.rdsync_delaypipe = 4,
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                txfifo.read_aclr_synch = "OFF",
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                txfifo.underflow_checking = "ON",
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                txfifo.use_eab = "ON",
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                txfifo.write_aclr_synch = "OFF",
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                txfifo.wrsync_delaypipe = 4;
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dcfifo  rxfifo (
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                                .aclr (reset),
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                                .data (rxf_wrdata),
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                                .rdclk (rxf_rdclk),
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                                .rdreq (rxf_rdreq),
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                                .wrclk (rxf_wrclk),
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                                .wrreq (rxf_wrreq),
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                                .q (rxf_rddata),
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                                .rdempty (rxf_rdempty),
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                                .wrfull (rxf_wrfull),
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                                .wrusedw (),
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                                .eccstatus (),
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                                .rdfull (rxf_rdfull),
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                                .rdusedw (rxf_rdusedw),
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                                .wrempty ());
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        defparam
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                rxfifo.intended_device_family = "Cyclone IV E",
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                rxfifo.lpm_numwords = FIFO_DEPTH,
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                rxfifo.lpm_showahead = "OFF",
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                rxfifo.lpm_type = "dcfifo",
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                rxfifo.lpm_width = 8,
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                rxfifo.lpm_widthu = FIFO_WIDTHU,
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                rxfifo.overflow_checking = "ON",
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                rxfifo.rdsync_delaypipe = 4,
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                rxfifo.read_aclr_synch = "OFF",
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                rxfifo.underflow_checking = "ON",
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                rxfifo.use_eab = "ON",
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                rxfifo.write_aclr_synch = "OFF",
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                rxfifo.wrsync_delaypipe = 4;
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always_ff @(negedge clk)
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begin
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        if(read)
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                addr <= address;
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end
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always_ff @(posedge clk)
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begin
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                case(addr)
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                `RDDATA_ADDR: begin
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                        readdata <= rxf_rddata;
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                end
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                `TXSTATUSL_ADDR: begin
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                        readdata <= txstatus[7:0];
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                end
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                `TXSTATUSH_ADDR: begin
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                        readdata <= txstatus[15:8];
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                end
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                `RXSTATUSL_ADDR: begin
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                        readdata <= rxstatus[7:0];
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                end
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                `RXSTATUSH_ADDR: begin
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                        readdata <= rxstatus[15:8];
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                end
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                default: begin
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                        readdata <= 8'b0;
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                end
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                endcase
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end
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always_ff @(negedge txf_rdclk or posedge reset)
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begin
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        if(reset)
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        begin
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                reg_txf_rdreq <= 1'b0;
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                error <= 1'b0;
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        end
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        else
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        begin
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                if(usb_oe_n & (~txf_rdempty | error) & ~usb_txe_n)
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                begin
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                        reg_txf_rdreq <= 1'b1;
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                end
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                else
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                begin
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                        reg_txf_rdreq <= 1'b0;
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                end
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                if(reg_txf_rdreq)
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                begin
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                        if(usb_txe_n)
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                                error <= 1'b1;
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                        else
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                                error <= 1'b0;
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                end
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        end
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end
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always_ff @(posedge usb_clk or posedge reset)
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begin
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        if(reset)
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        begin
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                reg_usb_wr_n <= 1'b1;
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        end
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        else
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        begin
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                if(reg_txf_rdreq)
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                begin
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                        reg_usb_wr_n <= 1'b0;
251 
                end
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                else
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                        reg_usb_wr_n <= 1'b1;
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        end
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end
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always_ff @(posedge usb_clk or posedge reset)
258 
begin
259 
        if(reset)
260 
        begin
261 
                reg_usb_rd_n <= 1'b1;
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                reg_usb_oe_n <= 1'b1;
263 
        end
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        else
265 
        begin
266 
                if((txf_rdempty | usb_txe_n | ~usb_oe_n) & ~rxf_wrfull & ~usb_rxf_n)
267 
                begin
268 
                        reg_usb_oe_n <= 1'b0;
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                        if(~reg_usb_oe_n)
270 
                        begin
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                                reg_usb_rd_n <= 1'b0;
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                        end
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                        else
274 
                        begin
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                                reg_usb_rd_n <= 1'b1;
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                        end
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                end
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                else
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                begin
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                        reg_usb_oe_n <= 1'b1;
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                        reg_usb_rd_n <= 1'b1;
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                end
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        end
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end
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always_ff @(negedge rxf_wrclk or posedge reset)
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begin
288 
        if(reset)
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        begin
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                reg_rxf_wrreq <= 1'b0;
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        end
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        else
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        begin
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                if(~usb_rd_n & ~usb_rxf_n)
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                        reg_rxf_wrreq <= 1'b1;
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                else
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                        reg_rxf_wrreq <= 1'b0;
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        end
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end
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endmodule

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