URL https://opencores.org/ocsvn/usimplez/usimplez/trunk

Subversion Repositories usimplez

[/] [usimplez/] [trunk/] [QuartusII/] [db/] [usimplez_top.hif] - Blame information for rev 3

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Quartus II
Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
7
3700
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
 
 
VRSM_ON
VHSM_ON
 
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
usimplez_top
# storage
db|usimplez_top.(0).cnf
db|usimplez_top.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
usimplez_top.vhd
fd40d3f9720444f4e8c377ddd731d8
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
WIDTH_WORD
12
PARAMETER_SIGNED_DEC
DEF
WIDTH_ADDRESS
9
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
|
}
# lmf
|altera|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence
 
# end
# entity
altsyncram
# storage
db|usimplez_top.(3).cnf
db|usimplez_top.(3).cnf
# case_insensitive
# source_file
|altera|quartus|libraries|megafunctions|altsyncram.tdf
67d9a3902c8a461c1d5750189e124f2
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
SINGLE_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
12
PARAMETER_UNKNOWN
USR
WIDTHAD_A
9
PARAMETER_UNKNOWN
USR
NUMWORDS_A
512
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
fibonacci.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
 
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_im61
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence
 
# end
# entity
altsyncram_im61
# storage
db|usimplez_top.(4).cnf
db|usimplez_top.(4).cnf
# case_insensitive
# source_file
db|altsyncram_im61.tdf
15b372adebb3e965fe4fdfacc8eb62b0
7
# used_port {
wren_a
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
fibonacci.mif
44e8ed8bcde6c33480b853c940c61d96
}
# macro_sequence
 
# end
# entity
altsyncram
# storage
db|usimplez_top.(5).cnf
db|usimplez_top.(5).cnf
# case_insensitive
# source_file
|altera|quartus|libraries|megafunctions|altsyncram.tdf
67d9a3902c8a461c1d5750189e124f2
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
SINGLE_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
12
PARAMETER_UNKNOWN
USR
WIDTHAD_A
9
PARAMETER_UNKNOWN
USR
NUMWORDS_A
512
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
adder.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
 
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_k961
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence
 
# end
# entity
altsyncram_k961
# storage
db|usimplez_top.(6).cnf
db|usimplez_top.(6).cnf
# case_insensitive
# source_file
db|altsyncram_k961.tdf
18e0b15b558b40691524381eaa9f467
7
# used_port {
wren_a
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
adder.mif
bb8d3b979b75eab27c7eb9bd52dd54a
}
# macro_sequence
 
# end
# entity
usimplez_cpu
# storage
db|usimplez_top.(1).cnf
db|usimplez_top.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
usimplez_cpu.vhd
ad52f891b788a95c143c0e372a9bc6b
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
width_word
12
PARAMETER_SIGNED_DEC
USR
width_operation_code
3
PARAMETER_SIGNED_DEC
USR
width_address
9
PARAMETER_SIGNED_DEC
USR
st
000
PARAMETER_UNSIGNED_BIN
USR
ld
001
PARAMETER_UNSIGNED_BIN
USR
add
010
PARAMETER_UNSIGNED_BIN
USR
br
011
PARAMETER_UNSIGNED_BIN
USR
bz
100
PARAMETER_UNSIGNED_BIN
USR
clr
101
PARAMETER_UNSIGNED_BIN
USR
dec
110
PARAMETER_UNSIGNED_BIN
USR
halt
111
PARAMETER_UNSIGNED_BIN
USR
 constraint(st)
 
PARAMETER_STRING
USR
 constraint(ld)
 
PARAMETER_STRING
USR
 constraint(add)
 
PARAMETER_STRING
USR
 constraint(br)
 
PARAMETER_STRING
USR
 constraint(bz)
 
PARAMETER_STRING
USR
 constraint(clr)
 
PARAMETER_STRING
USR
 constraint(dec)
 
PARAMETER_STRING
USR
 constraint(halt)
 
PARAMETER_STRING
USR
 constraint(data_bus_i)
11 downto 0
PARAMETER_STRING
USR
 constraint(data_bus_o)
11 downto 0
PARAMETER_STRING
USR
 constraint(addr_bus_o)
8 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
usimplez_cpu:cpu
}
# lmf
|altera|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence
 
# end
# entity
usimplez_ram
# storage
db|usimplez_top.(2).cnf
db|usimplez_top.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
usimplez_ram.vhd
c21bed544a534d01c38852e7cf9346b
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
width_word
12
PARAMETER_SIGNED_DEC
USR
width_address
9
PARAMETER_SIGNED_DEC
USR
 constraint(addr_i)
8 downto 0
PARAMETER_STRING
USR
 constraint(data_i)
11 downto 0
PARAMETER_STRING
USR
 constraint(data_o)
11 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
usimplez_ram:ram
}
# lmf
|altera|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence
 
# end
# complete
 

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Subversion Repositories usimplez

[/] [usimplez/] [trunk/] [QuartusII/] [db/] [usimplez_top.hif] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	pas.	`Quartus II`
2			`Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition`
3			`7`
4			`3700`
5			`OFF`
6			`OFF`
7			`OFF`
8			`ON`
9			`ON`
10			`ON`
11			`FV_OFF`
12			`Level2`
13
14
15			`VRSM_ON`
16			`VHSM_ON`
17
18			`-- Start Library Paths --`
19			`-- End Library Paths --`
20			`-- Start VHDL Libraries --`
21			`-- End VHDL Libraries --`
22			`# entity`
23			`usimplez_top`
24			`# storage`
25			`db\|usimplez_top.(0).cnf`
26			`db\|usimplez_top.(0).cnf`
27			`# logic_option {`
28			`AUTO_RAM_RECOGNITION`
29			`ON`
30			`}`
31			`# case_insensitive`
32			`# source_file`
33			`usimplez_top.vhd`
34			`fd40d3f9720444f4e8c377ddd731d8`
35			`5`
36			`# internal_option {`
37			`HDL_INITIAL_FANOUT_LIMIT`
38			`OFF`
39			`AUTO_RESOURCE_SHARING`
40			`OFF`
41			`AUTO_RAM_RECOGNITION`
42			`ON`
43			`AUTO_ROM_RECOGNITION`
44			`ON`
45			`}`
46			`# user_parameter {`
47			`WIDTH_WORD`
48			`12`
49			`PARAMETER_SIGNED_DEC`
50			`DEF`
51			`WIDTH_ADDRESS`
52			`9`
53			`PARAMETER_SIGNED_DEC`
54			`DEF`
55			`}`
56			`# hierarchies {`
57			`\|`
58			`}`
59			`# lmf`
60			`\|altera\|quartus\|lmf\|maxplus2.lmf`
61			`a36c8ec425c8a2589af98b2d4daabc3`
62			`# macro_sequence`
63
64			`# end`
65			`# entity`
66			`altsyncram`
67			`# storage`
68			`db\|usimplez_top.(3).cnf`
69			`db\|usimplez_top.(3).cnf`
70			`# case_insensitive`
71			`# source_file`
72			`\|altera\|quartus\|libraries\|megafunctions\|altsyncram.tdf`
73			`67d9a3902c8a461c1d5750189e124f2`
74			`7`
75			`# user_parameter {`
76			`BYTE_SIZE_BLOCK`
77			`8`
78			`PARAMETER_UNKNOWN`
79			`DEF`
80			`AUTO_CARRY_CHAINS`
81			`ON`
82			`AUTO_CARRY`
83			`USR`
84			`IGNORE_CARRY_BUFFERS`
85			`OFF`
86			`IGNORE_CARRY`
87			`USR`
88			`AUTO_CASCADE_CHAINS`
89			`ON`
90			`AUTO_CASCADE`
91			`USR`
92			`IGNORE_CASCADE_BUFFERS`
93			`OFF`
94			`IGNORE_CASCADE`
95			`USR`
96			`WIDTH_BYTEENA`
97			`1`
98			`PARAMETER_UNKNOWN`
99			`DEF`
100			`OPERATION_MODE`
101			`SINGLE_PORT`
102			`PARAMETER_UNKNOWN`
103			`USR`
104			`WIDTH_A`
105			`12`
106			`PARAMETER_UNKNOWN`
107			`USR`
108			`WIDTHAD_A`
109			`9`
110			`PARAMETER_UNKNOWN`
111			`USR`
112			`NUMWORDS_A`
113			`512`
114			`PARAMETER_UNKNOWN`
115			`USR`
116			`OUTDATA_REG_A`
117			`UNREGISTERED`
118			`PARAMETER_UNKNOWN`
119			`USR`
120			`ADDRESS_ACLR_A`
121			`NONE`
122			`PARAMETER_UNKNOWN`
123			`USR`
124			`OUTDATA_ACLR_A`
125			`NONE`
126			`PARAMETER_UNKNOWN`
127			`USR`
128			`WRCONTROL_ACLR_A`
129			`NONE`
130			`PARAMETER_UNKNOWN`
131			`USR`
132			`INDATA_ACLR_A`
133			`NONE`
134			`PARAMETER_UNKNOWN`
135			`USR`
136			`BYTEENA_ACLR_A`
137			`NONE`
138			`PARAMETER_UNKNOWN`
139			`DEF`
140			`WIDTH_B`
141			`1`
142			`PARAMETER_UNKNOWN`
143			`DEF`
144			`WIDTHAD_B`
145			`1`
146			`PARAMETER_UNKNOWN`
147			`DEF`
148			`NUMWORDS_B`
149			`1`
150			`PARAMETER_UNKNOWN`
151			`DEF`
152			`INDATA_REG_B`
153			`CLOCK1`
154			`PARAMETER_UNKNOWN`
155			`DEF`
156			`WRCONTROL_WRADDRESS_REG_B`
157			`CLOCK1`
158			`PARAMETER_UNKNOWN`
159			`DEF`
160			`RDCONTROL_REG_B`
161			`CLOCK1`
162			`PARAMETER_UNKNOWN`
163			`DEF`
164			`ADDRESS_REG_B`
165			`CLOCK1`
166			`PARAMETER_UNKNOWN`
167			`DEF`
168			`OUTDATA_REG_B`
169			`UNREGISTERED`
170			`PARAMETER_UNKNOWN`
171			`DEF`
172			`BYTEENA_REG_B`
173			`CLOCK1`
174			`PARAMETER_UNKNOWN`
175			`DEF`
176			`INDATA_ACLR_B`
177			`NONE`
178			`PARAMETER_UNKNOWN`
179			`DEF`
180			`WRCONTROL_ACLR_B`
181			`NONE`
182			`PARAMETER_UNKNOWN`
183			`DEF`
184			`ADDRESS_ACLR_B`
185			`NONE`
186			`PARAMETER_UNKNOWN`
187			`DEF`
188			`OUTDATA_ACLR_B`
189			`NONE`
190			`PARAMETER_UNKNOWN`
191			`DEF`
192			`RDCONTROL_ACLR_B`
193			`NONE`
194			`PARAMETER_UNKNOWN`
195			`DEF`
196			`BYTEENA_ACLR_B`
197			`NONE`
198			`PARAMETER_UNKNOWN`
199			`DEF`
200			`WIDTH_BYTEENA_A`
201			`1`
202			`PARAMETER_UNKNOWN`
203			`DEF`
204			`WIDTH_BYTEENA_B`
205			`1`
206			`PARAMETER_UNKNOWN`
207			`DEF`
208			`RAM_BLOCK_TYPE`
209			`AUTO`
210			`PARAMETER_UNKNOWN`
211			`DEF`
212			`BYTE_SIZE`
213			`8`
214			`PARAMETER_UNKNOWN`
215			`DEF`
216			`READ_DURING_WRITE_MODE_MIXED_PORTS`
217			`DONT_CARE`
218			`PARAMETER_UNKNOWN`
219			`DEF`
220			`READ_DURING_WRITE_MODE_PORT_A`
221			`NEW_DATA_NO_NBE_READ`
222			`PARAMETER_UNKNOWN`
223			`DEF`
224			`READ_DURING_WRITE_MODE_PORT_B`
225			`NEW_DATA_NO_NBE_READ`
226			`PARAMETER_UNKNOWN`
227			`DEF`
228			`INIT_FILE`
229			`fibonacci.mif`
230			`PARAMETER_UNKNOWN`
231			`USR`
232			`INIT_FILE_LAYOUT`
233			`PORT_A`
234			`PARAMETER_UNKNOWN`
235			`DEF`
236			`MAXIMUM_DEPTH`
237
238			`PARAMETER_UNKNOWN`
239			`DEF`
240			`CLOCK_ENABLE_INPUT_A`
241			`NORMAL`
242			`PARAMETER_UNKNOWN`
243			`DEF`
244			`CLOCK_ENABLE_INPUT_B`
245			`NORMAL`
246			`PARAMETER_UNKNOWN`
247			`DEF`
248			`CLOCK_ENABLE_OUTPUT_A`
249			`NORMAL`
250			`PARAMETER_UNKNOWN`
251			`DEF`
252			`CLOCK_ENABLE_OUTPUT_B`
253			`NORMAL`
254			`PARAMETER_UNKNOWN`
255			`DEF`
256			`CLOCK_ENABLE_CORE_A`
257			`USE_INPUT_CLKEN`
258			`PARAMETER_UNKNOWN`
259			`DEF`
260			`CLOCK_ENABLE_CORE_B`
261			`USE_INPUT_CLKEN`
262			`PARAMETER_UNKNOWN`
263			`DEF`
264			`ENABLE_ECC`
265			`FALSE`
266			`PARAMETER_UNKNOWN`
267			`DEF`
268			`DEVICE_FAMILY`
269			`Stratix II`
270			`PARAMETER_UNKNOWN`
271			`USR`
272			`CBXI_PARAMETER`
273			`altsyncram_im61`
274			`PARAMETER_UNKNOWN`
275			`USR`
276			`}`
277			`# used_port {`
278			`wren_a`
279			`-1`
280			`3`
281			`q_a9`
282			`-1`
283			`3`
284			`q_a8`
285			`-1`
286			`3`
287			`q_a7`
288			`-1`
289			`3`
290			`q_a6`
291			`-1`
292			`3`
293			`q_a5`
294			`-1`
295			`3`
296			`q_a4`
297			`-1`
298			`3`
299			`q_a3`
300			`-1`
301			`3`
302			`q_a2`
303			`-1`
304			`3`
305			`q_a11`
306			`-1`
307			`3`
308			`q_a10`
309			`-1`
310			`3`
311			`q_a1`
312			`-1`
313			`3`
314			`q_a0`
315			`-1`
316			`3`
317			`data_a9`
318			`-1`
319			`3`
320			`data_a8`
321			`-1`
322			`3`
323			`data_a7`
324			`-1`
325			`3`
326			`data_a6`
327			`-1`
328			`3`
329			`data_a5`
330			`-1`
331			`3`
332			`data_a4`
333			`-1`
334			`3`
335			`data_a3`
336			`-1`
337			`3`
338			`data_a2`
339			`-1`
340			`3`
341			`data_a11`
342			`-1`
343			`3`
344			`data_a10`
345			`-1`
346			`3`
347			`data_a1`
348			`-1`
349			`3`
350			`data_a0`
351			`-1`
352			`3`
353			`clock0`
354			`-1`
355			`3`
356			`address_a8`
357			`-1`
358			`3`
359			`address_a7`
360			`-1`
361			`3`
362			`address_a6`
363			`-1`
364			`3`
365			`address_a5`
366			`-1`
367			`3`
368			`address_a4`
369			`-1`
370			`3`
371			`address_a3`
372			`-1`
373			`3`
374			`address_a2`
375			`-1`
376			`3`
377			`address_a1`
378			`-1`
379			`3`
380			`address_a0`
381			`-1`
382			`3`
383			`}`
384			`# macro_sequence`
385
386			`# end`
387			`# entity`
388			`altsyncram_im61`
389			`# storage`
390			`db\|usimplez_top.(4).cnf`
391			`db\|usimplez_top.(4).cnf`
392			`# case_insensitive`
393			`# source_file`
394			`db\|altsyncram_im61.tdf`
395			`15b372adebb3e965fe4fdfacc8eb62b0`
396			`7`
397			`# used_port {`
398			`wren_a`
399			`-1`
400			`3`
401			`q_a9`
402			`-1`
403			`3`
404			`q_a8`
405			`-1`
406			`3`
407			`q_a7`
408			`-1`
409			`3`
410			`q_a6`
411			`-1`
412			`3`
413			`q_a5`
414			`-1`
415			`3`
416			`q_a4`
417			`-1`
418			`3`
419			`q_a3`
420			`-1`
421			`3`
422			`q_a2`
423			`-1`
424			`3`
425			`q_a11`
426			`-1`
427			`3`
428			`q_a10`
429			`-1`
430			`3`
431			`q_a1`
432			`-1`
433			`3`
434			`q_a0`
435			`-1`
436			`3`
437			`data_a9`
438			`-1`
439			`3`
440			`data_a8`
441			`-1`
442			`3`
443			`data_a7`
444			`-1`
445			`3`
446			`data_a6`
447			`-1`
448			`3`
449			`data_a5`
450			`-1`
451			`3`
452			`data_a4`
453			`-1`
454			`3`
455			`data_a3`
456			`-1`
457			`3`
458			`data_a2`
459			`-1`
460			`3`
461			`data_a11`
462			`-1`
463			`3`
464			`data_a10`
465			`-1`
466			`3`
467			`data_a1`
468			`-1`
469			`3`
470			`data_a0`
471			`-1`
472			`3`
473			`clock0`
474			`-1`
475			`3`
476			`address_a8`
477			`-1`
478			`3`
479			`address_a7`
480			`-1`
481			`3`
482			`address_a6`
483			`-1`
484			`3`
485			`address_a5`
486			`-1`
487			`3`
488			`address_a4`
489			`-1`
490			`3`
491			`address_a3`
492			`-1`
493			`3`
494			`address_a2`
495			`-1`
496			`3`
497			`address_a1`
498			`-1`
499			`3`
500			`address_a0`
501			`-1`
502			`3`
503			`}`
504			`# memory_file {`
505			`fibonacci.mif`
506			`44e8ed8bcde6c33480b853c940c61d96`
507			`}`
508			`# macro_sequence`
509
510			`# end`
511			`# entity`
512			`altsyncram`
513			`# storage`
514			`db\|usimplez_top.(5).cnf`
515			`db\|usimplez_top.(5).cnf`
516			`# case_insensitive`
517			`# source_file`
518			`\|altera\|quartus\|libraries\|megafunctions\|altsyncram.tdf`
519			`67d9a3902c8a461c1d5750189e124f2`
520			`7`
521			`# user_parameter {`
522			`BYTE_SIZE_BLOCK`
523			`8`
524			`PARAMETER_UNKNOWN`
525			`DEF`
526			`AUTO_CARRY_CHAINS`
527			`ON`
528			`AUTO_CARRY`
529			`USR`
530			`IGNORE_CARRY_BUFFERS`
531			`OFF`
532			`IGNORE_CARRY`
533			`USR`
534			`AUTO_CASCADE_CHAINS`
535			`ON`
536			`AUTO_CASCADE`
537			`USR`
538			`IGNORE_CASCADE_BUFFERS`
539			`OFF`
540			`IGNORE_CASCADE`
541			`USR`
542			`WIDTH_BYTEENA`
543			`1`
544			`PARAMETER_UNKNOWN`
545			`DEF`
546			`OPERATION_MODE`
547			`SINGLE_PORT`
548			`PARAMETER_UNKNOWN`
549			`USR`
550			`WIDTH_A`
551			`12`
552			`PARAMETER_UNKNOWN`
553			`USR`
554			`WIDTHAD_A`
555			`9`
556			`PARAMETER_UNKNOWN`
557			`USR`
558			`NUMWORDS_A`
559			`512`
560			`PARAMETER_UNKNOWN`
561			`USR`
562			`OUTDATA_REG_A`
563			`UNREGISTERED`
564			`PARAMETER_UNKNOWN`
565			`USR`
566			`ADDRESS_ACLR_A`
567			`NONE`
568			`PARAMETER_UNKNOWN`
569			`USR`
570			`OUTDATA_ACLR_A`
571			`NONE`
572			`PARAMETER_UNKNOWN`
573			`USR`
574			`WRCONTROL_ACLR_A`
575			`NONE`
576			`PARAMETER_UNKNOWN`
577			`USR`
578			`INDATA_ACLR_A`
579			`NONE`
580			`PARAMETER_UNKNOWN`
581			`USR`
582			`BYTEENA_ACLR_A`
583			`NONE`
584			`PARAMETER_UNKNOWN`
585			`DEF`
586			`WIDTH_B`
587			`1`
588			`PARAMETER_UNKNOWN`
589			`DEF`
590			`WIDTHAD_B`
591			`1`
592			`PARAMETER_UNKNOWN`
593			`DEF`
594			`NUMWORDS_B`
595			`1`
596			`PARAMETER_UNKNOWN`
597			`DEF`
598			`INDATA_REG_B`
599			`CLOCK1`
600			`PARAMETER_UNKNOWN`
601			`DEF`
602			`WRCONTROL_WRADDRESS_REG_B`
603			`CLOCK1`
604			`PARAMETER_UNKNOWN`
605			`DEF`
606			`RDCONTROL_REG_B`
607			`CLOCK1`
608			`PARAMETER_UNKNOWN`
609			`DEF`
610			`ADDRESS_REG_B`
611			`CLOCK1`
612			`PARAMETER_UNKNOWN`
613			`DEF`
614			`OUTDATA_REG_B`
615			`UNREGISTERED`
616			`PARAMETER_UNKNOWN`
617			`DEF`
618			`BYTEENA_REG_B`
619			`CLOCK1`
620			`PARAMETER_UNKNOWN`
621			`DEF`
622			`INDATA_ACLR_B`
623			`NONE`
624			`PARAMETER_UNKNOWN`
625			`DEF`
626			`WRCONTROL_ACLR_B`
627			`NONE`
628			`PARAMETER_UNKNOWN`
629			`DEF`
630			`ADDRESS_ACLR_B`
631			`NONE`
632			`PARAMETER_UNKNOWN`
633			`DEF`
634			`OUTDATA_ACLR_B`
635			`NONE`
636			`PARAMETER_UNKNOWN`
637			`DEF`
638			`RDCONTROL_ACLR_B`
639			`NONE`
640			`PARAMETER_UNKNOWN`
641			`DEF`
642			`BYTEENA_ACLR_B`
643			`NONE`
644			`PARAMETER_UNKNOWN`
645			`DEF`
646			`WIDTH_BYTEENA_A`
647			`1`
648			`PARAMETER_UNKNOWN`
649			`DEF`
650			`WIDTH_BYTEENA_B`
651			`1`
652			`PARAMETER_UNKNOWN`
653			`DEF`
654			`RAM_BLOCK_TYPE`
655			`AUTO`
656			`PARAMETER_UNKNOWN`
657			`DEF`
658			`BYTE_SIZE`
659			`8`
660			`PARAMETER_UNKNOWN`
661			`DEF`
662			`READ_DURING_WRITE_MODE_MIXED_PORTS`
663			`DONT_CARE`
664			`PARAMETER_UNKNOWN`
665			`DEF`
666			`READ_DURING_WRITE_MODE_PORT_A`
667			`NEW_DATA_NO_NBE_READ`
668			`PARAMETER_UNKNOWN`
669			`DEF`
670			`READ_DURING_WRITE_MODE_PORT_B`
671			`NEW_DATA_NO_NBE_READ`
672			`PARAMETER_UNKNOWN`
673			`DEF`
674			`INIT_FILE`
675			`adder.mif`
676			`PARAMETER_UNKNOWN`
677			`USR`
678			`INIT_FILE_LAYOUT`
679			`PORT_A`
680			`PARAMETER_UNKNOWN`
681			`DEF`
682			`MAXIMUM_DEPTH`
683
684			`PARAMETER_UNKNOWN`
685			`DEF`
686			`CLOCK_ENABLE_INPUT_A`
687			`NORMAL`
688			`PARAMETER_UNKNOWN`
689			`DEF`
690			`CLOCK_ENABLE_INPUT_B`
691			`NORMAL`
692			`PARAMETER_UNKNOWN`
693			`DEF`
694			`CLOCK_ENABLE_OUTPUT_A`
695			`NORMAL`
696			`PARAMETER_UNKNOWN`
697			`DEF`
698			`CLOCK_ENABLE_OUTPUT_B`
699			`NORMAL`
700			`PARAMETER_UNKNOWN`
701			`DEF`
702			`CLOCK_ENABLE_CORE_A`
703			`USE_INPUT_CLKEN`
704			`PARAMETER_UNKNOWN`
705			`DEF`
706			`CLOCK_ENABLE_CORE_B`
707			`USE_INPUT_CLKEN`
708			`PARAMETER_UNKNOWN`
709			`DEF`
710			`ENABLE_ECC`
711			`FALSE`
712			`PARAMETER_UNKNOWN`
713			`DEF`
714			`DEVICE_FAMILY`
715			`Stratix II`
716			`PARAMETER_UNKNOWN`
717			`USR`
718			`CBXI_PARAMETER`
719			`altsyncram_k961`
720			`PARAMETER_UNKNOWN`
721			`USR`
722			`}`
723			`# used_port {`
724			`wren_a`
725			`-1`
726			`3`
727			`q_a9`
728			`-1`
729			`3`
730			`q_a8`
731			`-1`
732			`3`
733			`q_a7`
734			`-1`
735			`3`
736			`q_a6`
737			`-1`
738			`3`
739			`q_a5`
740			`-1`
741			`3`
742			`q_a4`
743			`-1`
744			`3`
745			`q_a3`
746			`-1`
747			`3`
748			`q_a2`
749			`-1`
750			`3`
751			`q_a11`
752			`-1`
753			`3`
754			`q_a10`
755			`-1`
756			`3`
757			`q_a1`
758			`-1`
759			`3`
760			`q_a0`
761			`-1`
762			`3`
763			`data_a9`
764			`-1`
765			`3`
766			`data_a8`
767			`-1`
768			`3`
769			`data_a7`
770			`-1`
771			`3`
772			`data_a6`
773			`-1`
774			`3`
775			`data_a5`
776			`-1`
777			`3`
778			`data_a4`
779			`-1`
780			`3`
781			`data_a3`
782			`-1`
783			`3`
784			`data_a2`
785			`-1`
786			`3`
787			`data_a11`
788			`-1`
789			`3`
790			`data_a10`
791			`-1`
792			`3`
793			`data_a1`
794			`-1`
795			`3`
796			`data_a0`
797			`-1`
798			`3`
799			`clock0`
800			`-1`
801			`3`
802			`address_a8`
803			`-1`
804			`3`
805			`address_a7`
806			`-1`
807			`3`
808			`address_a6`
809			`-1`
810			`3`
811			`address_a5`
812			`-1`
813			`3`
814			`address_a4`
815			`-1`
816			`3`
817			`address_a3`
818			`-1`
819			`3`
820			`address_a2`
821			`-1`
822			`3`
823			`address_a1`
824			`-1`
825			`3`
826			`address_a0`
827			`-1`
828			`3`
829			`}`
830			`# macro_sequence`
831
832			`# end`
833			`# entity`
834			`altsyncram_k961`
835			`# storage`
836			`db\|usimplez_top.(6).cnf`
837			`db\|usimplez_top.(6).cnf`
838			`# case_insensitive`
839			`# source_file`
840			`db\|altsyncram_k961.tdf`
841			`18e0b15b558b40691524381eaa9f467`
842			`7`
843			`# used_port {`
844			`wren_a`
845			`-1`
846			`3`
847			`q_a9`
848			`-1`
849			`3`
850			`q_a8`
851			`-1`
852			`3`
853			`q_a7`
854			`-1`
855			`3`
856			`q_a6`
857			`-1`
858			`3`
859			`q_a5`
860			`-1`
861			`3`
862			`q_a4`
863			`-1`
864			`3`
865			`q_a3`
866			`-1`
867			`3`
868			`q_a2`
869			`-1`
870			`3`
871			`q_a11`
872			`-1`
873			`3`
874			`q_a10`
875			`-1`
876			`3`
877			`q_a1`
878			`-1`
879			`3`
880			`q_a0`
881			`-1`
882			`3`
883			`data_a9`
884			`-1`
885			`3`
886			`data_a8`
887			`-1`
888			`3`
889			`data_a7`
890			`-1`
891			`3`
892			`data_a6`
893			`-1`
894			`3`
895			`data_a5`
896			`-1`
897			`3`
898			`data_a4`
899			`-1`
900			`3`
901			`data_a3`
902			`-1`
903			`3`
904			`data_a2`
905			`-1`
906			`3`
907			`data_a11`
908			`-1`
909			`3`
910			`data_a10`
911			`-1`
912			`3`
913			`data_a1`
914			`-1`
915			`3`
916			`data_a0`
917			`-1`
918			`3`
919			`clock0`
920			`-1`
921			`3`
922			`address_a8`
923			`-1`
924			`3`
925			`address_a7`
926			`-1`
927			`3`
928			`address_a6`
929			`-1`
930			`3`
931			`address_a5`
932			`-1`
933			`3`
934			`address_a4`
935			`-1`
936			`3`
937			`address_a3`
938			`-1`
939			`3`
940			`address_a2`
941			`-1`
942			`3`
943			`address_a1`
944			`-1`
945			`3`
946			`address_a0`
947			`-1`
948			`3`
949			`}`
950			`# memory_file {`
951			`adder.mif`
952			`bb8d3b979b75eab27c7eb9bd52dd54a`
953			`}`
954			`# macro_sequence`
955
956			`# end`
957			`# entity`
958			`usimplez_cpu`
959			`# storage`
960			`db\|usimplez_top.(1).cnf`
961			`db\|usimplez_top.(1).cnf`
962			`# logic_option {`
963			`AUTO_RAM_RECOGNITION`
964			`ON`
965			`}`
966			`# case_insensitive`
967			`# source_file`
968			`usimplez_cpu.vhd`
969			`ad52f891b788a95c143c0e372a9bc6b`
970			`5`
971			`# internal_option {`
972			`HDL_INITIAL_FANOUT_LIMIT`
973			`OFF`
974			`AUTO_RESOURCE_SHARING`
975			`OFF`
976			`AUTO_RAM_RECOGNITION`
977			`ON`
978			`AUTO_ROM_RECOGNITION`
979			`ON`
980			`}`
981			`# user_parameter {`
982			`width_word`
983			`12`
984			`PARAMETER_SIGNED_DEC`
985			`USR`
986			`width_operation_code`
987			`3`
988			`PARAMETER_SIGNED_DEC`
989			`USR`
990			`width_address`
991			`9`
992			`PARAMETER_SIGNED_DEC`
993			`USR`
994			`st`
995			`000`
996			`PARAMETER_UNSIGNED_BIN`
997			`USR`
998			`ld`
999			`001`
1000			`PARAMETER_UNSIGNED_BIN`
1001			`USR`
1002			`add`
1003			`010`
1004			`PARAMETER_UNSIGNED_BIN`
1005			`USR`
1006			`br`
1007			`011`
1008			`PARAMETER_UNSIGNED_BIN`
1009			`USR`
1010			`bz`
1011			`100`
1012			`PARAMETER_UNSIGNED_BIN`
1013			`USR`
1014			`clr`
1015			`101`
1016			`PARAMETER_UNSIGNED_BIN`
1017			`USR`
1018			`dec`
1019			`110`
1020			`PARAMETER_UNSIGNED_BIN`
1021			`USR`
1022			`halt`
1023			`111`
1024			`PARAMETER_UNSIGNED_BIN`
1025			`USR`
1026			`constraint(st)`
1027
1028			`PARAMETER_STRING`
1029			`USR`
1030			`constraint(ld)`
1031
1032			`PARAMETER_STRING`
1033			`USR`
1034			`constraint(add)`
1035
1036			`PARAMETER_STRING`
1037			`USR`
1038			`constraint(br)`
1039
1040			`PARAMETER_STRING`
1041			`USR`
1042			`constraint(bz)`
1043
1044			`PARAMETER_STRING`
1045			`USR`
1046			`constraint(clr)`
1047
1048			`PARAMETER_STRING`
1049			`USR`
1050			`constraint(dec)`
1051
1052			`PARAMETER_STRING`
1053			`USR`
1054			`constraint(halt)`
1055
1056			`PARAMETER_STRING`
1057			`USR`
1058			`constraint(data_bus_i)`
1059			`11 downto 0`
1060			`PARAMETER_STRING`
1061			`USR`
1062			`constraint(data_bus_o)`
1063			`11 downto 0`
1064			`PARAMETER_STRING`
1065			`USR`
1066			`constraint(addr_bus_o)`
1067			`8 downto 0`
1068			`PARAMETER_STRING`
1069			`USR`
1070			`}`
1071			`# hierarchies {`
1072			`usimplez_cpu:cpu`
1073			`}`
1074			`# lmf`
1075			`\|altera\|quartus\|lmf\|maxplus2.lmf`
1076			`a36c8ec425c8a2589af98b2d4daabc3`
1077			`# macro_sequence`
1078
1079			`# end`
1080			`# entity`
1081			`usimplez_ram`
1082			`# storage`
1083			`db\|usimplez_top.(2).cnf`
1084			`db\|usimplez_top.(2).cnf`
1085			`# logic_option {`
1086			`AUTO_RAM_RECOGNITION`
1087			`ON`
1088			`}`
1089			`# case_insensitive`
1090			`# source_file`
1091			`usimplez_ram.vhd`
1092			`c21bed544a534d01c38852e7cf9346b`
1093			`5`
1094			`# internal_option {`
1095			`HDL_INITIAL_FANOUT_LIMIT`
1096			`OFF`
1097			`AUTO_RESOURCE_SHARING`
1098			`OFF`
1099			`AUTO_RAM_RECOGNITION`
1100			`ON`
1101			`AUTO_ROM_RECOGNITION`
1102			`ON`
1103			`}`
1104			`# user_parameter {`
1105			`width_word`
1106			`12`
1107			`PARAMETER_SIGNED_DEC`
1108			`USR`
1109			`width_address`
1110			`9`
1111			`PARAMETER_SIGNED_DEC`
1112			`USR`
1113			`constraint(addr_i)`
1114			`8 downto 0`
1115			`PARAMETER_STRING`
1116			`USR`
1117			`constraint(data_i)`
1118			`11 downto 0`
1119			`PARAMETER_STRING`
1120			`USR`
1121			`constraint(data_o)`
1122			`11 downto 0`
1123			`PARAMETER_STRING`
1124			`USR`
1125			`}`
1126			`# hierarchies {`
1127			`usimplez_ram:ram`
1128			`}`
1129			`# lmf`
1130			`\|altera\|quartus\|lmf\|maxplus2.lmf`
1131			`a36c8ec425c8a2589af98b2d4daabc3`
1132			`# macro_sequence`
1133
1134			`# end`
1135			`# complete`
1136