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--//////////////////////////////////////////////////////////////////////
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--//// ////
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--//// ////
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--//// ////
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--//// This file is part of the MicroSimplez project ////
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--//// http://opencores.org/project,usimplez ////
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--//// ////
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--//// Description ////
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--//// Implementation of MicroSimplez IP core according to ////
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--//// MicroSimplez IP core specification document. ////
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--//// ////
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--//// To Do: ////
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--//// - ////
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--//// ////
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--//// Author(s): ////
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--//// - Daniel Peralta, peraltahd@opencores.org, designer ////
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--//// - Martin Montero, monteromrtn@opencores.org, designer ////
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--//// - Julian Castro, julyan@opencores.org, reviewer ////
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--//// - Pablo A. Salvadeo, pas.@opencores, manager ////
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--//// ////
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--//////////////////////////////////////////////////////////////////////
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--//// ////
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--//// Copyright (C) 2011 Authors and OPENCORES.ORG ////
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--//// ////
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--//// This source file may be used and distributed without ////
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--//// restriction provided that this copyright statement is not ////
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--//// removed from the file and that any derivative work contains ////
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--//// the original copyright notice and the associated disclaimer. ////
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--//// ////
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--//// This source file is free software; you can redistribute it ////
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--//// and/or modify it under the terms of the GNU Lesser General ////
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--//// Public License as published by the Free Software Foundation; ////
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--//// either version 2.1 of the License, or (at your option) any ////
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--//// later version. ////
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--//// ////
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--//// This source is distributed in the hope that it will be ////
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--//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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--//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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--//// PURPOSE. See the GNU Lesser General Public License for more ////
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--//// details. ////
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--//// ////
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--//// You should have received a copy of the GNU Lesser General ////
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--//// Public License along with this source; if not, download it ////
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--//// from http://www.opencores.org/lgpl.shtml ////
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--//// ////
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--//////////////////////////////////////////////////////////////////////
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity usimplez_ram is
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generic( WIDTH_WORD: natural:= 12;
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WIDTH_ADDRESS: natural:= 9
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);
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port
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(
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clk_i : in std_logic;
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addr_i : in unsigned((WIDTH_ADDRESS-1) downto 0);
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data_i : in std_logic_vector((WIDTH_WORD-1) downto 0);
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we_i : in std_logic ;
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data_o : out std_logic_vector((WIDTH_WORD-1) downto 0)
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);
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end usimplez_ram;
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architecture rtl of usimplez_ram is
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subtype word_t is std_logic_vector((WIDTH_WORD-1) downto 0);
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type memory_t is array(2**WIDTH_ADDRESS-1 downto 0) of word_t;
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signal ram : memory_t;
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attribute ram_init_file : string;
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attribute ram_init_file of ram : signal is "adder.mif"; --code adder.txt
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-- attribute ram_init_file of ram : signal is "fibonacci.mif"; --code fibonacci.txt
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signal addr_reg_s : unsigned((WIDTH_ADDRESS-1) downto 0);
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begin
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process(clk_i)
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begin
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if(falling_edge(clk_i)) then
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if(we_i = '1') then
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ram(to_integer(addr_i)) <= data_i;
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end if;
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addr_reg_s <= addr_i;
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end if;
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end process;
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data_o <= ram(to_integer(addr_reg_s));
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end rtl;
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