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[/] [usimplez/] [trunk/] [QuartusII/] [usimplez_top.flow.rpt] - Blame information for rev 3

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1 3 pas.
Flow report for usimplez_top
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Wed Nov 09 11:47:37 2011
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Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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  1. Legal Notice
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  2. Flow Summary
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  3. Flow Settings
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  4. Flow Non-Default Global Settings
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  5. Flow Elapsed Time
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  6. Flow OS Summary
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  7. Flow Log
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2010 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors.  Please refer to the
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applicable agreement for further details.
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+------------------------------------------------------------------------------+
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; Flow Summary                                                                 ;
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+-------------------------------+----------------------------------------------+
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; Flow Status                   ; Successful - Wed Nov 09 11:47:37 2011        ;
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; Quartus II Version            ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
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; Revision Name                 ; usimplez_top                                 ;
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; Top-level Entity Name         ; usimplez_top                                 ;
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; Family                        ; Stratix II                                   ;
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; Met timing requirements       ; N/A                                          ;
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; Logic utilization             ; < 1 %                                        ;
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;     Combinational ALUTs       ; 48 / 12,480 ( < 1 % )                        ;
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;     Dedicated logic registers ; 63 / 12,480 ( < 1 % )                        ;
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; Total registers               ; 63                                           ;
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; Total pins                    ; 7 / 343 ( 2 % )                              ;
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; Total virtual pins            ; 0                                            ;
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; Total block memory bits       ; 6,144 / 419,328 ( 1 % )                      ;
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; DSP block 9-bit elements      ; 0 / 96 ( 0 % )                               ;
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; Total PLLs                    ; 0 / 6 ( 0 % )                                ;
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; Total DLLs                    ; 0 / 2 ( 0 % )                                ;
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; Device                        ; EP2S15F484C3                                 ;
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; Timing Models                 ; Final                                        ;
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+-------------------------------+----------------------------------------------+
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+-----------------------------------------+
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; Flow Settings                           ;
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+-------------------+---------------------+
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; Option            ; Setting             ;
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+-------------------+---------------------+
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; Start date & time ; 11/09/2011 11:45:50 ;
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; Main task         ; Compilation         ;
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; Revision Name     ; usimplez_top        ;
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+-------------------+---------------------+
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+--------------------------------------------------------------------------------------------------------------------+
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; Flow Non-Default Global Settings                                                                                   ;
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+------------------------------------+--------------------------------+---------------+-------------+----------------+
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; Assignment Name                    ; Value                          ; Default Value ; Entity Name ; Section Id     ;
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+------------------------------------+--------------------------------+---------------+-------------+----------------+
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; COMPILER_SIGNATURE_ID              ; 13608450046966.132084994903584 ; --            ; --          ; --             ;
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; PARTITION_COLOR                    ; 16764057                       ; --            ; --          ; Top            ;
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; PARTITION_NETLIST_TYPE             ; SOURCE                         ; --            ; --          ; Top            ;
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; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off                            ; --            ; --          ; eda_blast_fpga ;
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+------------------------------------+--------------------------------+---------------+-------------+----------------+
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+--------------------------------------------------------------------------------------------------------------------------+
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; Flow Elapsed Time                                                                                                        ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Analysis & Synthesis ; 00:00:12     ; 1.0                     ; 194 MB              ; 00:00:12                           ;
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; Fitter               ; 00:00:27     ; 1.0                     ; 236 MB              ; 00:00:26                           ;
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; Total                ; 00:00:39     ; --                      ; --                  ; 00:00:38                           ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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+------------------------------------------------------------------------------------+
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; Flow OS Summary                                                                    ;
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+----------------------+------------------+------------+------------+----------------+
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; Module Name          ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
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+----------------------+------------------+------------+------------+----------------+
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; Analysis & Synthesis ; LAPTOP           ; Windows XP ; 5.1        ; i686           ;
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; Fitter               ; LAPTOP           ; Windows XP ; 5.1        ; i686           ;
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+----------------------+------------------+------------+------------+----------------+
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------------
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; Flow Log ;
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------------
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quartus_map --read_settings_files=on --write_settings_files=off usimplez -c usimplez_top
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quartus_fit --read_settings_files=on --write_settings_files=off usimplez -c usimplez_top
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