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URL https://opencores.org/ocsvn/usimplez/usimplez/trunk

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[/] [usimplez/] [trunk/] [QuartusII/] [usimplez_top.vwf] - Blame information for rev 2

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1 2 pas. 
/*
2 
WARNING: Do NOT edit the input and output ports in this file in a text
3 
editor if you plan to continue editing the block that represents it in
4 
the Block Editor! File corruption is VERY likely to occur.
5 
*/
6 
 
7 
/*
8 
Copyright (C) 1991-2010 Altera Corporation
9 
Your use of Altera Corporation's design tools, logic functions
10 
and other software and tools, and its AMPP partner logic
11 
functions, and any output files from any of the foregoing
12 
(including device programming or simulation files), and any
13 
associated documentation or information are expressly subject
14 
to the terms and conditions of the Altera Program License
15 
Subscription Agreement, Altera MegaCore Function License
16 
Agreement, or other applicable license agreement, including,
17 
without limitation, that your use is for the sole purpose of
18 
programming logic devices manufactured by Altera and sold by
19 
Altera or its authorized distributors.  Please refer to the
20 
applicable agreement for further details.
21 
*/
22 
 
23 
HEADER
24 
{
25 
        VERSION = 1;
26 
        TIME_UNIT = ns;
27 
        DATA_OFFSET = 0.0;
28 
        DATA_DURATION = 100000.0;
29 
        SIMULATION_TIME = 0.0;
30 
        GRID_PHASE = 0.0;
31 
        GRID_PERIOD = 10.0;
32 
        GRID_DUTY_CYCLE = 50;
33 
}
34 
 
35 
SIGNAL("usimplez_cpu:cpu|acumulador")
36 
{
37 
        VALUE_TYPE = NINE_LEVEL_BIT;
38 
        SIGNAL_TYPE = BUS;
39 
        WIDTH = 12;
40 
        LSB_INDEX = 0;
41 
        DIRECTION = REGISTERED;
42 
        PARENT = "";
43 
}
44 
 
45 
SIGNAL("usimplez_cpu:cpu|acumulador[11]")
46 
{
47 
        VALUE_TYPE = NINE_LEVEL_BIT;
48 
        SIGNAL_TYPE = SINGLE_BIT;
49 
        WIDTH = 1;
50 
        LSB_INDEX = -1;
51 
        DIRECTION = REGISTERED;
52 
        PARENT = "usimplez_cpu:cpu|acumulador";
53 
}
54 
 
55 
SIGNAL("usimplez_cpu:cpu|acumulador[10]")
56 
{
57 
        VALUE_TYPE = NINE_LEVEL_BIT;
58 
        SIGNAL_TYPE = SINGLE_BIT;
59 
        WIDTH = 1;
60 
        LSB_INDEX = -1;
61 
        DIRECTION = REGISTERED;
62 
        PARENT = "usimplez_cpu:cpu|acumulador";
63 
}
64 
 
65 
SIGNAL("usimplez_cpu:cpu|acumulador[9]")
66 
{
67 
        VALUE_TYPE = NINE_LEVEL_BIT;
68 
        SIGNAL_TYPE = SINGLE_BIT;
69 
        WIDTH = 1;
70 
        LSB_INDEX = -1;
71 
        DIRECTION = REGISTERED;
72 
        PARENT = "usimplez_cpu:cpu|acumulador";
73 
}
74 
 
75 
SIGNAL("usimplez_cpu:cpu|acumulador[8]")
76 
{
77 
        VALUE_TYPE = NINE_LEVEL_BIT;
78 
        SIGNAL_TYPE = SINGLE_BIT;
79 
        WIDTH = 1;
80 
        LSB_INDEX = -1;
81 
        DIRECTION = REGISTERED;
82 
        PARENT = "usimplez_cpu:cpu|acumulador";
83 
}
84 
 
85 
SIGNAL("usimplez_cpu:cpu|acumulador[7]")
86 
{
87 
        VALUE_TYPE = NINE_LEVEL_BIT;
88 
        SIGNAL_TYPE = SINGLE_BIT;
89 
        WIDTH = 1;
90 
        LSB_INDEX = -1;
91 
        DIRECTION = REGISTERED;
92 
        PARENT = "usimplez_cpu:cpu|acumulador";
93 
}
94 
 
95 
SIGNAL("usimplez_cpu:cpu|acumulador[6]")
96 
{
97 
        VALUE_TYPE = NINE_LEVEL_BIT;
98 
        SIGNAL_TYPE = SINGLE_BIT;
99 
        WIDTH = 1;
100 
        LSB_INDEX = -1;
101 
        DIRECTION = REGISTERED;
102 
        PARENT = "usimplez_cpu:cpu|acumulador";
103 
}
104 
 
105 
SIGNAL("usimplez_cpu:cpu|acumulador[5]")
106 
{
107 
        VALUE_TYPE = NINE_LEVEL_BIT;
108 
        SIGNAL_TYPE = SINGLE_BIT;
109 
        WIDTH = 1;
110 
        LSB_INDEX = -1;
111 
        DIRECTION = REGISTERED;
112 
        PARENT = "usimplez_cpu:cpu|acumulador";
113 
}
114 
 
115 
SIGNAL("usimplez_cpu:cpu|acumulador[4]")
116 
{
117 
        VALUE_TYPE = NINE_LEVEL_BIT;
118 
        SIGNAL_TYPE = SINGLE_BIT;
119 
        WIDTH = 1;
120 
        LSB_INDEX = -1;
121 
        DIRECTION = REGISTERED;
122 
        PARENT = "usimplez_cpu:cpu|acumulador";
123 
}
124 
 
125 
SIGNAL("usimplez_cpu:cpu|acumulador[3]")
126 
{
127 
        VALUE_TYPE = NINE_LEVEL_BIT;
128 
        SIGNAL_TYPE = SINGLE_BIT;
129 
        WIDTH = 1;
130 
        LSB_INDEX = -1;
131 
        DIRECTION = REGISTERED;
132 
        PARENT = "usimplez_cpu:cpu|acumulador";
133 
}
134 
 
135 
SIGNAL("usimplez_cpu:cpu|acumulador[2]")
136 
{
137 
        VALUE_TYPE = NINE_LEVEL_BIT;
138 
        SIGNAL_TYPE = SINGLE_BIT;
139 
        WIDTH = 1;
140 
        LSB_INDEX = -1;
141 
        DIRECTION = REGISTERED;
142 
        PARENT = "usimplez_cpu:cpu|acumulador";
143 
}
144 
 
145 
SIGNAL("usimplez_cpu:cpu|acumulador[1]")
146 
{
147 
        VALUE_TYPE = NINE_LEVEL_BIT;
148 
        SIGNAL_TYPE = SINGLE_BIT;
149 
        WIDTH = 1;
150 
        LSB_INDEX = -1;
151 
        DIRECTION = REGISTERED;
152 
        PARENT = "usimplez_cpu:cpu|acumulador";
153 
}
154 
 
155 
SIGNAL("usimplez_cpu:cpu|acumulador[0]")
156 
{
157 
        VALUE_TYPE = NINE_LEVEL_BIT;
158 
        SIGNAL_TYPE = SINGLE_BIT;
159 
        WIDTH = 1;
160 
        LSB_INDEX = -1;
161 
        DIRECTION = REGISTERED;
162 
        PARENT = "usimplez_cpu:cpu|acumulador";
163 
}
164 
 
165 
SIGNAL("usimplez_cpu:cpu|addr_bus_o")
166 
{
167 
        VALUE_TYPE = NINE_LEVEL_BIT;
168 
        SIGNAL_TYPE = BUS;
169 
        WIDTH = 9;
170 
        LSB_INDEX = 0;
171 
        DIRECTION = REGISTERED;
172 
        PARENT = "";
173 
}
174 
 
175 
SIGNAL("usimplez_cpu:cpu|addr_bus_o[8]")
176 
{
177 
        VALUE_TYPE = NINE_LEVEL_BIT;
178 
        SIGNAL_TYPE = SINGLE_BIT;
179 
        WIDTH = 1;
180 
        LSB_INDEX = -1;
181 
        DIRECTION = REGISTERED;
182 
        PARENT = "usimplez_cpu:cpu|addr_bus_o";
183 
}
184 
 
185 
SIGNAL("usimplez_cpu:cpu|addr_bus_o[7]")
186 
{
187 
        VALUE_TYPE = NINE_LEVEL_BIT;
188 
        SIGNAL_TYPE = SINGLE_BIT;
189 
        WIDTH = 1;
190 
        LSB_INDEX = -1;
191 
        DIRECTION = REGISTERED;
192 
        PARENT = "usimplez_cpu:cpu|addr_bus_o";
193 
}
194 
 
195 
SIGNAL("usimplez_cpu:cpu|addr_bus_o[6]")
196 
{
197 
        VALUE_TYPE = NINE_LEVEL_BIT;
198 
        SIGNAL_TYPE = SINGLE_BIT;
199 
        WIDTH = 1;
200 
        LSB_INDEX = -1;
201 
        DIRECTION = REGISTERED;
202 
        PARENT = "usimplez_cpu:cpu|addr_bus_o";
203 
}
204 
 
205 
SIGNAL("usimplez_cpu:cpu|addr_bus_o[5]")
206 
{
207 
        VALUE_TYPE = NINE_LEVEL_BIT;
208 
        SIGNAL_TYPE = SINGLE_BIT;
209 
        WIDTH = 1;
210 
        LSB_INDEX = -1;
211 
        DIRECTION = REGISTERED;
212 
        PARENT = "usimplez_cpu:cpu|addr_bus_o";
213 
}
214 
 
215 
SIGNAL("usimplez_cpu:cpu|addr_bus_o[4]")
216 
{
217 
        VALUE_TYPE = NINE_LEVEL_BIT;
218 
        SIGNAL_TYPE = SINGLE_BIT;
219 
        WIDTH = 1;
220 
        LSB_INDEX = -1;
221 
        DIRECTION = REGISTERED;
222 
        PARENT = "usimplez_cpu:cpu|addr_bus_o";
223 
}
224 
 
225 
SIGNAL("usimplez_cpu:cpu|addr_bus_o[3]")
226 
{
227 
        VALUE_TYPE = NINE_LEVEL_BIT;
228 
        SIGNAL_TYPE = SINGLE_BIT;
229 
        WIDTH = 1;
230 
        LSB_INDEX = -1;
231 
        DIRECTION = REGISTERED;
232 
        PARENT = "usimplez_cpu:cpu|addr_bus_o";
233 
}
234 
 
235 
SIGNAL("usimplez_cpu:cpu|addr_bus_o[2]")
236 
{
237 
        VALUE_TYPE = NINE_LEVEL_BIT;
238 
        SIGNAL_TYPE = SINGLE_BIT;
239 
        WIDTH = 1;
240 
        LSB_INDEX = -1;
241 
        DIRECTION = REGISTERED;
242 
        PARENT = "usimplez_cpu:cpu|addr_bus_o";
243 
}
244 
 
245 
SIGNAL("usimplez_cpu:cpu|addr_bus_o[1]")
246 
{
247 
        VALUE_TYPE = NINE_LEVEL_BIT;
248 
        SIGNAL_TYPE = SINGLE_BIT;
249 
        WIDTH = 1;
250 
        LSB_INDEX = -1;
251 
        DIRECTION = REGISTERED;
252 
        PARENT = "usimplez_cpu:cpu|addr_bus_o";
253 
}
254 
 
255 
SIGNAL("usimplez_cpu:cpu|addr_bus_o[0]")
256 
{
257 
        VALUE_TYPE = NINE_LEVEL_BIT;
258 
        SIGNAL_TYPE = SINGLE_BIT;
259 
        WIDTH = 1;
260 
        LSB_INDEX = -1;
261 
        DIRECTION = REGISTERED;
262 
        PARENT = "usimplez_cpu:cpu|addr_bus_o";
263 
}
264 
 
265 
SIGNAL("usimplez_cpu:cpu|cd_reg_s")
266 
{
267 
        VALUE_TYPE = NINE_LEVEL_BIT;
268 
        SIGNAL_TYPE = BUS;
269 
        WIDTH = 9;
270 
        LSB_INDEX = 0;
271 
        DIRECTION = REGISTERED;
272 
        PARENT = "";
273 
}
274 
 
275 
SIGNAL("usimplez_cpu:cpu|cd_reg_s[8]")
276 
{
277 
        VALUE_TYPE = NINE_LEVEL_BIT;
278 
        SIGNAL_TYPE = SINGLE_BIT;
279 
        WIDTH = 1;
280 
        LSB_INDEX = -1;
281 
        DIRECTION = REGISTERED;
282 
        PARENT = "usimplez_cpu:cpu|cd_reg_s";
283 
}
284 
 
285 
SIGNAL("usimplez_cpu:cpu|cd_reg_s[7]")
286 
{
287 
        VALUE_TYPE = NINE_LEVEL_BIT;
288 
        SIGNAL_TYPE = SINGLE_BIT;
289 
        WIDTH = 1;
290 
        LSB_INDEX = -1;
291 
        DIRECTION = REGISTERED;
292 
        PARENT = "usimplez_cpu:cpu|cd_reg_s";
293 
}
294 
 
295 
SIGNAL("usimplez_cpu:cpu|cd_reg_s[6]")
296 
{
297 
        VALUE_TYPE = NINE_LEVEL_BIT;
298 
        SIGNAL_TYPE = SINGLE_BIT;
299 
        WIDTH = 1;
300 
        LSB_INDEX = -1;
301 
        DIRECTION = REGISTERED;
302 
        PARENT = "usimplez_cpu:cpu|cd_reg_s";
303 
}
304 
 
305 
SIGNAL("usimplez_cpu:cpu|cd_reg_s[5]")
306 
{
307 
        VALUE_TYPE = NINE_LEVEL_BIT;
308 
        SIGNAL_TYPE = SINGLE_BIT;
309 
        WIDTH = 1;
310 
        LSB_INDEX = -1;
311 
        DIRECTION = REGISTERED;
312 
        PARENT = "usimplez_cpu:cpu|cd_reg_s";
313 
}
314 
 
315 
SIGNAL("usimplez_cpu:cpu|cd_reg_s[4]")
316 
{
317 
        VALUE_TYPE = NINE_LEVEL_BIT;
318 
        SIGNAL_TYPE = SINGLE_BIT;
319 
        WIDTH = 1;
320 
        LSB_INDEX = -1;
321 
        DIRECTION = REGISTERED;
322 
        PARENT = "usimplez_cpu:cpu|cd_reg_s";
323 
}
324 
 
325 
SIGNAL("usimplez_cpu:cpu|cd_reg_s[3]")
326 
{
327 
        VALUE_TYPE = NINE_LEVEL_BIT;
328 
        SIGNAL_TYPE = SINGLE_BIT;
329 
        WIDTH = 1;
330 
        LSB_INDEX = -1;
331 
        DIRECTION = REGISTERED;
332 
        PARENT = "usimplez_cpu:cpu|cd_reg_s";
333 
}
334 
 
335 
SIGNAL("usimplez_cpu:cpu|cd_reg_s[2]")
336 
{
337 
        VALUE_TYPE = NINE_LEVEL_BIT;
338 
        SIGNAL_TYPE = SINGLE_BIT;
339 
        WIDTH = 1;
340 
        LSB_INDEX = -1;
341 
        DIRECTION = REGISTERED;
342 
        PARENT = "usimplez_cpu:cpu|cd_reg_s";
343 
}
344 
 
345 
SIGNAL("usimplez_cpu:cpu|cd_reg_s[1]")
346 
{
347 
        VALUE_TYPE = NINE_LEVEL_BIT;
348 
        SIGNAL_TYPE = SINGLE_BIT;
349 
        WIDTH = 1;
350 
        LSB_INDEX = -1;
351 
        DIRECTION = REGISTERED;
352 
        PARENT = "usimplez_cpu:cpu|cd_reg_s";
353 
}
354 
 
355 
SIGNAL("usimplez_cpu:cpu|cd_reg_s[0]")
356 
{
357 
        VALUE_TYPE = NINE_LEVEL_BIT;
358 
        SIGNAL_TYPE = SINGLE_BIT;
359 
        WIDTH = 1;
360 
        LSB_INDEX = -1;
361 
        DIRECTION = REGISTERED;
362 
        PARENT = "usimplez_cpu:cpu|cd_reg_s";
363 
}
364 
 
365 
SIGNAL("usimplez_cpu:cpu|co_reg_s")
366 
{
367 
        VALUE_TYPE = NINE_LEVEL_BIT;
368 
        SIGNAL_TYPE = BUS;
369 
        WIDTH = 3;
370 
        LSB_INDEX = 0;
371 
        DIRECTION = REGISTERED;
372 
        PARENT = "";
373 
}
374 
 
375 
SIGNAL("usimplez_cpu:cpu|co_reg_s[2]")
376 
{
377 
        VALUE_TYPE = NINE_LEVEL_BIT;
378 
        SIGNAL_TYPE = SINGLE_BIT;
379 
        WIDTH = 1;
380 
        LSB_INDEX = -1;
381 
        DIRECTION = REGISTERED;
382 
        PARENT = "usimplez_cpu:cpu|co_reg_s";
383 
}
384 
 
385 
SIGNAL("usimplez_cpu:cpu|co_reg_s[1]")
386 
{
387 
        VALUE_TYPE = NINE_LEVEL_BIT;
388 
        SIGNAL_TYPE = SINGLE_BIT;
389 
        WIDTH = 1;
390 
        LSB_INDEX = -1;
391 
        DIRECTION = REGISTERED;
392 
        PARENT = "usimplez_cpu:cpu|co_reg_s";
393 
}
394 
 
395 
SIGNAL("usimplez_cpu:cpu|co_reg_s[0]")
396 
{
397 
        VALUE_TYPE = NINE_LEVEL_BIT;
398 
        SIGNAL_TYPE = SINGLE_BIT;
399 
        WIDTH = 1;
400 
        LSB_INDEX = -1;
401 
        DIRECTION = REGISTERED;
402 
        PARENT = "usimplez_cpu:cpu|co_reg_s";
403 
}
404 
 
405 
SIGNAL("usimplez_cpu:cpu|cp_reg_s")
406 
{
407 
        VALUE_TYPE = NINE_LEVEL_BIT;
408 
        SIGNAL_TYPE = BUS;
409 
        WIDTH = 9;
410 
        LSB_INDEX = 0;
411 
        DIRECTION = REGISTERED;
412 
        PARENT = "";
413 
}
414 
 
415 
SIGNAL("usimplez_cpu:cpu|cp_reg_s[8]")
416 
{
417 
        VALUE_TYPE = NINE_LEVEL_BIT;
418 
        SIGNAL_TYPE = SINGLE_BIT;
419 
        WIDTH = 1;
420 
        LSB_INDEX = -1;
421 
        DIRECTION = REGISTERED;
422 
        PARENT = "usimplez_cpu:cpu|cp_reg_s";
423 
}
424 
 
425 
SIGNAL("usimplez_cpu:cpu|cp_reg_s[7]")
426 
{
427 
        VALUE_TYPE = NINE_LEVEL_BIT;
428 
        SIGNAL_TYPE = SINGLE_BIT;
429 
        WIDTH = 1;
430 
        LSB_INDEX = -1;
431 
        DIRECTION = REGISTERED;
432 
        PARENT = "usimplez_cpu:cpu|cp_reg_s";
433 
}
434 
 
435 
SIGNAL("usimplez_cpu:cpu|cp_reg_s[6]")
436 
{
437 
        VALUE_TYPE = NINE_LEVEL_BIT;
438 
        SIGNAL_TYPE = SINGLE_BIT;
439 
        WIDTH = 1;
440 
        LSB_INDEX = -1;
441 
        DIRECTION = REGISTERED;
442 
        PARENT = "usimplez_cpu:cpu|cp_reg_s";
443 
}
444 
 
445 
SIGNAL("usimplez_cpu:cpu|cp_reg_s[5]")
446 
{
447 
        VALUE_TYPE = NINE_LEVEL_BIT;
448 
        SIGNAL_TYPE = SINGLE_BIT;
449 
        WIDTH = 1;
450 
        LSB_INDEX = -1;
451 
        DIRECTION = REGISTERED;
452 
        PARENT = "usimplez_cpu:cpu|cp_reg_s";
453 
}
454 
 
455 
SIGNAL("usimplez_cpu:cpu|cp_reg_s[4]")
456 
{
457 
        VALUE_TYPE = NINE_LEVEL_BIT;
458 
        SIGNAL_TYPE = SINGLE_BIT;
459 
        WIDTH = 1;
460 
        LSB_INDEX = -1;
461 
        DIRECTION = REGISTERED;
462 
        PARENT = "usimplez_cpu:cpu|cp_reg_s";
463 
}
464 
 
465 
SIGNAL("usimplez_cpu:cpu|cp_reg_s[3]")
466 
{
467 
        VALUE_TYPE = NINE_LEVEL_BIT;
468 
        SIGNAL_TYPE = SINGLE_BIT;
469 
        WIDTH = 1;
470 
        LSB_INDEX = -1;
471 
        DIRECTION = REGISTERED;
472 
        PARENT = "usimplez_cpu:cpu|cp_reg_s";
473 
}
474 
 
475 
SIGNAL("usimplez_cpu:cpu|cp_reg_s[2]")
476 
{
477 
        VALUE_TYPE = NINE_LEVEL_BIT;
478 
        SIGNAL_TYPE = SINGLE_BIT;
479 
        WIDTH = 1;
480 
        LSB_INDEX = -1;
481 
        DIRECTION = REGISTERED;
482 
        PARENT = "usimplez_cpu:cpu|cp_reg_s";
483 
}
484 
 
485 
SIGNAL("usimplez_cpu:cpu|cp_reg_s[1]")
486 
{
487 
        VALUE_TYPE = NINE_LEVEL_BIT;
488 
        SIGNAL_TYPE = SINGLE_BIT;
489 
        WIDTH = 1;
490 
        LSB_INDEX = -1;
491 
        DIRECTION = REGISTERED;
492 
        PARENT = "usimplez_cpu:cpu|cp_reg_s";
493 
}
494 
 
495 
SIGNAL("usimplez_cpu:cpu|cp_reg_s[0]")
496 
{
497 
        VALUE_TYPE = NINE_LEVEL_BIT;
498 
        SIGNAL_TYPE = SINGLE_BIT;
499 
        WIDTH = 1;
500 
        LSB_INDEX = -1;
501 
        DIRECTION = REGISTERED;
502 
        PARENT = "usimplez_cpu:cpu|cp_reg_s";
503 
}
504 
 
505 
SIGNAL("usimplez_cpu:cpu|data_bus_o")
506 
{
507 
        VALUE_TYPE = NINE_LEVEL_BIT;
508 
        SIGNAL_TYPE = BUS;
509 
        WIDTH = 12;
510 
        LSB_INDEX = 0;
511 
        DIRECTION = REGISTERED;
512 
        PARENT = "";
513 
}
514 
 
515 
SIGNAL("usimplez_cpu:cpu|data_bus_o[11]")
516 
{
517 
        VALUE_TYPE = NINE_LEVEL_BIT;
518 
        SIGNAL_TYPE = SINGLE_BIT;
519 
        WIDTH = 1;
520 
        LSB_INDEX = -1;
521 
        DIRECTION = REGISTERED;
522 
        PARENT = "usimplez_cpu:cpu|data_bus_o";
523 
}
524 
 
525 
SIGNAL("usimplez_cpu:cpu|data_bus_o[10]")
526 
{
527 
        VALUE_TYPE = NINE_LEVEL_BIT;
528 
        SIGNAL_TYPE = SINGLE_BIT;
529 
        WIDTH = 1;
530 
        LSB_INDEX = -1;
531 
        DIRECTION = REGISTERED;
532 
        PARENT = "usimplez_cpu:cpu|data_bus_o";
533 
}
534 
 
535 
SIGNAL("usimplez_cpu:cpu|data_bus_o[9]")
536 
{
537 
        VALUE_TYPE = NINE_LEVEL_BIT;
538 
        SIGNAL_TYPE = SINGLE_BIT;
539 
        WIDTH = 1;
540 
        LSB_INDEX = -1;
541 
        DIRECTION = REGISTERED;
542 
        PARENT = "usimplez_cpu:cpu|data_bus_o";
543 
}
544 
 
545 
SIGNAL("usimplez_cpu:cpu|data_bus_o[8]")
546 
{
547 
        VALUE_TYPE = NINE_LEVEL_BIT;
548 
        SIGNAL_TYPE = SINGLE_BIT;
549 
        WIDTH = 1;
550 
        LSB_INDEX = -1;
551 
        DIRECTION = REGISTERED;
552 
        PARENT = "usimplez_cpu:cpu|data_bus_o";
553 
}
554 
 
555 
SIGNAL("usimplez_cpu:cpu|data_bus_o[7]")
556 
{
557 
        VALUE_TYPE = NINE_LEVEL_BIT;
558 
        SIGNAL_TYPE = SINGLE_BIT;
559 
        WIDTH = 1;
560 
        LSB_INDEX = -1;
561 
        DIRECTION = REGISTERED;
562 
        PARENT = "usimplez_cpu:cpu|data_bus_o";
563 
}
564 
 
565 
SIGNAL("usimplez_cpu:cpu|data_bus_o[6]")
566 
{
567 
        VALUE_TYPE = NINE_LEVEL_BIT;
568 
        SIGNAL_TYPE = SINGLE_BIT;
569 
        WIDTH = 1;
570 
        LSB_INDEX = -1;
571 
        DIRECTION = REGISTERED;
572 
        PARENT = "usimplez_cpu:cpu|data_bus_o";
573 
}
574 
 
575 
SIGNAL("usimplez_cpu:cpu|data_bus_o[5]")
576 
{
577 
        VALUE_TYPE = NINE_LEVEL_BIT;
578 
        SIGNAL_TYPE = SINGLE_BIT;
579 
        WIDTH = 1;
580 
        LSB_INDEX = -1;
581 
        DIRECTION = REGISTERED;
582 
        PARENT = "usimplez_cpu:cpu|data_bus_o";
583 
}
584 
 
585 
SIGNAL("usimplez_cpu:cpu|data_bus_o[4]")
586 
{
587 
        VALUE_TYPE = NINE_LEVEL_BIT;
588 
        SIGNAL_TYPE = SINGLE_BIT;
589 
        WIDTH = 1;
590 
        LSB_INDEX = -1;
591 
        DIRECTION = REGISTERED;
592 
        PARENT = "usimplez_cpu:cpu|data_bus_o";
593 
}
594 
 
595 
SIGNAL("usimplez_cpu:cpu|data_bus_o[3]")
596 
{
597 
        VALUE_TYPE = NINE_LEVEL_BIT;
598 
        SIGNAL_TYPE = SINGLE_BIT;
599 
        WIDTH = 1;
600 
        LSB_INDEX = -1;
601 
        DIRECTION = REGISTERED;
602 
        PARENT = "usimplez_cpu:cpu|data_bus_o";
603 
}
604 
 
605 
SIGNAL("usimplez_cpu:cpu|data_bus_o[2]")
606 
{
607 
        VALUE_TYPE = NINE_LEVEL_BIT;
608 
        SIGNAL_TYPE = SINGLE_BIT;
609 
        WIDTH = 1;
610 
        LSB_INDEX = -1;
611 
        DIRECTION = REGISTERED;
612 
        PARENT = "usimplez_cpu:cpu|data_bus_o";
613 
}
614 
 
615 
SIGNAL("usimplez_cpu:cpu|data_bus_o[1]")
616 
{
617 
        VALUE_TYPE = NINE_LEVEL_BIT;
618 
        SIGNAL_TYPE = SINGLE_BIT;
619 
        WIDTH = 1;
620 
        LSB_INDEX = -1;
621 
        DIRECTION = REGISTERED;
622 
        PARENT = "usimplez_cpu:cpu|data_bus_o";
623 
}
624 
 
625 
SIGNAL("usimplez_cpu:cpu|data_bus_o[0]")
626 
{
627 
        VALUE_TYPE = NINE_LEVEL_BIT;
628 
        SIGNAL_TYPE = SINGLE_BIT;
629 
        WIDTH = 1;
630 
        LSB_INDEX = -1;
631 
        DIRECTION = REGISTERED;
632 
        PARENT = "usimplez_cpu:cpu|data_bus_o";
633 
}
634 
 
635 
SIGNAL("clk_i")
636 
{
637 
        VALUE_TYPE = NINE_LEVEL_BIT;
638 
        SIGNAL_TYPE = SINGLE_BIT;
639 
        WIDTH = 1;
640 
        LSB_INDEX = -1;
641 
        DIRECTION = INPUT;
642 
        PARENT = "";
643 
}
644 
 
645 
SIGNAL("in0_o")
646 
{
647 
        VALUE_TYPE = NINE_LEVEL_BIT;
648 
        SIGNAL_TYPE = SINGLE_BIT;
649 
        WIDTH = 1;
650 
        LSB_INDEX = -1;
651 
        DIRECTION = OUTPUT;
652 
        PARENT = "";
653 
}
654 
 
655 
SIGNAL("in1_o")
656 
{
657 
        VALUE_TYPE = NINE_LEVEL_BIT;
658 
        SIGNAL_TYPE = SINGLE_BIT;
659 
        WIDTH = 1;
660 
        LSB_INDEX = -1;
661 
        DIRECTION = OUTPUT;
662 
        PARENT = "";
663 
}
664 
 
665 
SIGNAL("op0_o")
666 
{
667 
        VALUE_TYPE = NINE_LEVEL_BIT;
668 
        SIGNAL_TYPE = SINGLE_BIT;
669 
        WIDTH = 1;
670 
        LSB_INDEX = -1;
671 
        DIRECTION = OUTPUT;
672 
        PARENT = "";
673 
}
674 
 
675 
SIGNAL("op1_o")
676 
{
677 
        VALUE_TYPE = NINE_LEVEL_BIT;
678 
        SIGNAL_TYPE = SINGLE_BIT;
679 
        WIDTH = 1;
680 
        LSB_INDEX = -1;
681 
        DIRECTION = OUTPUT;
682 
        PARENT = "";
683 
}
684 
 
685 
SIGNAL("rst_i")
686 
{
687 
        VALUE_TYPE = NINE_LEVEL_BIT;
688 
        SIGNAL_TYPE = SINGLE_BIT;
689 
        WIDTH = 1;
690 
        LSB_INDEX = -1;
691 
        DIRECTION = INPUT;
692 
        PARENT = "";
693 
}
694 
 
695 
SIGNAL("we_o")
696 
{
697 
        VALUE_TYPE = NINE_LEVEL_BIT;
698 
        SIGNAL_TYPE = SINGLE_BIT;
699 
        WIDTH = 1;
700 
        LSB_INDEX = -1;
701 
        DIRECTION = OUTPUT;
702 
        PARENT = "";
703 
}
704 
 
705 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[11]")
706 
{
707 
        NODE
708 
        {
709 
                REPEAT = 1;
710 
                LEVEL U FOR 100000.0;
711 
        }
712 
}
713 
 
714 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[10]")
715 
{
716 
        NODE
717 
        {
718 
                REPEAT = 1;
719 
                LEVEL U FOR 100000.0;
720 
        }
721 
}
722 
 
723 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[9]")
724 
{
725 
        NODE
726 
        {
727 
                REPEAT = 1;
728 
                LEVEL U FOR 100000.0;
729 
        }
730 
}
731 
 
732 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[8]")
733 
{
734 
        NODE
735 
        {
736 
                REPEAT = 1;
737 
                LEVEL U FOR 100000.0;
738 
        }
739 
}
740 
 
741 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[7]")
742 
{
743 
        NODE
744 
        {
745 
                REPEAT = 1;
746 
                LEVEL U FOR 100000.0;
747 
        }
748 
}
749 
 
750 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[6]")
751 
{
752 
        NODE
753 
        {
754 
                REPEAT = 1;
755 
                LEVEL U FOR 100000.0;
756 
        }
757 
}
758 
 
759 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[5]")
760 
{
761 
        NODE
762 
        {
763 
                REPEAT = 1;
764 
                LEVEL U FOR 100000.0;
765 
        }
766 
}
767 
 
768 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[4]")
769 
{
770 
        NODE
771 
        {
772 
                REPEAT = 1;
773 
                LEVEL U FOR 100000.0;
774 
        }
775 
}
776 
 
777 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[3]")
778 
{
779 
        NODE
780 
        {
781 
                REPEAT = 1;
782 
                LEVEL U FOR 100000.0;
783 
        }
784 
}
785 
 
786 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[2]")
787 
{
788 
        NODE
789 
        {
790 
                REPEAT = 1;
791 
                LEVEL U FOR 100000.0;
792 
        }
793 
}
794 
 
795 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[1]")
796 
{
797 
        NODE
798 
        {
799 
                REPEAT = 1;
800 
                LEVEL U FOR 100000.0;
801 
        }
802 
}
803 
 
804 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[0]")
805 
{
806 
        NODE
807 
        {
808 
                REPEAT = 1;
809 
                LEVEL U FOR 100000.0;
810 
        }
811 
}
812 
 
813 
TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[8]")
814 
{
815 
        NODE
816 
        {
817 
                REPEAT = 1;
818 
                LEVEL U FOR 100000.0;
819 
        }
820 
}
821 
 
822 
TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[7]")
823 
{
824 
        NODE
825 
        {
826 
                REPEAT = 1;
827 
                LEVEL U FOR 100000.0;
828 
        }
829 
}
830 
 
831 
TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[6]")
832 
{
833 
        NODE
834 
        {
835 
                REPEAT = 1;
836 
                LEVEL U FOR 100000.0;
837 
        }
838 
}
839 
 
840 
TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[5]")
841 
{
842 
        NODE
843 
        {
844 
                REPEAT = 1;
845 
                LEVEL U FOR 100000.0;
846 
        }
847 
}
848 
 
849 
TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[4]")
850 
{
851 
        NODE
852 
        {
853 
                REPEAT = 1;
854 
                LEVEL U FOR 100000.0;
855 
        }
856 
}
857 
 
858 
TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[3]")
859 
{
860 
        NODE
861 
        {
862 
                REPEAT = 1;
863 
                LEVEL U FOR 100000.0;
864 
        }
865 
}
866 
 
867 
TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[2]")
868 
{
869 
        NODE
870 
        {
871 
                REPEAT = 1;
872 
                LEVEL U FOR 100000.0;
873 
        }
874 
}
875 
 
876 
TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[1]")
877 
{
878 
        NODE
879 
        {
880 
                REPEAT = 1;
881 
                LEVEL U FOR 100000.0;
882 
        }
883 
}
884 
 
885 
TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[0]")
886 
{
887 
        NODE
888 
        {
889 
                REPEAT = 1;
890 
                LEVEL U FOR 100000.0;
891 
        }
892 
}
893 
 
894 
TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[8]")
895 
{
896 
        NODE
897 
        {
898 
                REPEAT = 1;
899 
                LEVEL U FOR 100000.0;
900 
        }
901 
}
902 
 
903 
TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[7]")
904 
{
905 
        NODE
906 
        {
907 
                REPEAT = 1;
908 
                LEVEL U FOR 100000.0;
909 
        }
910 
}
911 
 
912 
TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[6]")
913 
{
914 
        NODE
915 
        {
916 
                REPEAT = 1;
917 
                LEVEL U FOR 100000.0;
918 
        }
919 
}
920 
 
921 
TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[5]")
922 
{
923 
        NODE
924 
        {
925 
                REPEAT = 1;
926 
                LEVEL U FOR 100000.0;
927 
        }
928 
}
929 
 
930 
TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[4]")
931 
{
932 
        NODE
933 
        {
934 
                REPEAT = 1;
935 
                LEVEL U FOR 100000.0;
936 
        }
937 
}
938 
 
939 
TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[3]")
940 
{
941 
        NODE
942 
        {
943 
                REPEAT = 1;
944 
                LEVEL U FOR 100000.0;
945 
        }
946 
}
947 
 
948 
TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[2]")
949 
{
950 
        NODE
951 
        {
952 
                REPEAT = 1;
953 
                LEVEL U FOR 100000.0;
954 
        }
955 
}
956 
 
957 
TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[1]")
958 
{
959 
        NODE
960 
        {
961 
                REPEAT = 1;
962 
                LEVEL U FOR 100000.0;
963 
        }
964 
}
965 
 
966 
TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[0]")
967 
{
968 
        NODE
969 
        {
970 
                REPEAT = 1;
971 
                LEVEL U FOR 100000.0;
972 
        }
973 
}
974 
 
975 
TRANSITION_LIST("usimplez_cpu:cpu|co_reg_s[2]")
976 
{
977 
        NODE
978 
        {
979 
                REPEAT = 1;
980 
                LEVEL U FOR 100000.0;
981 
        }
982 
}
983 
 
984 
TRANSITION_LIST("usimplez_cpu:cpu|co_reg_s[1]")
985 
{
986 
        NODE
987 
        {
988 
                REPEAT = 1;
989 
                LEVEL U FOR 100000.0;
990 
        }
991 
}
992 
 
993 
TRANSITION_LIST("usimplez_cpu:cpu|co_reg_s[0]")
994 
{
995 
        NODE
996 
        {
997 
                REPEAT = 1;
998 
                LEVEL U FOR 100000.0;
999 
        }
1000 
}
1001 
 
1002 
TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[8]")
1003 
{
1004 
        NODE
1005 
        {
1006 
                REPEAT = 1;
1007 
                LEVEL U FOR 100000.0;
1008 
        }
1009 
}
1010 
 
1011 
TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[7]")
1012 
{
1013 
        NODE
1014 
        {
1015 
                REPEAT = 1;
1016 
                LEVEL U FOR 100000.0;
1017 
        }
1018 
}
1019 
 
1020 
TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[6]")
1021 
{
1022 
        NODE
1023 
        {
1024 
                REPEAT = 1;
1025 
                LEVEL U FOR 100000.0;
1026 
        }
1027 
}
1028 
 
1029 
TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[5]")
1030 
{
1031 
        NODE
1032 
        {
1033 
                REPEAT = 1;
1034 
                LEVEL U FOR 100000.0;
1035 
        }
1036 
}
1037 
 
1038 
TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[4]")
1039 
{
1040 
        NODE
1041 
        {
1042 
                REPEAT = 1;
1043 
                LEVEL U FOR 100000.0;
1044 
        }
1045 
}
1046 
 
1047 
TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[3]")
1048 
{
1049 
        NODE
1050 
        {
1051 
                REPEAT = 1;
1052 
                LEVEL U FOR 100000.0;
1053 
        }
1054 
}
1055 
 
1056 
TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[2]")
1057 
{
1058 
        NODE
1059 
        {
1060 
                REPEAT = 1;
1061 
                LEVEL U FOR 100000.0;
1062 
        }
1063 
}
1064 
 
1065 
TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[1]")
1066 
{
1067 
        NODE
1068 
        {
1069 
                REPEAT = 1;
1070 
                LEVEL U FOR 100000.0;
1071 
        }
1072 
}
1073 
 
1074 
TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[0]")
1075 
{
1076 
        NODE
1077 
        {
1078 
                REPEAT = 1;
1079 
                LEVEL U FOR 100000.0;
1080 
        }
1081 
}
1082 
 
1083 
TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[11]")
1084 
{
1085 
        NODE
1086 
        {
1087 
                REPEAT = 1;
1088 
                LEVEL U FOR 100000.0;
1089 
        }
1090 
}
1091 
 
1092 
TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[10]")
1093 
{
1094 
        NODE
1095 
        {
1096 
                REPEAT = 1;
1097 
                LEVEL U FOR 100000.0;
1098 
        }
1099 
}
1100 
 
1101 
TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[9]")
1102 
{
1103 
        NODE
1104 
        {
1105 
                REPEAT = 1;
1106 
                LEVEL U FOR 100000.0;
1107 
        }
1108 
}
1109 
 
1110 
TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[8]")
1111 
{
1112 
        NODE
1113 
        {
1114 
                REPEAT = 1;
1115 
                LEVEL U FOR 100000.0;
1116 
        }
1117 
}
1118 
 
1119 
TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[7]")
1120 
{
1121 
        NODE
1122 
        {
1123 
                REPEAT = 1;
1124 
                LEVEL U FOR 100000.0;
1125 
        }
1126 
}
1127 
 
1128 
TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[6]")
1129 
{
1130 
        NODE
1131 
        {
1132 
                REPEAT = 1;
1133 
                LEVEL U FOR 100000.0;
1134 
        }
1135 
}
1136 
 
1137 
TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[5]")
1138 
{
1139 
        NODE
1140 
        {
1141 
                REPEAT = 1;
1142 
                LEVEL U FOR 100000.0;
1143 
        }
1144 
}
1145 
 
1146 
TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[4]")
1147 
{
1148 
        NODE
1149 
        {
1150 
                REPEAT = 1;
1151 
                LEVEL U FOR 100000.0;
1152 
        }
1153 
}
1154 
 
1155 
TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[3]")
1156 
{
1157 
        NODE
1158 
        {
1159 
                REPEAT = 1;
1160 
                LEVEL U FOR 100000.0;
1161 
        }
1162 
}
1163 
 
1164 
TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[2]")
1165 
{
1166 
        NODE
1167 
        {
1168 
                REPEAT = 1;
1169 
                LEVEL U FOR 100000.0;
1170 
        }
1171 
}
1172 
 
1173 
TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[1]")
1174 
{
1175 
        NODE
1176 
        {
1177 
                REPEAT = 1;
1178 
                LEVEL U FOR 100000.0;
1179 
        }
1180 
}
1181 
 
1182 
TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[0]")
1183 
{
1184 
        NODE
1185 
        {
1186 
                REPEAT = 1;
1187 
                LEVEL U FOR 100000.0;
1188 
        }
1189 
}
1190 
 
1191 
TRANSITION_LIST("clk_i")
1192 
{
1193 
        NODE
1194 
        {
1195 
                REPEAT = 1;
1196 
                NODE
1197 
                {
1198 
                        REPEAT = 2000;
1199 
                        LEVEL 0 FOR 25.0;
1200 
                        LEVEL 1 FOR 25.0;
1201 
                }
1202 
        }
1203 
}
1204 
 
1205 
TRANSITION_LIST("in0_o")
1206 
{
1207 
        NODE
1208 
        {
1209 
                REPEAT = 1;
1210 
                LEVEL X FOR 100000.0;
1211 
        }
1212 
}
1213 
 
1214 
TRANSITION_LIST("in1_o")
1215 
{
1216 
        NODE
1217 
        {
1218 
                REPEAT = 1;
1219 
                LEVEL X FOR 100000.0;
1220 
        }
1221 
}
1222 
 
1223 
TRANSITION_LIST("op0_o")
1224 
{
1225 
        NODE
1226 
        {
1227 
                REPEAT = 1;
1228 
                LEVEL X FOR 100000.0;
1229 
        }
1230 
}
1231 
 
1232 
TRANSITION_LIST("op1_o")
1233 
{
1234 
        NODE
1235 
        {
1236 
                REPEAT = 1;
1237 
                LEVEL X FOR 100000.0;
1238 
        }
1239 
}
1240 
 
1241 
TRANSITION_LIST("rst_i")
1242 
{
1243 
        NODE
1244 
        {
1245 
                REPEAT = 1;
1246 
                LEVEL 0 FOR 4.0;
1247 
                LEVEL 1 FOR 11.6;
1248 
                LEVEL 0 FOR 99984.4;
1249 
        }
1250 
}
1251 
 
1252 
TRANSITION_LIST("we_o")
1253 
{
1254 
        NODE
1255 
        {
1256 
                REPEAT = 1;
1257 
                LEVEL X FOR 100000.0;
1258 
        }
1259 
}
1260 
 
1261 
DISPLAY_LINE
1262 
{
1263 
        CHANNEL = "rst_i";
1264 
        EXPAND_STATUS = COLLAPSED;
1265 
        RADIX = Unsigned;
1266 
        TREE_INDEX = 0;
1267 
        TREE_LEVEL = 0;
1268 
}
1269 
 
1270 
DISPLAY_LINE
1271 
{
1272 
        CHANNEL = "clk_i";
1273 
        EXPAND_STATUS = COLLAPSED;
1274 
        RADIX = Unsigned;
1275 
        TREE_INDEX = 1;
1276 
        TREE_LEVEL = 0;
1277 
}
1278 
 
1279 
DISPLAY_LINE
1280 
{
1281 
        CHANNEL = "we_o";
1282 
        EXPAND_STATUS = COLLAPSED;
1283 
        RADIX = Unsigned;
1284 
        TREE_INDEX = 2;
1285 
        TREE_LEVEL = 0;
1286 
}
1287 
 
1288 
DISPLAY_LINE
1289 
{
1290 
        CHANNEL = "in0_o";
1291 
        EXPAND_STATUS = COLLAPSED;
1292 
        RADIX = Unsigned;
1293 
        TREE_INDEX = 3;
1294 
        TREE_LEVEL = 0;
1295 
}
1296 
 
1297 
DISPLAY_LINE
1298 
{
1299 
        CHANNEL = "in1_o";
1300 
        EXPAND_STATUS = COLLAPSED;
1301 
        RADIX = Unsigned;
1302 
        TREE_INDEX = 4;
1303 
        TREE_LEVEL = 0;
1304 
}
1305 
 
1306 
DISPLAY_LINE
1307 
{
1308 
        CHANNEL = "op0_o";
1309 
        EXPAND_STATUS = COLLAPSED;
1310 
        RADIX = Unsigned;
1311 
        TREE_INDEX = 5;
1312 
        TREE_LEVEL = 0;
1313 
}
1314 
 
1315 
DISPLAY_LINE
1316 
{
1317 
        CHANNEL = "op1_o";
1318 
        EXPAND_STATUS = COLLAPSED;
1319 
        RADIX = Unsigned;
1320 
        TREE_INDEX = 6;
1321 
        TREE_LEVEL = 0;
1322 
}
1323 
 
1324 
DISPLAY_LINE
1325 
{
1326 
        CHANNEL = "usimplez_cpu:cpu|acumulador";
1327 
        EXPAND_STATUS = COLLAPSED;
1328 
        RADIX = Unsigned;
1329 
        TREE_INDEX = 7;
1330 
        TREE_LEVEL = 0;
1331 
        CHILDREN = 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19;
1332 
}
1333 
 
1334 
DISPLAY_LINE
1335 
{
1336 
        CHANNEL = "usimplez_cpu:cpu|acumulador[11]";
1337 
        EXPAND_STATUS = COLLAPSED;
1338 
        RADIX = Unsigned;
1339 
        TREE_INDEX = 8;
1340 
        TREE_LEVEL = 1;
1341 
        PARENT = 7;
1342 
}
1343 
 
1344 
DISPLAY_LINE
1345 
{
1346 
        CHANNEL = "usimplez_cpu:cpu|acumulador[10]";
1347 
        EXPAND_STATUS = COLLAPSED;
1348 
        RADIX = Unsigned;
1349 
        TREE_INDEX = 9;
1350 
        TREE_LEVEL = 1;
1351 
        PARENT = 7;
1352 
}
1353 
 
1354 
DISPLAY_LINE
1355 
{
1356 
        CHANNEL = "usimplez_cpu:cpu|acumulador[9]";
1357 
        EXPAND_STATUS = COLLAPSED;
1358 
        RADIX = Unsigned;
1359 
        TREE_INDEX = 10;
1360 
        TREE_LEVEL = 1;
1361 
        PARENT = 7;
1362 
}
1363 
 
1364 
DISPLAY_LINE
1365 
{
1366 
        CHANNEL = "usimplez_cpu:cpu|acumulador[8]";
1367 
        EXPAND_STATUS = COLLAPSED;
1368 
        RADIX = Unsigned;
1369 
        TREE_INDEX = 11;
1370 
        TREE_LEVEL = 1;
1371 
        PARENT = 7;
1372 
}
1373 
 
1374 
DISPLAY_LINE
1375 
{
1376 
        CHANNEL = "usimplez_cpu:cpu|acumulador[7]";
1377 
        EXPAND_STATUS = COLLAPSED;
1378 
        RADIX = Unsigned;
1379 
        TREE_INDEX = 12;
1380 
        TREE_LEVEL = 1;
1381 
        PARENT = 7;
1382 
}
1383 
 
1384 
DISPLAY_LINE
1385 
{
1386 
        CHANNEL = "usimplez_cpu:cpu|acumulador[6]";
1387 
        EXPAND_STATUS = COLLAPSED;
1388 
        RADIX = Unsigned;
1389 
        TREE_INDEX = 13;
1390 
        TREE_LEVEL = 1;
1391 
        PARENT = 7;
1392 
}
1393 
 
1394 
DISPLAY_LINE
1395 
{
1396 
        CHANNEL = "usimplez_cpu:cpu|acumulador[5]";
1397 
        EXPAND_STATUS = COLLAPSED;
1398 
        RADIX = Unsigned;
1399 
        TREE_INDEX = 14;
1400 
        TREE_LEVEL = 1;
1401 
        PARENT = 7;
1402 
}
1403 
 
1404 
DISPLAY_LINE
1405 
{
1406 
        CHANNEL = "usimplez_cpu:cpu|acumulador[4]";
1407 
        EXPAND_STATUS = COLLAPSED;
1408 
        RADIX = Unsigned;
1409 
        TREE_INDEX = 15;
1410 
        TREE_LEVEL = 1;
1411 
        PARENT = 7;
1412 
}
1413 
 
1414 
DISPLAY_LINE
1415 
{
1416 
        CHANNEL = "usimplez_cpu:cpu|acumulador[3]";
1417 
        EXPAND_STATUS = COLLAPSED;
1418 
        RADIX = Unsigned;
1419 
        TREE_INDEX = 16;
1420 
        TREE_LEVEL = 1;
1421 
        PARENT = 7;
1422 
}
1423 
 
1424 
DISPLAY_LINE
1425 
{
1426 
        CHANNEL = "usimplez_cpu:cpu|acumulador[2]";
1427 
        EXPAND_STATUS = COLLAPSED;
1428 
        RADIX = Unsigned;
1429 
        TREE_INDEX = 17;
1430 
        TREE_LEVEL = 1;
1431 
        PARENT = 7;
1432 
}
1433 
 
1434 
DISPLAY_LINE
1435 
{
1436 
        CHANNEL = "usimplez_cpu:cpu|acumulador[1]";
1437 
        EXPAND_STATUS = COLLAPSED;
1438 
        RADIX = Unsigned;
1439 
        TREE_INDEX = 18;
1440 
        TREE_LEVEL = 1;
1441 
        PARENT = 7;
1442 
}
1443 
 
1444 
DISPLAY_LINE
1445 
{
1446 
        CHANNEL = "usimplez_cpu:cpu|acumulador[0]";
1447 
        EXPAND_STATUS = COLLAPSED;
1448 
        RADIX = Unsigned;
1449 
        TREE_INDEX = 19;
1450 
        TREE_LEVEL = 1;
1451 
        PARENT = 7;
1452 
}
1453 
 
1454 
DISPLAY_LINE
1455 
{
1456 
        CHANNEL = "usimplez_cpu:cpu|addr_bus_o";
1457 
        EXPAND_STATUS = COLLAPSED;
1458 
        RADIX = Unsigned;
1459 
        TREE_INDEX = 20;
1460 
        TREE_LEVEL = 0;
1461 
        CHILDREN = 21, 22, 23, 24, 25, 26, 27, 28, 29;
1462 
}
1463 
 
1464 
DISPLAY_LINE
1465 
{
1466 
        CHANNEL = "usimplez_cpu:cpu|addr_bus_o[8]";
1467 
        EXPAND_STATUS = COLLAPSED;
1468 
        RADIX = Unsigned;
1469 
        TREE_INDEX = 21;
1470 
        TREE_LEVEL = 1;
1471 
        PARENT = 20;
1472 
}
1473 
 
1474 
DISPLAY_LINE
1475 
{
1476 
        CHANNEL = "usimplez_cpu:cpu|addr_bus_o[7]";
1477 
        EXPAND_STATUS = COLLAPSED;
1478 
        RADIX = Unsigned;
1479 
        TREE_INDEX = 22;
1480 
        TREE_LEVEL = 1;
1481 
        PARENT = 20;
1482 
}
1483 
 
1484 
DISPLAY_LINE
1485 
{
1486 
        CHANNEL = "usimplez_cpu:cpu|addr_bus_o[6]";
1487 
        EXPAND_STATUS = COLLAPSED;
1488 
        RADIX = Unsigned;
1489 
        TREE_INDEX = 23;
1490 
        TREE_LEVEL = 1;
1491 
        PARENT = 20;
1492 
}
1493 
 
1494 
DISPLAY_LINE
1495 
{
1496 
        CHANNEL = "usimplez_cpu:cpu|addr_bus_o[5]";
1497 
        EXPAND_STATUS = COLLAPSED;
1498 
        RADIX = Unsigned;
1499 
        TREE_INDEX = 24;
1500 
        TREE_LEVEL = 1;
1501 
        PARENT = 20;
1502 
}
1503 
 
1504 
DISPLAY_LINE
1505 
{
1506 
        CHANNEL = "usimplez_cpu:cpu|addr_bus_o[4]";
1507 
        EXPAND_STATUS = COLLAPSED;
1508 
        RADIX = Unsigned;
1509 
        TREE_INDEX = 25;
1510 
        TREE_LEVEL = 1;
1511 
        PARENT = 20;
1512 
}
1513 
 
1514 
DISPLAY_LINE
1515 
{
1516 
        CHANNEL = "usimplez_cpu:cpu|addr_bus_o[3]";
1517 
        EXPAND_STATUS = COLLAPSED;
1518 
        RADIX = Unsigned;
1519 
        TREE_INDEX = 26;
1520 
        TREE_LEVEL = 1;
1521 
        PARENT = 20;
1522 
}
1523 
 
1524 
DISPLAY_LINE
1525 
{
1526 
        CHANNEL = "usimplez_cpu:cpu|addr_bus_o[2]";
1527 
        EXPAND_STATUS = COLLAPSED;
1528 
        RADIX = Unsigned;
1529 
        TREE_INDEX = 27;
1530 
        TREE_LEVEL = 1;
1531 
        PARENT = 20;
1532 
}
1533 
 
1534 
DISPLAY_LINE
1535 
{
1536 
        CHANNEL = "usimplez_cpu:cpu|addr_bus_o[1]";
1537 
        EXPAND_STATUS = COLLAPSED;
1538 
        RADIX = Unsigned;
1539 
        TREE_INDEX = 28;
1540 
        TREE_LEVEL = 1;
1541 
        PARENT = 20;
1542 
}
1543 
 
1544 
DISPLAY_LINE
1545 
{
1546 
        CHANNEL = "usimplez_cpu:cpu|addr_bus_o[0]";
1547 
        EXPAND_STATUS = COLLAPSED;
1548 
        RADIX = Unsigned;
1549 
        TREE_INDEX = 29;
1550 
        TREE_LEVEL = 1;
1551 
        PARENT = 20;
1552 
}
1553 
 
1554 
DISPLAY_LINE
1555 
{
1556 
        CHANNEL = "usimplez_cpu:cpu|cd_reg_s";
1557 
        EXPAND_STATUS = COLLAPSED;
1558 
        RADIX = Unsigned;
1559 
        TREE_INDEX = 30;
1560 
        TREE_LEVEL = 0;
1561 
        CHILDREN = 31, 32, 33, 34, 35, 36, 37, 38, 39;
1562 
}
1563 
 
1564 
DISPLAY_LINE
1565 
{
1566 
        CHANNEL = "usimplez_cpu:cpu|cd_reg_s[8]";
1567 
        EXPAND_STATUS = COLLAPSED;
1568 
        RADIX = Unsigned;
1569 
        TREE_INDEX = 31;
1570 
        TREE_LEVEL = 1;
1571 
        PARENT = 30;
1572 
}
1573 
 
1574 
DISPLAY_LINE
1575 
{
1576 
        CHANNEL = "usimplez_cpu:cpu|cd_reg_s[7]";
1577 
        EXPAND_STATUS = COLLAPSED;
1578 
        RADIX = Unsigned;
1579 
        TREE_INDEX = 32;
1580 
        TREE_LEVEL = 1;
1581 
        PARENT = 30;
1582 
}
1583 
 
1584 
DISPLAY_LINE
1585 
{
1586 
        CHANNEL = "usimplez_cpu:cpu|cd_reg_s[6]";
1587 
        EXPAND_STATUS = COLLAPSED;
1588 
        RADIX = Unsigned;
1589 
        TREE_INDEX = 33;
1590 
        TREE_LEVEL = 1;
1591 
        PARENT = 30;
1592 
}
1593 
 
1594 
DISPLAY_LINE
1595 
{
1596 
        CHANNEL = "usimplez_cpu:cpu|cd_reg_s[5]";
1597 
        EXPAND_STATUS = COLLAPSED;
1598 
        RADIX = Unsigned;
1599 
        TREE_INDEX = 34;
1600 
        TREE_LEVEL = 1;
1601 
        PARENT = 30;
1602 
}
1603 
 
1604 
DISPLAY_LINE
1605 
{
1606 
        CHANNEL = "usimplez_cpu:cpu|cd_reg_s[4]";
1607 
        EXPAND_STATUS = COLLAPSED;
1608 
        RADIX = Unsigned;
1609 
        TREE_INDEX = 35;
1610 
        TREE_LEVEL = 1;
1611 
        PARENT = 30;
1612 
}
1613 
 
1614 
DISPLAY_LINE
1615 
{
1616 
        CHANNEL = "usimplez_cpu:cpu|cd_reg_s[3]";
1617 
        EXPAND_STATUS = COLLAPSED;
1618 
        RADIX = Unsigned;
1619 
        TREE_INDEX = 36;
1620 
        TREE_LEVEL = 1;
1621 
        PARENT = 30;
1622 
}
1623 
 
1624 
DISPLAY_LINE
1625 
{
1626 
        CHANNEL = "usimplez_cpu:cpu|cd_reg_s[2]";
1627 
        EXPAND_STATUS = COLLAPSED;
1628 
        RADIX = Unsigned;
1629 
        TREE_INDEX = 37;
1630 
        TREE_LEVEL = 1;
1631 
        PARENT = 30;
1632 
}
1633 
 
1634 
DISPLAY_LINE
1635 
{
1636 
        CHANNEL = "usimplez_cpu:cpu|cd_reg_s[1]";
1637 
        EXPAND_STATUS = COLLAPSED;
1638 
        RADIX = Unsigned;
1639 
        TREE_INDEX = 38;
1640 
        TREE_LEVEL = 1;
1641 
        PARENT = 30;
1642 
}
1643 
 
1644 
DISPLAY_LINE
1645 
{
1646 
        CHANNEL = "usimplez_cpu:cpu|cd_reg_s[0]";
1647 
        EXPAND_STATUS = COLLAPSED;
1648 
        RADIX = Unsigned;
1649 
        TREE_INDEX = 39;
1650 
        TREE_LEVEL = 1;
1651 
        PARENT = 30;
1652 
}
1653 
 
1654 
DISPLAY_LINE
1655 
{
1656 
        CHANNEL = "usimplez_cpu:cpu|co_reg_s";
1657 
        EXPAND_STATUS = COLLAPSED;
1658 
        RADIX = Unsigned;
1659 
        TREE_INDEX = 40;
1660 
        TREE_LEVEL = 0;
1661 
        CHILDREN = 41, 42, 43;
1662 
}
1663 
 
1664 
DISPLAY_LINE
1665 
{
1666 
        CHANNEL = "usimplez_cpu:cpu|co_reg_s[2]";
1667 
        EXPAND_STATUS = COLLAPSED;
1668 
        RADIX = Unsigned;
1669 
        TREE_INDEX = 41;
1670 
        TREE_LEVEL = 1;
1671 
        PARENT = 40;
1672 
}
1673 
 
1674 
DISPLAY_LINE
1675 
{
1676 
        CHANNEL = "usimplez_cpu:cpu|co_reg_s[1]";
1677 
        EXPAND_STATUS = COLLAPSED;
1678 
        RADIX = Unsigned;
1679 
        TREE_INDEX = 42;
1680 
        TREE_LEVEL = 1;
1681 
        PARENT = 40;
1682 
}
1683 
 
1684 
DISPLAY_LINE
1685 
{
1686 
        CHANNEL = "usimplez_cpu:cpu|co_reg_s[0]";
1687 
        EXPAND_STATUS = COLLAPSED;
1688 
        RADIX = Unsigned;
1689 
        TREE_INDEX = 43;
1690 
        TREE_LEVEL = 1;
1691 
        PARENT = 40;
1692 
}
1693 
 
1694 
DISPLAY_LINE
1695 
{
1696 
        CHANNEL = "usimplez_cpu:cpu|cp_reg_s";
1697 
        EXPAND_STATUS = COLLAPSED;
1698 
        RADIX = Unsigned;
1699 
        TREE_INDEX = 44;
1700 
        TREE_LEVEL = 0;
1701 
        CHILDREN = 45, 46, 47, 48, 49, 50, 51, 52, 53;
1702 
}
1703 
 
1704 
DISPLAY_LINE
1705 
{
1706 
        CHANNEL = "usimplez_cpu:cpu|cp_reg_s[8]";
1707 
        EXPAND_STATUS = COLLAPSED;
1708 
        RADIX = Unsigned;
1709 
        TREE_INDEX = 45;
1710 
        TREE_LEVEL = 1;
1711 
        PARENT = 44;
1712 
}
1713 
 
1714 
DISPLAY_LINE
1715 
{
1716 
        CHANNEL = "usimplez_cpu:cpu|cp_reg_s[7]";
1717 
        EXPAND_STATUS = COLLAPSED;
1718 
        RADIX = Unsigned;
1719 
        TREE_INDEX = 46;
1720 
        TREE_LEVEL = 1;
1721 
        PARENT = 44;
1722 
}
1723 
 
1724 
DISPLAY_LINE
1725 
{
1726 
        CHANNEL = "usimplez_cpu:cpu|cp_reg_s[6]";
1727 
        EXPAND_STATUS = COLLAPSED;
1728 
        RADIX = Unsigned;
1729 
        TREE_INDEX = 47;
1730 
        TREE_LEVEL = 1;
1731 
        PARENT = 44;
1732 
}
1733 
 
1734 
DISPLAY_LINE
1735 
{
1736 
        CHANNEL = "usimplez_cpu:cpu|cp_reg_s[5]";
1737 
        EXPAND_STATUS = COLLAPSED;
1738 
        RADIX = Unsigned;
1739 
        TREE_INDEX = 48;
1740 
        TREE_LEVEL = 1;
1741 
        PARENT = 44;
1742 
}
1743 
 
1744 
DISPLAY_LINE
1745 
{
1746 
        CHANNEL = "usimplez_cpu:cpu|cp_reg_s[4]";
1747 
        EXPAND_STATUS = COLLAPSED;
1748 
        RADIX = Unsigned;
1749 
        TREE_INDEX = 49;
1750 
        TREE_LEVEL = 1;
1751 
        PARENT = 44;
1752 
}
1753 
 
1754 
DISPLAY_LINE
1755 
{
1756 
        CHANNEL = "usimplez_cpu:cpu|cp_reg_s[3]";
1757 
        EXPAND_STATUS = COLLAPSED;
1758 
        RADIX = Unsigned;
1759 
        TREE_INDEX = 50;
1760 
        TREE_LEVEL = 1;
1761 
        PARENT = 44;
1762 
}
1763 
 
1764 
DISPLAY_LINE
1765 
{
1766 
        CHANNEL = "usimplez_cpu:cpu|cp_reg_s[2]";
1767 
        EXPAND_STATUS = COLLAPSED;
1768 
        RADIX = Unsigned;
1769 
        TREE_INDEX = 51;
1770 
        TREE_LEVEL = 1;
1771 
        PARENT = 44;
1772 
}
1773 
 
1774 
DISPLAY_LINE
1775 
{
1776 
        CHANNEL = "usimplez_cpu:cpu|cp_reg_s[1]";
1777 
        EXPAND_STATUS = COLLAPSED;
1778 
        RADIX = Unsigned;
1779 
        TREE_INDEX = 52;
1780 
        TREE_LEVEL = 1;
1781 
        PARENT = 44;
1782 
}
1783 
 
1784 
DISPLAY_LINE
1785 
{
1786 
        CHANNEL = "usimplez_cpu:cpu|cp_reg_s[0]";
1787 
        EXPAND_STATUS = COLLAPSED;
1788 
        RADIX = Unsigned;
1789 
        TREE_INDEX = 53;
1790 
        TREE_LEVEL = 1;
1791 
        PARENT = 44;
1792 
}
1793 
 
1794 
DISPLAY_LINE
1795 
{
1796 
        CHANNEL = "usimplez_cpu:cpu|data_bus_o";
1797 
        EXPAND_STATUS = COLLAPSED;
1798 
        RADIX = Unsigned;
1799 
        TREE_INDEX = 54;
1800 
        TREE_LEVEL = 0;
1801 
        CHILDREN = 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66;
1802 
}
1803 
 
1804 
DISPLAY_LINE
1805 
{
1806 
        CHANNEL = "usimplez_cpu:cpu|data_bus_o[11]";
1807 
        EXPAND_STATUS = COLLAPSED;
1808 
        RADIX = Unsigned;
1809 
        TREE_INDEX = 55;
1810 
        TREE_LEVEL = 1;
1811 
        PARENT = 54;
1812 
}
1813 
 
1814 
DISPLAY_LINE
1815 
{
1816 
        CHANNEL = "usimplez_cpu:cpu|data_bus_o[10]";
1817 
        EXPAND_STATUS = COLLAPSED;
1818 
        RADIX = Unsigned;
1819 
        TREE_INDEX = 56;
1820 
        TREE_LEVEL = 1;
1821 
        PARENT = 54;
1822 
}
1823 
 
1824 
DISPLAY_LINE
1825 
{
1826 
        CHANNEL = "usimplez_cpu:cpu|data_bus_o[9]";
1827 
        EXPAND_STATUS = COLLAPSED;
1828 
        RADIX = Unsigned;
1829 
        TREE_INDEX = 57;
1830 
        TREE_LEVEL = 1;
1831 
        PARENT = 54;
1832 
}
1833 
 
1834 
DISPLAY_LINE
1835 
{
1836 
        CHANNEL = "usimplez_cpu:cpu|data_bus_o[8]";
1837 
        EXPAND_STATUS = COLLAPSED;
1838 
        RADIX = Unsigned;
1839 
        TREE_INDEX = 58;
1840 
        TREE_LEVEL = 1;
1841 
        PARENT = 54;
1842 
}
1843 
 
1844 
DISPLAY_LINE
1845 
{
1846 
        CHANNEL = "usimplez_cpu:cpu|data_bus_o[7]";
1847 
        EXPAND_STATUS = COLLAPSED;
1848 
        RADIX = Unsigned;
1849 
        TREE_INDEX = 59;
1850 
        TREE_LEVEL = 1;
1851 
        PARENT = 54;
1852 
}
1853 
 
1854 
DISPLAY_LINE
1855 
{
1856 
        CHANNEL = "usimplez_cpu:cpu|data_bus_o[6]";
1857 
        EXPAND_STATUS = COLLAPSED;
1858 
        RADIX = Unsigned;
1859 
        TREE_INDEX = 60;
1860 
        TREE_LEVEL = 1;
1861 
        PARENT = 54;
1862 
}
1863 
 
1864 
DISPLAY_LINE
1865 
{
1866 
        CHANNEL = "usimplez_cpu:cpu|data_bus_o[5]";
1867 
        EXPAND_STATUS = COLLAPSED;
1868 
        RADIX = Unsigned;
1869 
        TREE_INDEX = 61;
1870 
        TREE_LEVEL = 1;
1871 
        PARENT = 54;
1872 
}
1873 
 
1874 
DISPLAY_LINE
1875 
{
1876 
        CHANNEL = "usimplez_cpu:cpu|data_bus_o[4]";
1877 
        EXPAND_STATUS = COLLAPSED;
1878 
        RADIX = Unsigned;
1879 
        TREE_INDEX = 62;
1880 
        TREE_LEVEL = 1;
1881 
        PARENT = 54;
1882 
}
1883 
 
1884 
DISPLAY_LINE
1885 
{
1886 
        CHANNEL = "usimplez_cpu:cpu|data_bus_o[3]";
1887 
        EXPAND_STATUS = COLLAPSED;
1888 
        RADIX = Unsigned;
1889 
        TREE_INDEX = 63;
1890 
        TREE_LEVEL = 1;
1891 
        PARENT = 54;
1892 
}
1893 
 
1894 
DISPLAY_LINE
1895 
{
1896 
        CHANNEL = "usimplez_cpu:cpu|data_bus_o[2]";
1897 
        EXPAND_STATUS = COLLAPSED;
1898 
        RADIX = Unsigned;
1899 
        TREE_INDEX = 64;
1900 
        TREE_LEVEL = 1;
1901 
        PARENT = 54;
1902 
}
1903 
 
1904 
DISPLAY_LINE
1905 
{
1906 
        CHANNEL = "usimplez_cpu:cpu|data_bus_o[1]";
1907 
        EXPAND_STATUS = COLLAPSED;
1908 
        RADIX = Unsigned;
1909 
        TREE_INDEX = 65;
1910 
        TREE_LEVEL = 1;
1911 
        PARENT = 54;
1912 
}
1913 
 
1914 
DISPLAY_LINE
1915 
{
1916 
        CHANNEL = "usimplez_cpu:cpu|data_bus_o[0]";
1917 
        EXPAND_STATUS = COLLAPSED;
1918 
        RADIX = Unsigned;
1919 
        TREE_INDEX = 66;
1920 
        TREE_LEVEL = 1;
1921 
        PARENT = 54;
1922 
}
1923 
 
1924 
TIME_BAR
1925 
{
1926 
        TIME = 9575;
1927 
        MASTER = TRUE;
1928 
}
1929 
;

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