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121 |
ultro |
module realign (
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| 2 |
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clk,
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| 3 |
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rstn,
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read_req_in,write_req_in,
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| 5 |
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read_req_out,write_req_out,
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read_ack_in,write_ack_in,
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read_ack_out,write_ack_out,
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| 10 |
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addr_in,
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| 11 |
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addr_out,
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| 12 |
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read_data_in,
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read_data_out,
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| 15 |
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write_data_in,
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write_data_out,
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write_sz_in,
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write_msk_out
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| 20 |
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| 21 |
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);
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| 22 |
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input [31:0] write_data_in ,read_data_in ,addr_in;
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output [31:0] write_data_out,read_data_out,addr_out;
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| 25 |
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input rstn,clk;
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input read_req_in,write_req_in,read_ack_in,write_ack_in;
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input [1:0] write_sz_in;
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output [3:0] write_msk_out;
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output write_req_out,read_req_out,read_ack_out,write_ack_out;
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| 31 |
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reg write_req_ff, write_ack_ff, read_req_ff, read_ack_ff;
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reg [31:0] addr_out_ff;
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reg even;
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reg [31:0] read_data_sav;
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reg [31:0] read_data_out_ff,write_data_out_ff;
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reg [3:0] write_msk_ff;
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wire not_align = ((addr_in[1] == 1'b1) || (addr_in[0] == 1'b1)) ? 1'b1 : 1'b0;
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assign read_req_out = not_align ? read_req_ff : read_req_in;
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assign read_ack_out = not_align ? read_ack_ff : read_ack_in;
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assign write_req_out = ((not_align == 1'b1) && (write_sz_in !=2'b00)) ? write_req_ff : write_req_in;
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assign write_ack_out = ((not_align == 1'b1) && (write_sz_in !=2'b00)) ? write_ack_ff : write_ack_in;
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| 45 |
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| 46 |
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assign write_msk_out = ((not_align == 1'b1) && (write_sz_in != 2'b00)) ? write_msk_ff :
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((addr_in[1:0] == 2'b00) && (write_sz_in == 2'b00)) ? 4'b0001 :
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| 48 |
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((addr_in[1:0] == 2'b01) && (write_sz_in == 2'b00)) ? 4'b0010 :
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| 49 |
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((addr_in[1:0] == 2'b10) && (write_sz_in == 2'b00)) ? 4'b0100 :
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| 50 |
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((addr_in[1:0] == 2'b11) && (write_sz_in == 2'b00)) ? 4'b1000 :
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(write_sz_in == 2'b01) ? 4'b0011 :
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4'b1111 ;
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| 53 |
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| 54 |
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assign write_data_out = ((not_align == 1'b1) && (write_sz_in != 2'b00)) ? write_data_out_ff :
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((addr_in[1:0] == 2'b01) && (write_sz_in == 2'b00)) ? {16'h5555,write_data_in[7:0],8'h55} :
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((addr_in[1:0] == 2'b10) && (write_sz_in == 2'b00)) ? { 8'h55,write_data_in[7:0],16'h5555} :
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((addr_in[1:0] == 2'b11) && (write_sz_in == 2'b00)) ? { write_data_in[7:0],24'h555555} :
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write_data_in;
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assign read_data_out = not_align ? read_data_out_ff : read_data_in;
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assign addr_out = ((not_align == 1'b1) && ( read_req_in == 1'b1)) ? addr_out_ff :
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((not_align == 1'b1) && (write_req_in == 1'b1) && (write_sz_in !=2'b00)) ? addr_out_ff :
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{addr_in[31:2],2'b00};
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| 65 |
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always @(posedge clk or negedge rstn)
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if (~rstn)
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begin
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write_req_ff <= 1'b0;
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write_ack_ff <= 1'b0;
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read_req_ff <= 1'b0;
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read_ack_ff <= 1'b0;
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even <= 1'b0;
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write_msk_ff <= 4'b1111;
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read_data_out_ff <= 32'h0;
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write_data_out_ff <= 32'h0;
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end
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else
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begin
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if (write_ack_ff == 1'b1)
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begin
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write_req_ff <= 1'b0;
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write_ack_ff <= 1'b0;
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even <= 1'b0;
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write_msk_ff <= 4'b0000;
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end
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else if (read_ack_ff == 1'b1)
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begin
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read_req_ff <= 1'b0;
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read_ack_ff <= 1'b0;
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even <= 1'b0;
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end
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| 93 |
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else
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if ((not_align == 1'b1) && (read_req_ff == 1'b0) && (read_req_in == 1'b1) && (even == 1'b0))
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begin
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read_req_ff <= 1'b1;
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addr_out_ff <= {addr_in[31:2],2'b00};
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even <= 1'b1;
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end
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| 100 |
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else
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if ((not_align == 1'b1) && (read_req_ff == 1'b1) && (read_ack_in == 1'b1) && (even == 1'b1))
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begin
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addr_out_ff <= {addr_in[31:2],2'b00} + 3'b100;
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read_data_sav<= read_data_in;
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even <= 1'b0;
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end
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else
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if ((not_align == 1'b1) && (read_req_ff == 1'b1) && (read_ack_in == 1'b1) && (even == 1'b0))
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begin
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even <= 1'b0;
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read_ack_ff <= 1'b1;
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read_req_ff <= 1'b0;
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case(addr_in[1:0])
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2'b00: read_data_out_ff <= read_data_sav;
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2'b01: read_data_out_ff <= {read_data_in[ 7:0],read_data_sav[31: 8]};
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2'b10: read_data_out_ff <= {read_data_in[15:0],read_data_sav[31:16]};
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2'b11: read_data_out_ff <= {read_data_in[23:0],read_data_sav[31:24]};
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endcase
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end
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| 120 |
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else
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if ((not_align == 1'b1) && (write_req_ff == 1'b0) && (write_req_in == 1'b1) && (even == 1'b0) && (write_sz_in != 2'b00))
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| 122 |
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begin
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addr_out_ff <= {addr_in[31:2],2'b00};
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even <= 1'b1;
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write_req_ff <= 1'b1;
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| 126 |
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if ((addr_in[1:0] == 2'b01) && (write_sz_in ==2'b01)) begin write_msk_ff <= 4'b0110; write_data_out_ff <= {write_data_in[23:0], 8'b0}; end else
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| 127 |
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if ((addr_in[1:0] == 2'b01) && (write_sz_in ==2'b10)) begin write_msk_ff <= 4'b1110; write_data_out_ff <= {write_data_in[23:0], 8'b0}; end else
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| 128 |
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if ((addr_in[1:0] == 2'b10) && (write_sz_in ==2'b01)) begin write_msk_ff <= 4'b1100; write_data_out_ff <= {write_data_in[15:0],16'b0}; end else
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| 129 |
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if ((addr_in[1:0] == 2'b10) && (write_sz_in ==2'b10)) begin write_msk_ff <= 4'b1100; write_data_out_ff <= {write_data_in[15:0],16'b0}; end else
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| 130 |
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if ((addr_in[1:0] == 2'b11) && (write_sz_in ==2'b01)) begin write_msk_ff <= 4'b1000; write_data_out_ff <= {write_data_in[ 7:0],24'b0}; end else
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| 131 |
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if ((addr_in[1:0] == 2'b11) && (write_sz_in ==2'b10)) begin write_msk_ff <= 4'b1000; write_data_out_ff <= {write_data_in[ 7:0],24'b0}; end
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end
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else
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if ((not_align == 1'b1) && (write_req_ff == 1'b1) && (write_ack_in == 1'b1) && (even == 1'b1))
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begin
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addr_out_ff <= {addr_in[31:2],2'b00} + 3'b100;
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even <= 1'b0;
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if ((addr_in[1:0] == 2'b01) && (write_sz_in ==2'b10)) begin write_msk_ff <= 4'b0001; write_data_out_ff <= {24'b0,write_data_in[31:24]}; end else
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| 139 |
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if ((addr_in[1:0] == 2'b10) && (write_sz_in ==2'b10)) begin write_msk_ff <= 4'b0011; write_data_out_ff <= {16'b0,write_data_in[31:16]}; end else
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| 140 |
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if ((addr_in[1:0] == 2'b11) && (write_sz_in ==2'b01)) begin write_msk_ff <= 4'b0001; write_data_out_ff <= { 8'b0,write_data_in[31: 8]}; end else
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| 141 |
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if ((addr_in[1:0] == 2'b11) && (write_sz_in ==2'b10)) begin write_msk_ff <= 4'b0111; write_data_out_ff <= { 8'b0,write_data_in[31: 8]}; end else
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begin write_msk_ff <= 4'b0000; end
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end
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| 144 |
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else
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if ((not_align == 1'b1) && (write_req_ff == 1'b1) && (write_ack_in == 1'b1) && (even == 1'b0))
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begin
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even <= 1'b0;
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write_ack_ff <= 1'b1;
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write_req_ff <= 1'b0;
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end
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| 151 |
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end
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| 152 |
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| 153 |
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endmodule
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