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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// GRAY counter
module adr_gen ( cke, q, q_bin, rst, clk);
 
   parameter length = 4;
   input cke;
   output reg [length:1] q;
   output [length:1] q_bin;
   input rst;
   input clk;
 
 
   reg  [length:1] qi;
   wire [length:1] q_next;
   assign q_next = qi + {{length-1{1'b0}},1'b1};
 
   always @ (posedge clk or posedge rst)
     if (rst)
       qi <= {length{1'b0}};
     else
     if (cke)
       qi <= q_next;
 
   always @ (posedge clk or posedge rst)
     if (rst)
       q <= {length{1'b0}};
     else
       if (cke)
         q <= (q_next>>1) ^ q_next;
 
   assign q_bin = qi;
 
endmodule
// true dual port RAM, sync
 
 
 
 
module vfifo_dual_port_ram_dc_dw
  (
   d_a,
   q_a,
   adr_a,
   we_a,
   clk_a,
   q_b,
   adr_b,
   d_b,
   we_b,
   clk_b
   );
   parameter DATA_WIDTH = 32;
   parameter ADDR_WIDTH = 8;
   input [(DATA_WIDTH-1):0]      d_a;
   input [(ADDR_WIDTH-1):0]       adr_a;
   input [(ADDR_WIDTH-1):0]       adr_b;
   input                         we_a;
   output [(DATA_WIDTH-1):0]      q_b;
   input [(DATA_WIDTH-1):0]       d_b;
   output reg [(DATA_WIDTH-1):0] q_a;
   input                         we_b;
   input                         clk_a, clk_b;
   reg [(DATA_WIDTH-1):0]         q_b;
   reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
     begin
          q_b <= ram[adr_b];
        if (we_b)
          ram[adr_b] <= d_b;
     end
endmodule
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
module dff_sr ( aclr, aset, clock, data, q);
 
    input         aclr;
    input         aset;
    input         clock;
    input         data;
    output reg    q;
 
   always @ (posedge clock or posedge aclr or posedge aset)
     if (aclr)
       q <= 1'b0;
     else if (aset)
       q <= 1'b1;
     else
       q <= data;
 
endmodule
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
 
   parameter ADDR_WIDTH = 4;
   parameter N = ADDR_WIDTH-1;
 
   parameter Q1 = 2'b00;
   parameter Q2 = 2'b01;
   parameter Q3 = 2'b11;
   parameter Q4 = 2'b10;
 
   parameter going_empty = 1'b0;
   parameter going_full  = 1'b1;
 
   input [N:0]  wptr, rptr;
   output reg   fifo_empty;
   output       fifo_full;
   input        wclk, rclk, rst;
 
 
 
 
 
   reg direction;
 
   reg  direction_set, direction_clr;
 
   wire async_empty, async_full;
   wire fifo_full2;
   reg  fifo_empty2;
 
   // direction_set
   always @ (wptr[N:N-1] or rptr[N:N-1])
     case ({wptr[N:N-1],rptr[N:N-1]})
       {Q1,Q2} : direction_set <= 1'b1;
       {Q2,Q3} : direction_set <= 1'b1;
       {Q3,Q4} : direction_set <= 1'b1;
       {Q4,Q1} : direction_set <= 1'b1;
       default : direction_set <= 1'b0;
     endcase
 
   // direction_clear
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
     if (rst)
       direction_clr <= 1'b1;
     else
       case ({wptr[N:N-1],rptr[N:N-1]})
         {Q2,Q1} : direction_clr <= 1'b1;
         {Q3,Q2} : direction_clr <= 1'b1;
         {Q4,Q3} : direction_clr <= 1'b1;
         {Q1,Q4} : direction_clr <= 1'b1;
         default : direction_clr <= 1'b0;
       endcase
 
 
 
 
 
 
   always @ (posedge direction_set or posedge direction_clr)
     if (direction_clr)
       direction <= going_empty;
     else
       direction <= going_full;
 
 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_full  = (wptr == rptr) && (direction==going_full);
 
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
 
/*
   always @ (posedge wclk or posedge rst or posedge async_full)
     if (rst)
       {fifo_full, fifo_full2} <= 2'b00;
     else if (async_full)
       {fifo_full, fifo_full2} <= 2'b11;
     else
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
   always @ (posedge rclk or posedge async_empty)
     if (async_empty)
       {fifo_empty, fifo_empty2} <= 2'b11;
     else
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
 
endmodule // async_comp
module async_fifo_dw_simplex_top (
        // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
        a_clk, a_rst,
        // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
        b_clk, b_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
input                   a_clk;
input                   a_rst;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
input                   b_clk;
input                   b_rst;
 
// adr_gen
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
adr_gen
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
 
adr_gen
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_rst));
 
adr_gen
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
 
adr_gen
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_rst));
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
 
vfifo_dual_port_ram_dc_dw
    # (.DATA_WIDTH(data_width), .ADDR_WIDTH(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
 
versatile_fifo_async_cmp
    # (.ADDR_WIDTH(addr_width))
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
 
versatile_fifo_async_cmp
    # (.ADDR_WIDTH(addr_width))
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
 
endmodule

Line No.	Rev	Author	Line
1	29	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Versatile counter ////`
4			`//// ////`
5			`//// Description ////`
6			`//// Versatile counter, a reconfigurable binary, gray or LFSR ////`
7			`//// counter ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - add LFSR with more taps ////`
11			`//// ////`
12			`//// Author(s): ////`
13			`//// - Michael Unneback, unneback@opencores.org ////`
14			`//// ORSoC AB ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2009 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43			`// GRAY counter`
44	28	unneback	`module adr_gen ( cke, q, q_bin, rst, clk);`
45	29	unneback
46	28	unneback	`parameter length = 4;`
47			`input cke;`
48			`output reg [length:1] q;`
49			`output [length:1] q_bin;`
50			`input rst;`
51			`input clk;`
52	29	unneback
53
54	28	unneback	`reg [length:1] qi;`
55			`wire [length:1] q_next;`
56			`assign q_next = qi + {{length-1{1'b0}},1'b1};`
57	29	unneback
58	28	unneback	`always @ (posedge clk or posedge rst)`
59			`if (rst)`
60			`qi <= {length{1'b0}};`
61			`else`
62			`if (cke)`
63			`qi <= q_next;`
64	29	unneback
65	28	unneback	`always @ (posedge clk or posedge rst)`
66			`if (rst)`
67			`q <= {length{1'b0}};`
68			`else`
69			`if (cke)`
70			`q <= (q_next>>1) ^ q_next;`
71	29	unneback
72	28	unneback	`assign q_bin = qi;`
73	29	unneback
74	28	unneback	`endmodule`
75	29	unneback	`// true dual port RAM, sync`
76
77
78
79
80	28	unneback	`module vfifo_dual_port_ram_dc_dw`
81			`(`
82			`d_a,`
83			`q_a,`
84			`adr_a,`
85			`we_a,`
86			`clk_a,`
87			`q_b,`
88			`adr_b,`
89			`d_b,`
90			`we_b,`
91			`clk_b`
92			`);`
93			`parameter DATA_WIDTH = 32;`
94			`parameter ADDR_WIDTH = 8;`
95			`input [(DATA_WIDTH-1):0] d_a;`
96			`input [(ADDR_WIDTH-1):0] adr_a;`
97			`input [(ADDR_WIDTH-1):0] adr_b;`
98			`input we_a;`
99			`output [(DATA_WIDTH-1):0] q_b;`
100			`input [(DATA_WIDTH-1):0] d_b;`
101			`output reg [(DATA_WIDTH-1):0] q_a;`
102			`input we_b;`
103			`input clk_a, clk_b;`
104			`reg [(DATA_WIDTH-1):0] q_b;`
105	29	unneback	`reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /synthesis syn_ramstyle = "no_rw_check"/;`
106	28	unneback	`always @ (posedge clk_a)`
107			`begin`
108			`q_a <= ram[adr_a];`
109			`if (we_a)`
110			`ram[adr_a] <= d_a;`
111			`end`
112			`always @ (posedge clk_b)`
113			`begin`
114			`q_b <= ram[adr_b];`
115			`if (we_b)`
116			`ram[adr_b] <= d_b;`
117			`end`
118			`endmodule`
119	29	unneback	`//////////////////////////////////////////////////////////////////////`
120			`//// ////`
121			`//// Versatile counter ////`
122			`//// ////`
123			`//// Description ////`
124			`//// Versatile counter, a reconfigurable binary, gray or LFSR ////`
125			`//// counter ////`
126			`//// ////`
127			`//// To Do: ////`
128			`//// - add LFSR with more taps ////`
129			`//// ////`
130			`//// Author(s): ////`
131			`//// - Michael Unneback, unneback@opencores.org ////`
132			`//// ORSoC AB ////`
133			`//// ////`
134			`//////////////////////////////////////////////////////////////////////`
135			`//// ////`
136			`//// Copyright (C) 2009 Authors and OPENCORES.ORG ////`
137			`//// ////`
138			`//// This source file may be used and distributed without ////`
139			`//// restriction provided that this copyright statement is not ////`
140			`//// removed from the file and that any derivative work contains ////`
141			`//// the original copyright notice and the associated disclaimer. ////`
142			`//// ////`
143			`//// This source file is free software; you can redistribute it ////`
144			`//// and/or modify it under the terms of the GNU Lesser General ////`
145			`//// Public License as published by the Free Software Foundation; ////`
146			`//// either version 2.1 of the License, or (at your option) any ////`
147			`//// later version. ////`
148			`//// ////`
149			`//// This source is distributed in the hope that it will be ////`
150			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
151			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
152			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
153			`//// details. ////`
154			`//// ////`
155			`//// You should have received a copy of the GNU Lesser General ////`
156			`//// Public License along with this source; if not, download it ////`
157			`//// from http://www.opencores.org/lgpl.shtml ////`
158			`//// ////`
159			`//////////////////////////////////////////////////////////////////////`
160
161	28	unneback	`module dff_sr ( aclr, aset, clock, data, q);`
162	29	unneback
163	28	unneback	`input aclr;`
164			`input aset;`
165			`input clock;`
166			`input data;`
167			`output reg q;`
168	29	unneback
169	28	unneback	`always @ (posedge clock or posedge aclr or posedge aset)`
170			`if (aclr)`
171			`q <= 1'b0;`
172			`else if (aset)`
173			`q <= 1'b1;`
174			`else`
175			`q <= data;`
176	29	unneback
177	28	unneback	`endmodule`
178	29	unneback	`//////////////////////////////////////////////////////////////////////`
179			`//// ////`
180			`//// Versatile counter ////`
181			`//// ////`
182			`//// Description ////`
183			`//// Versatile counter, a reconfigurable binary, gray or LFSR ////`
184			`//// counter ////`
185			`//// ////`
186			`//// To Do: ////`
187			`//// - add LFSR with more taps ////`
188			`//// ////`
189			`//// Author(s): ////`
190			`//// - Michael Unneback, unneback@opencores.org ////`
191			`//// ORSoC AB ////`
192			`//// ////`
193			`//////////////////////////////////////////////////////////////////////`
194			`//// ////`
195			`//// Copyright (C) 2009 Authors and OPENCORES.ORG ////`
196			`//// ////`
197			`//// This source file may be used and distributed without ////`
198			`//// restriction provided that this copyright statement is not ////`
199			`//// removed from the file and that any derivative work contains ////`
200			`//// the original copyright notice and the associated disclaimer. ////`
201			`//// ////`
202			`//// This source file is free software; you can redistribute it ////`
203			`//// and/or modify it under the terms of the GNU Lesser General ////`
204			`//// Public License as published by the Free Software Foundation; ////`
205			`//// either version 2.1 of the License, or (at your option) any ////`
206			`//// later version. ////`
207			`//// ////`
208			`//// This source is distributed in the hope that it will be ////`
209			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
210			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
211			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
212			`//// details. ////`
213			`//// ////`
214			`//// You should have received a copy of the GNU Lesser General ////`
215			`//// Public License along with this source; if not, download it ////`
216			`//// from http://www.opencores.org/lgpl.shtml ////`
217			`//// ////`
218			`//////////////////////////////////////////////////////////////////////`
219
220	28	unneback	`module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );`
221	29	unneback
222	28	unneback	`parameter ADDR_WIDTH = 4;`
223			`parameter N = ADDR_WIDTH-1;`
224	29	unneback
225	28	unneback	`parameter Q1 = 2'b00;`
226			`parameter Q2 = 2'b01;`
227			`parameter Q3 = 2'b11;`
228			`parameter Q4 = 2'b10;`
229	29	unneback
230	28	unneback	`parameter going_empty = 1'b0;`
231			`parameter going_full = 1'b1;`
232	29	unneback
233	28	unneback	`input [N:0] wptr, rptr;`
234			`output reg fifo_empty;`
235			`output fifo_full;`
236			`input wclk, rclk, rst;`
237	29	unneback
238
239
240
241
242	28	unneback	`reg direction;`
243	29	unneback
244	28	unneback	`reg direction_set, direction_clr;`
245	29	unneback
246	28	unneback	`wire async_empty, async_full;`
247			`wire fifo_full2;`
248			`reg fifo_empty2;`
249	29	unneback
250			`// direction_set`
251	28	unneback	`always @ (wptr[N:N-1] or rptr[N:N-1])`
252			`case ({wptr[N:N-1],rptr[N:N-1]})`
253			`{Q1,Q2} : direction_set <= 1'b1;`
254			`{Q2,Q3} : direction_set <= 1'b1;`
255			`{Q3,Q4} : direction_set <= 1'b1;`
256			`{Q4,Q1} : direction_set <= 1'b1;`
257			`default : direction_set <= 1'b0;`
258			`endcase`
259	29	unneback
260			`// direction_clear`
261	28	unneback	`always @ (wptr[N:N-1] or rptr[N:N-1] or rst)`
262			`if (rst)`
263			`direction_clr <= 1'b1;`
264			`else`
265			`case ({wptr[N:N-1],rptr[N:N-1]})`
266			`{Q2,Q1} : direction_clr <= 1'b1;`
267			`{Q3,Q2} : direction_clr <= 1'b1;`
268			`{Q4,Q3} : direction_clr <= 1'b1;`
269			`{Q1,Q4} : direction_clr <= 1'b1;`
270			`default : direction_clr <= 1'b0;`
271			`endcase`
272	29	unneback
273
274
275
276
277
278	28	unneback	`always @ (posedge direction_set or posedge direction_clr)`
279			`if (direction_clr)`
280			`direction <= going_empty;`
281			`else`
282			`direction <= going_full;`
283	29	unneback
284
285	28	unneback	`assign async_empty = (wptr == rptr) && (direction==going_empty);`
286			`assign async_full = (wptr == rptr) && (direction==going_full);`
287	29	unneback
288	28	unneback	`dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));`
289			`dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));`
290	29	unneback
291			`/*`
292			`always @ (posedge wclk or posedge rst or posedge async_full)`
293			`if (rst)`
294			`{fifo_full, fifo_full2} <= 2'b00;`
295			`else if (async_full)`
296			`{fifo_full, fifo_full2} <= 2'b11;`
297			`else`
298			`{fifo_full, fifo_full2} <= {fifo_full2, async_full};`
299			`*/`
300	28	unneback	`always @ (posedge rclk or posedge async_empty)`
301			`if (async_empty)`
302			`{fifo_empty, fifo_empty2} <= 2'b11;`
303			`else`
304			`{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};`
305	29	unneback
306			`endmodule // async_comp`
307	28	unneback	`module async_fifo_dw_simplex_top (`
308	29	unneback	`// a side`
309	28	unneback	`a_d, a_wr, a_fifo_full,`
310			`a_q, a_rd, a_fifo_empty,`
311			`a_clk, a_rst,`
312	29	unneback	`// b side`
313	28	unneback	`b_d, b_wr, b_fifo_full,`
314			`b_q, b_rd, b_fifo_empty,`
315			`b_clk, b_rst`
316			`);`
317	29	unneback
318	28	unneback	`parameter data_width = 18;`
319			`parameter addr_width = 4;`
320	29	unneback
321			`// a side`
322	28	unneback	`input [data_width-1:0] a_d;`
323			`input a_wr;`
324			`output a_fifo_full;`
325			`output [data_width-1:0] a_q;`
326			`input a_rd;`
327			`output a_fifo_empty;`
328			`input a_clk;`
329			`input a_rst;`
330	29	unneback
331			`// b side`
332	28	unneback	`input [data_width-1:0] b_d;`
333			`input b_wr;`
334			`output b_fifo_full;`
335			`output [data_width-1:0] b_q;`
336			`input b_rd;`
337			`output b_fifo_empty;`
338			`input b_clk;`
339			`input b_rst;`
340	29	unneback
341			`// adr_gen`
342	28	unneback	`wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;`
343			`wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;`
344	29	unneback	`// dpram`
345	28	unneback	`wire [addr_width:0] a_dpram_adr, b_dpram_adr;`
346	29	unneback
347	28	unneback	`adr_gen`
348			`# ( .length(addr_width))`
349			`fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));`
350	29	unneback
351	28	unneback	`adr_gen`
352			`# (.length(addr_width))`
353			`fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_rst));`
354	29	unneback
355	28	unneback	`adr_gen`
356			`# ( .length(addr_width))`
357			`fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));`
358	29	unneback
359	28	unneback	`adr_gen`
360			`# (.length(addr_width))`
361			`fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_rst));`
362	29	unneback
363			`// mux read or write adr to DPRAM`
364	28	unneback	`assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};`
365			`assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};`
366	29	unneback
367	28	unneback	`vfifo_dual_port_ram_dc_dw`
368			`# (.DATA_WIDTH(data_width), .ADDR_WIDTH(addr_width+1))`
369			`dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),`
370			`.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));`
371	29	unneback
372	28	unneback	`versatile_fifo_async_cmp`
373			`# (.ADDR_WIDTH(addr_width))`
374			`cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );`
375	29	unneback
376	28	unneback	`versatile_fifo_async_cmp`
377			`# (.ADDR_WIDTH(addr_width))`
378			`cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );`
379	29	unneback
380	28	unneback	`endmodule`

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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [async_fifo_dw_simplex_actel.v] - Blame information for rev 29