Subversion Repositories versatile_fifo

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );

   parameter ADDR_WIDTH = 4;

   parameter N = ADDR_WIDTH-1;

   parameter Q1 = 2'b00;

   parameter Q2 = 2'b01;

   parameter Q3 = 2'b11;

   parameter Q4 = 2'b10;

   parameter going_empty = 1'b0;

   parameter going_full  = 1'b1;

   input [N:0]  wptr, rptr;

   output reg   fifo_empty;

   output       fifo_full;

   input        wclk, rclk, rst;

`ifndef GENERATE_DIRECTION_AS_LATCH

   wire direction;

`endif

`ifdef GENERATE_DIRECTION_AS_LATCH

   reg direction;

`endif

   reg  direction_set, direction_clr;

   wire async_empty, async_full;

   wire fifo_full2;

   reg  fifo_empty2;

   // direction_set

   always @ (wptr[N:N-1] or rptr[N:N-1])

     case ({wptr[N:N-1],rptr[N:N-1]})

       {Q1,Q2} : direction_set <= 1'b1;

       {Q2,Q3} : direction_set <= 1'b1;

       {Q3,Q4} : direction_set <= 1'b1;

       {Q4,Q1} : direction_set <= 1'b1;

       default : direction_set <= 1'b0;

     endcase

   // direction_clear

   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)

     if (rst)

       direction_clr <= 1'b1;

     else

       case ({wptr[N:N-1],rptr[N:N-1]})

         {Q2,Q1} : direction_clr <= 1'b1;

         {Q3,Q2} : direction_clr <= 1'b1;

         {Q4,Q3} : direction_clr <= 1'b1;

         {Q1,Q4} : direction_clr <= 1'b1;

         default : direction_clr <= 1'b0;

       endcase

`ifndef GENERATE_DIRECTION_AS_LATCH

    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));

`endif

`ifdef GENERATE_DIRECTION_AS_LATCH

   always @ (posedge direction_set or posedge direction_clr)

     if (direction_clr)

       direction <= going_empty;

     else

       direction <= going_full;

`endif

   assign async_empty = (wptr == rptr) && (direction==going_empty);

   assign async_full  = (wptr == rptr) && (direction==going_full);

    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));

    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));

/*

   always @ (posedge wclk or posedge rst or posedge async_full)

     if (rst)

       {fifo_full, fifo_full2} <= 2'b00;

     else if (async_full)

       {fifo_full, fifo_full2} <= 2'b11;

     else

       {fifo_full, fifo_full2} <= {fifo_full2, async_full};

*/

   always @ (posedge rclk or posedge async_empty)

     if (async_empty)

       {fifo_empty, fifo_empty2} <= 2'b11;

     else

       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};

endmodule // async_comp