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Subversion Repositories versatile_io

[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [include/] [versatile_io_defines.v] - Blame information for rev 2

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//=tab Main
//=comment <b>Versatile IO</b>
//=tab UART
`define UART0
`define UART0_BASE 32'h92000000
`define UART0_MEM_MAP_HI 31
`define UART0_MEM_MAP_LO 24
//=comment
//`define UART1
`define UART1_BASE 32'h92100000
`define UART1_MEM_MAP_HI 31
`define UART1_MEM_MAP_LO 24

Line No.	Rev	Author	Line
1	2	unneback	`//=tab Main`
2			`//=comment <b>Versatile IO</b>`
3			`//=tab UART`
4			`define UART0
5			`define UART0_BASE 32'h92000000
6			`define UART0_MEM_MAP_HI 31
7			`define UART0_MEM_MAP_LO 24
8			`//=comment`
9			//`define UART1
10			`define UART1_BASE 32'h92100000
11			`define UART1_MEM_MAP_HI 31
12			`define UART1_MEM_MAP_LO 24

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[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [include/] [versatile_io_defines.v] - Blame information for rev 2