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Subversion Repositories uos_processor

[/] [vhdl/] [ram.vhd] - Blame information for rev 2

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1 2 droggen 
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY ram IS
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        generic(N : integer);
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   PORT
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   (
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      clk: IN   std_logic;
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      address:  IN   STD_LOGIC_VECTOR(N-1 downto 0);
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                data:  IN   STD_LOGIC_VECTOR(7 downto 0);
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      we:    IN   std_logic;
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      q:     OUT  STD_LOGIC_VECTOR(7 DOWNTO 0)
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   );
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END ram;
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ARCHITECTURE rtl OF ram IS
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   TYPE mem IS ARRAY(0 TO 2**N-1) OF std_logic_vector(7 DOWNTO 0);
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   SIGNAL ram_block : mem := (
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-- Put the initial content of the memory here. Note: provide exactly 32 bytes
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                                                                                        X"00", X"00",
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                                                                                        X"00", X"00",
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                                                                                        X"00", X"00",
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                                                                                        X"00", X"00",
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                                                                                        X"00", X"00",
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                                                                                        X"00", X"00",
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                                                                                        X"00", X"00",
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                                                                                        X"00", X"00",
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                                                                                        X"00", X"00",
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                                                                                        X"00", X"00",
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                                                                                        X"00", X"00",
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                                                                                        X"00", X"00",
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                                                                                        X"00", X"00",
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                                                                                        X"00", X"00",
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                                                                                        X"00", X"00",
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                                                                                        X"00", X"00"
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                                                                                );
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BEGIN
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   PROCESS(clk)
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   BEGIN
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      IF rising_edge(clk) THEN
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         IF we = '1' THEN
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            ram_block(to_integer(unsigned(address))) <= data;
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         END IF;
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      END IF;
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   END PROCESS;
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        q <= ram_block(to_integer(unsigned(address)));
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END rtl;
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