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elujan |
--
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-- Etapa Instruction Decoding (ID) del procesador MIPS Segmentado
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--
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-- Licencia: Copyright 2008 Emmanuel Luján
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--
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-- This program is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU General Public License as
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-- published by the Free Software Foundation; either version 2 of
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-- the License, or (at your option) any later version. This program
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-- is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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-- License for more details. You should have received a copy of the
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-- GNU General Public License along with this program; if not, write
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-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
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-- Boston, MA 02110-1301 USA.
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--
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-- Autor: Emmanuel Luján
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-- Email: info@emmanuellujan.com.ar
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-- Versión: 1.0
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.records_pkg.all;
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use work.segm_mips_const_pkg.all;
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entity INSTRUCTION_DECODING is
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port(
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CLK : in STD_LOGIC; --Reloj
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RESET : in STD_LOGIC; --Reset asincrónico
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--Entradas de la etapa de Búsqueda de la Instrucción (IF)
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INSTRUCTION : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Instrucción
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NEW_PC_ADDR_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Nueva dirección del PC
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--Entradas de la etapa de Post Escritura (WB)
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RegWrite : in STD_LOGIC; --Señal de habilitación de escritura (RegWrite)
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WRITE_DATA : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Datos a ser escritos
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WRITE_REG : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro Rd
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--Salidas de la etapa de Búsqueda de la Instrucción (IF)
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NEW_PC_ADDR_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Nueva dirección del PC
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--Salidas generadas a partir de la instrucción
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OFFSET : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Offset de la instrucción [15-0]
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RT_ADDR : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro RT [20-16]
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RD_ADDR : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro RD [15-11]
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--Salidas del Banco de Registros
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RS : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Datos leidos de la dir. Rs
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RT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Datos leidos de la dir. Rt
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--Salidas de la Unidad de Control
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WB_CR : out WB_CTRL_REG; --Estas señales se postergarán hasta la etapa WB
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MEM_CR : out MEM_CTRL_REG; --Estas señales se postergarán hasta la etapa MEM
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EX_CR : out EX_CTRL_REG --Estas señales se postergarán hasta la etapa EX
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);
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end INSTRUCTION_DECODING;
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architecture INSTRUCTION_DECODING_ARC of INSTRUCTION_DECODING is
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--Declaración de componentes
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component REGISTERS is
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port(
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CLK : in STD_LOGIC; --Reloj
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RESET : in STD_LOGIC; --Reset asincrónico
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RW : in STD_LOGIC; --Señal de habilitación de escritura (RegWrite)
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RS_ADDR : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro Rs
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RT_ADDR : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro Rt
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RD_ADDR : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro Rd
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WRITE_DATA : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Datos a ser escritos
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RS : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Datos leidos de la dir. Rs
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RT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0) --Datos leidos de la dir. Rt
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);
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end component REGISTERS;
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component CONTROL_UNIT is
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port(
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OP : in STD_LOGIC_VECTOR (5 downto 0); --Código de operación
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RegWrite : out STD_LOGIC; --Señal de habilitación de escritura (RegWrite)
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MemtoReg : out STD_LOGIC; --Señal de habilitación (MemToReg)
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Brach : out STD_LOGIC; --Señal de habilitación (Branch)
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MemRead : out STD_LOGIC; --Señal de habilitación (MemRead)
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MemWrite : out STD_LOGIC; --Señal de habilitación (MemWrite)
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RegDst : out STD_LOGIC; --Señal de habilitación (RegDst)
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ALUSrc : out STD_LOGIC; --Señal de habilitación (ALUSrc)
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ALUOp0 : out STD_LOGIC; --Señal de habilitación (ALUOp)
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ALUOp1 : out STD_LOGIC; --Señal de habilitación (ALUOp)
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ALUOp2 : out STD_LOGIC --Señal de habilitación (ALUOp2)
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);
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end component CONTROL_UNIT;
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component ID_EX_REGISTERS is
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port(
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--Entradas
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CLK : in STD_LOGIC; -- Reloj
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RESET : in STD_LOGIC; -- Reset asincrónico
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--Salidas de la etapa de Búsqueda de la Instrucción (IF)
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NEW_PC_ADDR_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Nueva dirección del PC
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--Salidas generadas a partir de la instrucción
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OFFSET_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Offset de la instrucción [15-0]
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RT_ADDR_IN : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);-- Dirección del registro RT [20-16]
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RD_ADDR_IN : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);-- Dirección del registro RD [15-11]
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--Salidas del Banco de Registros
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RS_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Datos leidos de la dir. Rs
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RT_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Datos leidos de la dir. Rt
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--Salidas de la Unidad de Control
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WB_IN : in WB_CTRL_REG; -- Señales de control para la etapa WB
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M_IN : in MEM_CTRL_REG; -- Señales de control para la etapa MEM
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EX_IN : in EX_CTRL_REG; -- Señales de control para la etapa EX
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--Salidas
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--Salidas de la etapa de Búsqueda de la Instrucción (IF)
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NEW_PC_ADDR_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Nueva dirección del PC
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--Salidas generadas a partir de la instrucción
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OFFSET_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Offset de la instrucción [15-0]
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RT_ADDR_OUT : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);-- Dirección del registro RT [20-16]
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RD_ADDR_OUT : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);-- Dirección del registro RD [15-11]
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--Salidas del Banco de Registros
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RS_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Datos leidos de la dir. Rs
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RT_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Datos leidos de la dir. Rt
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--Salidas de la Unidad de Control
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WB_OUT : out WB_CTRL_REG; -- Estas señales se postergarán hasta la etapa WB
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M_OUT : out MEM_CTRL_REG; -- Estas señales se postergarán hasta la etapa MEM
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EX_OUT : out EX_CTRL_REG -- Estas señales se postergarán hasta la etapa EX
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);
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end component ID_EX_REGISTERS;
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--Declaración de señales
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-- Buses de datos auxiliares para comunicar las distintas salidas
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-- que los componentes generan y dárselas a los registros de
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-- sincronización de etapas.
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signal OFFSET_AUX : STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);
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signal RS_AUX : STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);
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signal RT_AUX : STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);
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signal WB_AUX : WB_CTRL_REG;
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signal MEM_AUX : MEM_CTRL_REG;
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signal EX_AUX : EX_CTRL_REG;
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--Alias
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-- Se encuentran comentados debido a que GHDL no soporta su uso.
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--alias OP_A : STD_LOGIC_VECTOR (5 downto 0) is INSTRUCTION(INST_SIZE-1 downto 26);
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--alias RS_ADDR_A : STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0) is INSTRUCTION(25 downto 21);
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--alias RT_ADDR_A : STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0) is INSTRUCTION(20 downto 16);
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--alias RD_ADDR_A : STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0) is INSTRUCTION(15 downto 11);
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--alias OFFSET_A : STD_LOGIC_VECTOR (15 downto 0) is INSTRUCTION(15 downto 0);
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begin
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--Port maps
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REGS:
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REGISTERS port map(
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CLK => CLK,
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RESET => RESET,
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RW => RegWrite,
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RS_ADDR => INSTRUCTION(25 downto 21),--RS_ADDR_A,
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RT_ADDR => INSTRUCTION(20 downto 16),--RT_ADDR_A,
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RD_ADDR => WRITE_REG,
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WRITE_DATA => WRITE_DATA,
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RS => RS_AUX,
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RT => RT_AUX
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);
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CTRL :
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CONTROL_UNIT port map(
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--Entrada
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OP => INSTRUCTION(INST_SIZE-1 downto 26),--OP_A,
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--Salidas
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RegWrite => WB_AUX.RegWrite,
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MemtoReg => WB_AUX.MemtoReg,
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Brach => MEM_AUX.Branch,
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MemRead => MEM_AUX.MemRead,
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MemWrite => MEM_AUX.MemWrite,
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RegDst => EX_AUX.RegDst,
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ALUSrc => EX_AUX.ALUSrc,
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ALUOp0 => EX_AUX.ALUOp.Op0,
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ALUOp1 => EX_AUX.ALUOp.Op1,
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ALUOp2 => EX_AUX.ALUOp.Op2
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);
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--Se hace una extensión de signo
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--OFFSET_AUX <= ZERO16b & OFFSET_A
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-- when OFFSET_A(15) = '0'
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-- else ONE16b & OFFSET_A;
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OFFSET_AUX <= ZERO16b & INSTRUCTION(15 downto 0)
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when INSTRUCTION(15) = '0'
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else ONE16b & INSTRUCTION(15 downto 0);
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ID_EX_REGS:
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ID_EX_REGISTERS port map(
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--Entradas
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CLK => CLK,
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RESET => RESET,
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NEW_PC_ADDR_IN => NEW_PC_ADDR_IN,
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OFFSET_IN => OFFSET_AUX,
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RT_ADDR_IN => INSTRUCTION(20 downto 16),--RT_ADDR_A,
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RD_ADDR_IN => INSTRUCTION(15 downto 11),--RD_ADDR_A,
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RS_IN => RS_AUX,
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RT_IN => RT_AUX,
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WB_IN => WB_AUX,
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M_IN => MEM_AUX,
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EX_IN => EX_AUX,
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--Salidas
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NEW_PC_ADDR_OUT => NEW_PC_ADDR_OUT,
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OFFSET_OUT => OFFSET,
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RT_ADDR_OUT => RT_ADDR,
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RD_ADDR_OUT => RD_ADDR,
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RS_OUT => RS,
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RT_OUT => RT,
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WB_OUT => WB_CR,
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M_OUT => MEM_CR,
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EX_OUT => EX_CR
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);
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end INSTRUCTION_DECODING_ARC;
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