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--
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-- Banco de registros del procesador MIPS Segmentado
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--
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-- Licencia: Copyright 2008 Emmanuel Luján
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--
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-- This program is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU General Public License as
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-- published by the Free Software Foundation; either version 2 of
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-- the License, or (at your option) any later version. This program
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-- is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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-- License for more details. You should have received a copy of the
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-- GNU General Public License along with this program; if not, write
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-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
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-- Boston, MA 02110-1301 USA.
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--
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-- Autor: Emmanuel Luján
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-- Email: info@emmanuellujan.com.ar
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-- Versión: 1.0
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.segm_mips_const_pkg.all;
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entity REGISTERS is
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port(
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--Entradas
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CLK : in STD_LOGIC; --Reloj
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RESET : in STD_LOGIC; --Reset asincrónico
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RW : in STD_LOGIC; --Señal de habilitación de escritura (RegWrite)
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RS_ADDR : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro Rs
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RT_ADDR : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro Rt
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RD_ADDR : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro Rd
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WRITE_DATA : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Datos a ser escritos
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--Salidas
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RS : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Datos leidos de la dir. Rs
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RT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0) --Datos leidos de la dir. Rt
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);
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end REGISTERS;
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architecture REGISTERS_ARC of REGISTERS is
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-- Tipo para almacenar los registros
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type REGS_T is array (NUM_REG-1 downto 0) of STD_LOGIC_VECTOR(INST_SIZE-1 downto 0);
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-- Esta es la señal que contiene los registros. El acceso es de la
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-- siguiente manera: regs(i) acceso al registro i, donde i es
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-- un entero. Para convertir del tipo STD_LOGIC_VECTOR a entero se
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-- hace de la siguiente manera: to_integer(unsigned(slv)), donde
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-- slv es un elemento de tipo STD_LOGIC_VECTOR
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signal REGISTROS : REGS_T;
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begin
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REG_ASIG:
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process(CLK,RESET,RW,WRITE_DATA,RD_ADDR)
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begin
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if RESET='1' then
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for i in 0 to NUM_REG-1 loop
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REGISTROS(i) <= (others => '0');
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end loop;
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--Los resgitros son completados de esta manera para
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--la prueba del algoritmo "Restoring", ya que no se
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--ha implementado la instrucción LLI
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REGISTROS(0) <= "00000000000000000000000000000000";
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REGISTROS(1) <= "00000000000000000000000000000001";
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REGISTROS(2) <= "00000000000000000000000000000010";
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REGISTROS(3) <= "00000000000000000000000000000011";
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REGISTROS(4) <= "00000000000000000000000000000100";
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--REGISTROS(5) <= "00000000000000000000000000000101";
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REGISTROS(5) <= "00000000000000000000000000000001";
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--REGISTROS(6) <= "00000000000000000000000000000110";
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REGISTROS(6) <= "00000000000000000000000000000000";
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--REGISTROS(7) <= "00000000000000000000000000000111";
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REGISTROS(7) <= "00000000000000000000000000100000";
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--REGISTROS(8) <= "00000000000000000000000000001000";
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REGISTROS(8) <= "00000000000000000000000000000000";
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REGISTROS(9) <= "00000000000000000000000000001001";
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--REGISTROS(10) <= "00000000000000000000000000001010";
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REGISTROS(10) <= "00000000000000000000000000010011";
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--REGISTROS(11) <= "00000000000000000000000000001011";
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REGISTROS(11) <= "00000000000000000000000000011010";
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--REGISTROS(12) <= "00000000000000000000000000001100";
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REGISTROS(12) <= "00000000000000000000000000000000";
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REGISTROS(13) <= "00000000000000000000000000001101";
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REGISTROS(14) <= "00000000000000000000000000001110";
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REGISTROS(15) <= "00000000000000000000000000001111";
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REGISTROS(16) <= "00000000000000000000000000010000";
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REGISTROS(17) <= "00000000000000000000000000010001";
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REGISTROS(18) <= "00000000000000000000000000010010";
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REGISTROS(19) <= "00000000000000000000000000010011";
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REGISTROS(20) <= "00000000000000000000000000010100";
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REGISTROS(21) <= "00000000000000000000000000010101";
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REGISTROS(22) <= "00000000000000000000000000010110";
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REGISTROS(23) <= "00000000000000000000000000010111";
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REGISTROS(24) <= "00000000000000000000000000011000";
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REGISTROS(25) <= "00000000000000000000000000011001";
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REGISTROS(26) <= "00000000000000000000000000011010";
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REGISTROS(27) <= "00000000000000000000000000011011";
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REGISTROS(28) <= "00000000000000000000000000011100";
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REGISTROS(29) <= "00000000000000000000000000011101";
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REGISTROS(30) <= "00000000000000000000000000011110";
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REGISTROS(31) <= "00000000000000000000000000011111";
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elsif rising_edge(CLK) then
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if RW='1' then
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REGISTROS(to_integer(unsigned(RD_ADDR)))<=WRITE_DATA;
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end if;
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end if;
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end process REG_ASIG;
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RS <= (others=>'0') when RS_ADDR="00000"
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else REGISTROS(to_integer(unsigned(RS_ADDR)));
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RT <= (others=>'0') when RT_ADDR="00000"
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else REGISTROS(to_integer(unsigned(RT_ADDR)));
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end REGISTERS_ARC;
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