1 |
2 |
elujan |
--
|
2 |
|
|
-- Etapa Memory Access (MEM) del procesador MIPS Segmentado
|
3 |
|
|
--
|
4 |
|
|
-- Licencia: Copyright 2008 Emmanuel Luján
|
5 |
|
|
--
|
6 |
|
|
-- This program is free software; you can redistribute it and/or
|
7 |
|
|
-- modify it under the terms of the GNU General Public License as
|
8 |
|
|
-- published by the Free Software Foundation; either version 2 of
|
9 |
|
|
-- the License, or (at your option) any later version. This program
|
10 |
|
|
-- is distributed in the hope that it will be useful, but WITHOUT
|
11 |
|
|
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
12 |
|
|
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
13 |
|
|
-- License for more details. You should have received a copy of the
|
14 |
|
|
-- GNU General Public License along with this program; if not, write
|
15 |
|
|
-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
|
16 |
|
|
-- Boston, MA 02110-1301 USA.
|
17 |
|
|
--
|
18 |
|
|
-- Autor: Emmanuel Luján
|
19 |
|
|
-- Email: info@emmanuellujan.com.ar
|
20 |
|
|
-- Versión: 1.0
|
21 |
|
|
--
|
22 |
|
|
|
23 |
|
|
|
24 |
|
|
library ieee;
|
25 |
|
|
use ieee.std_logic_1164.all;
|
26 |
|
|
use ieee.numeric_std.all;
|
27 |
|
|
|
28 |
|
|
library work;
|
29 |
|
|
use work.records_pkg.all;
|
30 |
|
|
use work.segm_mips_const_pkg.all;
|
31 |
|
|
|
32 |
|
|
entity MEMORY_ACCESS is
|
33 |
|
|
port(
|
34 |
|
|
--Entradas
|
35 |
|
|
CLK : in STD_LOGIC; --Reloj
|
36 |
|
|
RESET : in STD_LOGIC; --Reset asincrónico
|
37 |
|
|
WB_IN : in WB_CTRL_REG; --Estas señales se postergarán hasta la etapa WB
|
38 |
|
|
MEM : in MEM_CTRL_REG; --Estas señales serán usadas en esta etapa
|
39 |
|
|
FLAG_ZERO : in STD_LOGIC; --Flag Zero de la ALU
|
40 |
|
|
NEW_PC_ADDR : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Nueva dirección de pc hacia la etapa de IF
|
41 |
|
|
ADDRESS_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Salida de la ALU (ALU Result), dirección de la memoria de datos
|
42 |
|
|
WRITE_DATA : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Datos a ser escritos en la memoria de datos
|
43 |
|
|
WRITE_REG_IN : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0); --WriteRegister de los registros de la etapa de ID
|
44 |
|
|
--Salidas hacia la etapa WB, sincronizadas por registros
|
45 |
|
|
WB_OUT : out WB_CTRL_REG; --Estas señales se postergarán hasta la etapa WB
|
46 |
|
|
READ_DATA : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Datos leidos de la memoria de datos
|
47 |
|
|
ADDRESS_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Resultado de la ALU
|
48 |
|
|
WRITE_REG_OUT : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0); --WriteRegister de los registros de la etapa de ID
|
49 |
|
|
--Salidas hacia la etapas IF, sin sincronización
|
50 |
|
|
NEW_PC_ADDR_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Nueva dirección de pc hacia la etapa de IF
|
51 |
|
|
PCSrc : out STD_LOGIC --Señal de habilitación del mux de la etapa de IF
|
52 |
|
|
);
|
53 |
|
|
end MEMORY_ACCESS;
|
54 |
|
|
|
55 |
|
|
architecture MEMORY_ACCESS_ARC of MEMORY_ACCESS is
|
56 |
|
|
|
57 |
|
|
-- Declaración de componentes
|
58 |
|
|
|
59 |
|
|
component DATA_MEMORY is
|
60 |
|
|
generic (N :NATURAL :=INST_SIZE; M :NATURAL :=NUM_ADDR); -- N = tam. dir. ; M = tamaño de la memoria
|
61 |
|
|
port(
|
62 |
|
|
RESET : in STD_LOGIC; --Reset asincrónico
|
63 |
|
|
ADDR : in STD_LOGIC_VECTOR (N-1 downto 0); --Dirección a ser leida o escrita
|
64 |
|
|
WRITE_DATA : in STD_LOGIC_VECTOR (N-1 downto 0); --Datos a ser escritos
|
65 |
|
|
MemRead : in STD_LOGIC; --Señal de hailitación para lectura
|
66 |
|
|
MemWrite : in STD_LOGIC; --Señal de hailitación para escritura
|
67 |
|
|
READ_DATA : out STD_LOGIC_VECTOR (N-1 downto 0) --Datos leidos
|
68 |
|
|
|
69 |
|
|
);
|
70 |
|
|
end component DATA_MEMORY;
|
71 |
|
|
|
72 |
|
|
component MEM_WB_REGISTERS is
|
73 |
|
|
port(
|
74 |
|
|
--Entradas
|
75 |
|
|
CLK : in STD_LOGIC;
|
76 |
|
|
RESET : in STD_LOGIC;
|
77 |
|
|
WB : in WB_CTRL_REG;
|
78 |
|
|
READ_DATA : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);
|
79 |
|
|
ADDRESS : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);
|
80 |
|
|
WRITE_REG : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);
|
81 |
|
|
--Salidas
|
82 |
|
|
WB_OUT : out WB_CTRL_REG;
|
83 |
|
|
READ_DATA_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);
|
84 |
|
|
ADDRESS_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);
|
85 |
|
|
WRITE_REG_OUT : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0)
|
86 |
|
|
);
|
87 |
|
|
end component MEM_WB_REGISTERS;
|
88 |
|
|
|
89 |
|
|
|
90 |
|
|
--Declaración de señales
|
91 |
|
|
signal READ_DATA_AUX : STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);
|
92 |
|
|
|
93 |
|
|
begin
|
94 |
|
|
|
95 |
|
|
OUT_MEM:
|
96 |
|
|
process(RESET,FLAG_ZERO,MEM.Branch,NEW_PC_ADDR)
|
97 |
|
|
begin
|
98 |
|
|
if( RESET = '1') then
|
99 |
|
|
PCSrc <= '0';
|
100 |
|
|
NEW_PC_ADDR_OUT <= ZERO32b;
|
101 |
|
|
else
|
102 |
|
|
PCSrc <= FLAG_ZERO and MEM.Branch;
|
103 |
|
|
NEW_PC_ADDR_OUT <= NEW_PC_ADDR;
|
104 |
|
|
end if;
|
105 |
|
|
end process OUT_MEM;
|
106 |
|
|
|
107 |
|
|
DAT_MEM:
|
108 |
|
|
DATA_MEMORY generic map (N=>INST_SIZE, M=>NUM_ADDR)
|
109 |
|
|
port map(
|
110 |
|
|
RESET => RESET,
|
111 |
|
|
ADDR => ADDRESS_IN,
|
112 |
|
|
WRITE_DATA => WRITE_DATA,
|
113 |
|
|
MemRead => MEM.MemRead,
|
114 |
|
|
MemWrite => MEM.MemWrite,
|
115 |
|
|
READ_DATA => READ_DATA_AUX
|
116 |
|
|
|
117 |
|
|
);
|
118 |
|
|
|
119 |
|
|
MEM_WB_REGS:
|
120 |
|
|
MEM_WB_REGISTERS port map(
|
121 |
|
|
--Entradas
|
122 |
|
|
CLK => CLK,
|
123 |
|
|
RESET => RESET,
|
124 |
|
|
WB => WB_IN,
|
125 |
|
|
READ_DATA => READ_DATA_AUX,
|
126 |
|
|
ADDRESS => ADDRESS_IN,
|
127 |
|
|
WRITE_REG => WRITE_REG_IN,
|
128 |
|
|
--Salidas
|
129 |
|
|
WB_OUT => WB_OUT,
|
130 |
|
|
READ_DATA_OUT => READ_DATA,
|
131 |
|
|
ADDRESS_OUT => ADDRESS_OUT,
|
132 |
|
|
WRITE_REG_OUT => WRITE_REG_OUT
|
133 |
|
|
);
|
134 |
|
|
|
135 |
|
|
|
136 |
|
|
end MEMORY_ACCESS_ARC;
|