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robfinch |
# via6522x12
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(C) 2022 Robert Finch
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## Overview
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The via6522x12 is a versatile interface adapter 12-bit peripheral core that is register compatible with a 6522.
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The core may also be configured for eight bit operation.
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## Features
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* 2 12-bit ports
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* 3 24-bit timers
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* 1 12-bit shift register
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## Registers
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|Reg |Bits|Moniker| Description | Comment |
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|----|----|-------|------------------------|----------------|
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| 00 | 12 | PB | Port B I/O | |
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| 01 | 12 | PA | Port A I/O | handshaking |
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| 02 | 12 | PBDDR | Port B data direction | |
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| 03 | 12 | PADDR | Port A data direction | |
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| 04 | 12 | T1CL | Time 1 count low | |
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| 05 | 12 | T1CH | Time 1 count high | |
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| 06 | 12 | T1LL | Time 1 latch low | |
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| 07 | 12 | T1LH | Time 1 latch high | |
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| 08 | 12 | T2CL | Time 2 count low | |
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| 09 | 12 | T2CH | Time 2 count high | |
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| 10 | 12 | SR | Shift register | |
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| 11 | 12 | ACR | Auxillary control reg | |
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| 12 | 12 | PCR | Peripheral control reg | |
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| 13 | 12 | IFR | Interrupt flag reg | |
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| 14 | 12 | IER | Interrupt enable reg | |
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| 15 | 12 | PA | Port A I/O | no-handshaking |
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| 16 | 12 | T3CL | Timer 3 count low | |
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| 17 | 12 | T3CH | Timer 3 count high | |
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| 18 | 12 | T3LL | Timer 3 latch low | |
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| 19 | 12 | T3LH | Timer 3 latch high | |
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| 20 | 12 | T3CMPL| Timer 3 compare low | |
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| 21 | 12 | T3CMPH| Timer 3 compare high | |
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### PB (Reg 00)
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Operates in the same manner as the 6522 port B but is 12-bits wide rather than 8-bits. If port B input latching is enabled, then input data on port B is latched by an active transition of the selected handshaking signal. Otherwise input data is reflected directly by reading the port register.
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### PA (Reg 01)
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Operates in the same manner as the 6522 port A but is 12-bits wide rather than 8-bits. If port A input latching is enabled, then input data on port A is latched by an active transition of the selected handshaking signal. Otherwise input data is reflected directly by reading the port register.
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### PBDDR (Reg 02)
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Operates in the same manner as the 6522 port B ddr but is 12-bits wide rather than 8-bits. Each bit that is set in this register set the corresponding port B I/O to an output. Each bit that is clear in this register sets the port B I/O to an input. The default value in this register at reset is zero, making all port B I/O’s inputs.
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### PADDR (Reg 03)
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Operates in the same manner as the 6522 port A ddr but is 12-bits wide rather than 8-bits. Each bit that is set in this register set the corresponding port A I/O to an output. Each bit that is clear in this register sets the port A I/O to an input. The default value in this register at reset is zero, making all port A I/O’s inputs.
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### T1CL (Reg 04)
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Similar function to the reg 4 of the 6522. Provides read access to the low order 12-bits of timer 1. Acts as a latch for the low 12-bits of the value to be loaded into the timer.
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### T1CH (Reg 05)
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Similar in function to register 5 of the 6522. When the timer is in 24-bit mode writing this register transfers bit 0 to 11 of the timer 1 latch to bits 0 to 11 of the timer and transfers input data bits 0 to 11 to counter bits 12 to 23 of the timer.
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### T1LL (Reg 06)
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Similar in function to register 6 of the 6522. Provides access to the timer 1 low order latches.
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### T1LH (Reg 07)
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Similar in function to register 7 of the 6522. Provides access to the timer 1 high order latches.
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### T2CL (Reg 08)
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Similar in function to register 8 of the 6522. Provides access to timer 2 low order latch / count.
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### T2CH (Reg 09)
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Similar in function to register 9 of the 6522. Provides access to timer 2 high order latch / count.
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### SR (Reg 10)
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Similar in function to register 10 of the 6522. The shift register is 12-bits wide.
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### ACR (Reg 11)
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| Bits | Function |
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|------|--------------------------------------|
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| 0 | port A input latch enable |
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| 1 | port B input latch enable |
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| 2-4 | shift register mode |
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| 5 | timer #2 mode |
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| 6-7 | timer #1 mode |
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| 8 | timer #3 mode |
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### PCR (Reg 12)
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| Bits | Function |
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|------|--------------------------------------|
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| 0 | CA1 mode |
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| 1-3 | CA2 mode |
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| 4 | CB1 mode |
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| 5-7 | CB2 mode |
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### IFR (Reg 13)
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| Bits | Function |
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|------|--------------------------------------|
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| 0 | CA2 active transition |
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| 1 | CA1 active transition |
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| 2 | shift register |
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| 3 | CB2 active transition |
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| 4 | CB1 active transition |
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| 5 | Timer #1 underflow |
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| 6 | Timer #2 underflow |
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| 7 | Timer #3 compare |
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| 8-10 | reserved |
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| 11 | Set if any interrupt is present |
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### IER (Reg 14)
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| Bits | Function |
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|------|--------------------------------------|
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| 0 | CA2 active transition |
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| 1 | CA1 active transition |
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| 2 | shift register |
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| 3 | CB2 active transition |
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| 4 | CB1 active transition |
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| 5 | Timer #1 underflow |
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| 6 | Timer #2 underflow |
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| 7 | Set if any interrupt is present |
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| 8 | Timer #3 compare |
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| 9-10 | reserved |
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### PA (Reg 15)
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This is an alias to access port A except no handshaking is present.
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### T3CL (Reg 16)
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Provides read access to the low order 12-bits of timer 3. Acts as a latch for the low 12-bits of the value to be loaded into the timer.
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### T3CH (Reg 17)
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Writing this register transfers bit 0 to 11 of the timer 3 latch to bits 0 to 11 of the timer and transfers input data bits 0 to 11 to counter bits 12 to 23 of the timer.
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### T3LL (Reg 18)
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Provides access to the timer 1 low order latches.
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### T3LH (Reg 19)
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Provides access to the timer 3 high order latches.
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### T3CMPL (Reg 20)
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Contains the low order 12 bits of a comparison value that will cause an interrupt flag to be set if timer #3 exceeds this value.
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### T3CMPH (Reg 21)
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Contains the high order 12 bits of the comparison value.
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## Key Differences from a 6522
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The reset input (rst_i) is active high.
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The IRQ output (irq_o) is not open collector and is active high.
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There is only a single active high circuit select (cs_i).
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## Software Examples
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The via6522x12 is being used for timing and gpio in a 12-bit 6809 test system.
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