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[/] [via6522/] [trunk/] [rtl/] [edge_det.v] - Blame information for rev 2

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1 2 robfinch
// ============================================================================
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// (C) 2007-2019 Robert Finch
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// All Rights Reserved.
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//
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//      edge_det.v
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//    Notes:
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//
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//      Edge detector
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//      This little core detects an edge (positive, negative, and
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//      either) in the input signal.
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//
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// ============================================================================
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//
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module edge_det(rst, clk, ce, i, pe, ne, ee);
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input rst;              // reset
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input clk;              // clock
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input ce;               // clock enable
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input i;                // input signal
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output pe;              // positive transition detected
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output ne;              // negative transition detected
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output ee;              // either edge (positive or negative) transition detected
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reg ed = 1'b0;
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always @(posedge clk)
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        if (rst)
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                ed <= 1'b0;
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        else if (ce)
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                ed <= i;
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assign pe = ~ed & i;    // positive: was low and is now high
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assign ne = ed & ~i;    // negative: was high and is now low
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assign ee = ed ^ i;             // either: signal is now opposite to what it was
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endmodule

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