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// ============================================================================
//        __
//   \\__/ o\    (C) 2004-2022  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//       ||
//
//      via6522_x12.sv
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see .
//
// ============================================================================
 
`define PB              5'd0
`define PA              5'd1
`define DDRB    5'd2
`define DDRA    5'd3
`define T1CL    5'd4
`define T1CH    5'd5
`define T1LL    5'd6
`define T1LH    5'd7
`define T2CL    5'd8
`define T2CH    5'd9
`define SR              5'd10
`define ACR             5'd11
`define PCR             5'd12
`define IFR             5'd13
`define IER             5'd14
`define ORA             5'd15
`define T3CL    5'd16
`define T3CH    5'd17
`define T3LL    5'd18
`define T3LH    5'd19
`define T3CMPL  5'd20
`define T3CMPH  5'd21
 
module via6522_x12 (rst_i, clk_i, wc_clk_i, irq_o, cs_i,
        cyc_i, stb_i, ack_o, we_i, adr_i, dat_i, dat_o,
        ca1, ca2_i, ca2_o, ca2_t, cb1_i, cb1_o, cb1_t, cb2_i, cb2_o, cb2_t,
        pa_i, pb_i, pa_o, pb_o, pa_t, pb_t,
        t1_if, t2_if, t3_if
        );
parameter pBitsPerByte=12;
input rst_i;
input clk_i;
input wc_clk_i;
output reg irq_o;
input cs_i;
input cyc_i;
input stb_i;
output ack_o;
input we_i;
input [4:0] adr_i;
input [pBitsPerByte-1:0] dat_i;
output reg [pBitsPerByte-1:0] dat_o;
 
input ca1;
input ca2_i;
output ca2_o;
output ca2_t;
input cb1_i;
output cb1_o;
output cb1_t;
input cb2_i;
output cb2_o;
output cb2_t;
input [pBitsPerByte-1:0] pa_i;
input [pBitsPerByte-1:0] pb_i;
output [pBitsPerByte-1:0] pa_o;
output [pBitsPerByte-1:0] pb_o;
output reg [pBitsPerByte-1:0] pa_t;
output reg [pBitsPerByte-1:0] pb_t;
 
output reg t1_if;                                                       // timer 1 interrupt flag
output reg t2_if;                                                       // timer 2 interrupt flag
output reg t3_if;                                                       // timer 3 interrupt flag
 
integer n;
 
wire cs = cs_i & cyc_i & stb_i;
 
ack_gen #(
        .READ_STAGES(2),
        .WRITE_STAGES(0),
        .REGISTER_OUTPUT(1)
) uag1
(
        .rst_i(rst_i),
        .clk_i(clk_i),
        .ce_i(1'b1),
        .i(cs),
        .we_i(cs & we_i),
        .o(ack_o),
        .rid_i(0),
        .wid_i(0),
        .rid_o(),
        .wid_o()
);
 
reg [5:0] ie_delay;
reg [8:0] ier, ierd;      // interrupt enable register / delayed interrupt enable register
reg [pBitsPerByte-1:0] pai, pbi;                // input registers
reg [pBitsPerByte-1:0] pao, pbo;                // output latches
reg [pBitsPerByte-1:0] pal, pbl;                // input latches
reg pa_le, pb_le;                               // latching enable
reg [pBitsPerByte-1:0] ddra, ddrb;      // data direction registers
reg cb1o, cb2o, ca2o;
reg [1:0] t1_mode;
reg t2_mode;
reg t3_mode;
reg [pBitsPerByte*2-1:0] t1, t2, t3;    // 24 bit timers
reg [pBitsPerByte*2-1:0] t3cmp;
reg t3_access;
reg t1_64, t2_64;
reg [pBitsPerByte*2-1:0] t1l;
reg [pBitsPerByte*2-1:0] t2l;
reg [pBitsPerByte*2-1:0] t3l;
wire ca1_trans, ca2_trans;      // active transitions
wire cb1_trans, cb2_trans;
reg ca1_mode;
reg cb1_mode;
reg [2:0] ca2_mode;
reg [2:0] cb2_mode;
reg [4:0] sr_cnt;                               // shift register counter
reg [pBitsPerByte-1:0] sr;                                      // shift register
reg sr_32;                                                      // shift register 32 bit mode
reg [2:0] sr_mode;                      // shift register mode
reg sr_if;
wire ca1_pe, ca1_ne, ca1_ee;
wire ca2_pe, ca2_ne, ca2_ee;
wire cb1_pe, cb1_ne, cb1_ee;
reg ca1_if, cb1_if;
reg ca2_if, cb2_if;
wire pb6_ne;
reg ca1_irq, ca2_irq;
reg cb1_irq, cb2_irq;
reg t1_irq, t2_irq, t3_irq;
reg sr_irq;
wire pe_t1z, pe_t2z, pe_t3z;
 
edge_det ued1 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(ca1), .pe(ca1_pe), .ne(ca1_ne), .ee(ca1_ee));
edge_det ued2 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(ca2_i), .pe(ca2_pe), .ne(ca2_ne), .ee(ca2_ee));
edge_det ued3 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cb1_i), .pe(cb1_pe), .ne(cb1_ne), .ee(cb1_ee));
edge_det ued4 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cb2_i), .pe(cb2_pe), .ne(cb2_ne), .ee(cb2_ee));
edge_det ued5 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(pb_i[10]), .pe(), .ne(pb6_ne), .ee());
edge_det ued6 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(t3=={pBitsPerByte*2{1'd0}}), .pe(pe_t3z), .ne(), .ee());
edge_det ued7 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(t2=={pBitsPerByte*2{1'd0}}), .pe(pe_t2z), .ne(), .ee());
edge_det ued8 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(t1=={pBitsPerByte*2{1'd0}}), .pe(pe_t1z), .ne(), .ee());
 
 
assign ca1_trans = (ca1_mode & ca1_pe) | (~ca1_mode & ca1_ne);
assign ca2_trans = (ca2_mode[2:1]==2'b00&&ca2_ne)||(ca2_mode[2:1]==2'b01&&ca2_pe);
assign cb1_trans = (cb1_mode & cb1_pe) | (~cb1_mode & cb1_ne);
assign cb2_trans = (cb2_mode[2:1]==2'b00&&cb2_ne)||(cb2_mode[2:1]==2'b01&&cb2_pe);
 
reg wr_t3;
 
always @(posedge wc_clk_i)
if (rst_i)
        t3 <= {pBitsPerByte*2{1'd1}};
else begin
        t3 <= t3 + 2'd1;
        if (wr_t3)
                t3 <= t3l;
end
 
always @(posedge clk_i)
if (rst_i) begin
        ddra <= {pBitsPerByte{1'd0}};
        ddrb <= {pBitsPerByte{1'd0}};
        ca1_irq <= 1'b0;
        ca2_irq <= 1'b0;
        cb1_irq <= 1'b0;
        cb2_irq <= 1'b0;
        ca2o <= 1'b0;
        cb1o <= 1'b0;
        cb2o <= 1'b0;
        t1_64 <= 1'b0;
        t2_64 <= 1'b0;
        sr_mode <= 3'b000;
        sr_32 <= 1'b0;
        sr_if <= 1'b0;
        t1 <= {pBitsPerByte*2{1'd1}};
        t1_if <= 1'b0;
        t2 <= {pBitsPerByte*2{1'd1}};
        t2_if <= 1'b0;
        t3_if <= 1'b0;
        t3_access <= 1'b0;
        wr_t3 <= 1'b0;
        ier <= 9'h00;
        ie_delay <= 6'h00;
end
else begin
 
  if (ie_delay!=6'h00)
    ie_delay <= ie_delay - 2'd1;
  if (ie_delay==6'h01)
    ier <= ierd;
 
        // Port A,B input latching
        // Port A input latches always reflect the input pins.
        if (pa_le) begin
                if (ca1_trans)
                        pai <= pa_i;
        end
        else
                pai <= pa_i;
 
        // Port B input latches reflect the contents of the output register if the
        // port pin direction is an output.
        if (pb_le) begin
                if (cb1_trans)
                        for (n = 0; n < 12; n = n + 1)
                                pbi <= ddrb[n] ? pbo[n] : pb_i[n];
        end
        else begin
                for (n = 0; n < 12; n = n + 1)
                        pbi <= ddrb[n] ? pbo[n] : pb_i[n];
        end
 
        // Bring ca2 back high on pulse output mode
        if (ca2_mode==3'b100 && ca1_trans)
                ca2o <= 1'b1;
        else if (ca2_mode==3'b101)
                ca2o <= 1'b1;
 
        t1 <= t1 - 2'd1;
        if (pe_t1z) begin
                t1_if <= 1'b1;
                case(t1_mode)
                2'd1:   t1 <= t1l;
                2'd2:
                        begin
                                pbo[pBitsPerByte-1] <= 1'b1;
                                ier[5] <= 1'b0;
                        end
                2'd3:
                        begin
                                pbo[pBitsPerByte-1] <= ~pbo[pBitsPerByte-1];
                                t1 <= t1l;
                        end
                default:        ;
                endcase
        end
 
        case(t2_mode)
        1'd0:   t2 <= t2 - 2'd1;
        1'd1:   if (pb6_ne) t2 <= t2 - 2'd1;
        endcase
        if (pe_t2z) begin
                t2_if <= 1'b1;
                if (t2_mode==1'b0)
                        ier[6] <= 1'b0;
        end
 
        // If counting up interrupt on count greater than or equal to compare
        // register.
        if (t3cmp <= t3) begin
                if (t3_mode==1'b0 && pBitsPerByte > 8)
                        ier[7] <= 1'b0;
                t3_if <= 1'b1;
        end
        else
                t3_if <= 1'b0;
 
        if (wr_t3) begin
                if (t3==t3l)
                        wr_t3 <= 1'b0;
        end
 
        case(sr_mode)
        3'b000: ;
        3'b001:
                begin
                        if (cb1_ne) begin
                                sr_cnt <= sr_cnt - 2'd1;
                                sr <= {sr[pBitsPerByte-2:0],cb2_i};
                                if (sr_cnt==5'd0)
                                        sr_if <= 1'b1;
                        end
                end
        3'b010:
                begin
                        if (cb1_ne) begin
                                sr_cnt <= sr_cnt - 2'd1;
                                sr <= {sr[pBitsPerByte-2:0],cb2_i};
                                if (sr_cnt==5'd0)
                                        sr_if <= 1'b1;
                        end
                end
        3'b011:
                begin
                        if (cb1_ne) begin
                                sr_cnt <= sr_cnt - 2'd1;
                                sr <= {sr[pBitsPerByte-2:0],cb2_i};
                                if (sr_cnt==5'd0)
                                        sr_if <= 1'b1;
                        end
                end
        3'b100:
                if (t2[11:0]==12'h00) begin
                        if (cb1_ne) begin
                                sr <= {sr[pBitsPerByte-2:0],sr[pBitsPerByte-1]};
                        end
                end
        3'b101:
                if (t2[11:0]==12'h00) begin
                        if (sr_cnt != 5'd0) begin
                                if (cb1_ne) begin
                                        sr_cnt <= sr_cnt - 2'd1;
                                        sr <= {sr[pBitsPerByte-2:0],sr[pBitsPerByte-1]};
                                        if (sr_cnt==5'd1)
                                                sr_if <= 1'b1;
                                end
                        end
                end
        3'b110:
                if (sr_cnt != 5'd0) begin
                        if (cb1_ne) begin
                                sr_cnt <= sr_cnt - 2'd1;
                                sr <= {sr[pBitsPerByte-2:0],sr[pBitsPerByte-1]};
                                if (sr_cnt==5'd1)
                                        sr_if <= 1'b1;
                        end
                end
        3'b111:
                if (cb1_ne) begin
                        sr_cnt <= sr_cnt - 2'd1;
                        sr <= {sr[pBitsPerByte-2:0],sr[pBitsPerByte-1]};
                        if (sr_cnt==5'd1)
                                sr_if <= 1'b1;
                end
        endcase
 
        // CB1 output
        case(sr_mode)
        3'b000: ;
        3'b001:
                if (t2[pBitsPerByte-1:0]=={pBitsPerByte{1'b0}})
                        cb1o <= ~cb1o;
        3'b010: cb1o <= ~cb1o;
        3'b011: ;       // used as input
        3'b100:
                if (t2[pBitsPerByte-1:0]=={pBitsPerByte{1'b0}})
                        cb1o <= ~cb1o;
        3'b101:
                if (t2[pBitsPerByte-1:0]=={pBitsPerByte{1'b0}}) begin
                        if (sr_cnt != 5'd0)
                                cb1o <= ~cb1o;
                end
        3'b110:
                if (sr_cnt != 5'd0)
                        cb1o <= ~cb1o;
        3'b111: ;       // used as input
        endcase
 
        // CB2 output
        case(sr_mode)
        3'b000,3'b001,3'b010,3'b011:
                if (cb2_mode==3'b100 && cb1_trans)
                        cb2o <= 1'b1;
                else if (cb2_mode==3'b101)
                        cb2o <= 1'b1;
        3'b100:
                if (t2[pBitsPerByte-1:0]=={pBitsPerByte{1'b0}}) begin
                        if (cb1_ne)
                                cb2o <= sr[pBitsPerByte-1];
                end
        3'b101:
                if (t2[pBitsPerByte-1:0]=={pBitsPerByte{1'b0}}) begin
                        if (sr_cnt != 5'd0) begin
                                if (cb1_ne)
                                        cb2o <= sr[pBitsPerByte-1];
                        end
                        if (sr_cnt==5'd0)
                                cb2o <= cb2_mode[0];
                end
        3'b110:
                if (sr_cnt != 5'd0) begin
                        if (cb1_ne)
                                cb2o <= sr[pBitsPerByte-1];
                end
        3'b111:
                if (cb1_ne)
                        cb2o <= sr[pBitsPerByte-1];
        endcase
 
        if (cs) begin
                if (we_i) begin
                        case(adr_i)
                        `PA:
                                begin
                                        pao <= dat_i;
                                        if (ca2_mode==3'b100||ca2_mode==3'b101)
                                                ca2o <= 1'b0;
                                        ca1_if <= 1'b0;
                                        ca2_if <= 1'b0;
                                end
                        `PB:
                                begin
                                        pbo <= dat_i;
                                        if (cb2_mode==3'b100||cb2_mode==3'b101)
                                                cb2o <= 1'b0;
                                        cb1_if <= 1'b0;
                                        cb2_if <= 1'b0;
                                end
                        `DDRA:
                                begin
                                        ddra <= dat_i;
                                end
                        `DDRB:
                                begin
                                        ddrb <= dat_i;
                                end
                        `T1CL:
                                begin
                                        t1l[pBitsPerByte-1:0] <= dat_i;
                                end
                        `T1CH:
                                begin
                                        t1 <= {dat_i[pBitsPerByte-1:0],t1l[pBitsPerByte-1:0]};
                                        t1_if <= 1'b0;
                                        if (t1_mode[1]==1'b1)
                                                pbo[11] <= 1'b0;
                                end
                        `T1LL:
                                begin
                                        t1l[pBitsPerByte-1:0] <= dat_i;
                                end
                        `T1LH:
                                begin
                                        t1l[pBitsPerByte*2-1:pBitsPerByte] <= {{pBitsPerByte{1'd0}},dat_i};
                                        t1_if <= 1'b0;
                                end
                        `T2CL:
                                begin
                                        t2l[pBitsPerByte-1:0] <= dat_i;
                                end
                        `T2CH:
                                begin
                                        t2 <= {dat_i,t2l[pBitsPerByte-1:0]};
                                        t2_if <= 1'b0;
                                end
                        `PCR:
                                begin
                                        ca1_mode <= dat_i[0];
                                        ca2_mode <= dat_i[3:1];
                                        cb1_mode <= dat_i[4];
                                        cb2_mode <= dat_i[7:5];
                                end
                        `SR:
                                begin
                                        sr <= dat_i;
                                        sr_cnt <= 5'd11;
                                        if (sr_mode==3'b001)
                                                cb1o <= 1'b1;
                                        sr_if <= 1'b0;
                                end
                        `ACR:
                                begin
                                        pa_le <= dat_i[0];
                                        pb_le <= dat_i[1];
                                        sr_mode <= dat_i[4:2];
                                        t2_mode <= dat_i[5];
                                        t1_mode <= dat_i[7:6];
                                        if (pBitsPerByte > 8)
                                                t3_mode <= dat_i[8];
                                end
                        `IER:
                                begin
                                        if (pBitsPerByte==8) begin
                                                if (dat_i[pBitsPerByte-1])
                                                        ierd[6:0] <= ier[6:0] | dat_i[6:0];
                                                else
                                                        ierd[6:0] <= ier[6:0] & ~dat_i[6:0];
                                        end
                                        else begin
                                                if (dat_i[pBitsPerByte-1])
                                                        ierd[7:0] <= ier[7:0] | dat_i[7:0];
                                                else
                                                        ierd[7:0] <= ier[7:0] & ~dat_i[7:0];
                                        end
                                        ier[pBitsPerByte-1] <= 1'b0;
                                  ie_delay <= 6'h01;
                                end
                        `ORA:
                                begin
                                        pao <= dat_i;
                                end
                        `T3CL:  ;
                        `T3CH:  ;
                        `T3LL:
                                begin
                                        t3l[pBitsPerByte-1:0] <= dat_i;
                                end
                        `T3LH:
                                begin
                                        t3l[pBitsPerByte*2-1:pBitsPerByte] <= dat_i;
                                        wr_t3 <= 1'b1;
                                        t3_if <= 1'b0;
                                end
                        `T3CMPL:
                                begin
                                        t3cmp[pBitsPerByte-1:0] <= dat_i;
                                end
                        `T3CMPH:
                                begin
                                        t3cmp[pBitsPerByte*2-1:pBitsPerByte] <= dat_i;
                                end
                        endcase
                        dat_o <= {pBitsPerByte{1'h0}};
                end
                else begin
                        case(adr_i)
                        `PA:
                                begin
                                        dat_o <= pai;
                                        if (ca2_mode==3'b100||ca2_mode==3'b101)
                                                ca2o <= 1'b0;
                                        ca1_if <= 1'b0;
                                        ca2_if <= 1'b0;
                                end
                        `PB:
                                begin
                                        dat_o <= pbi;
                                        cb1_if <= 1'b0;
                                        cb2_if <= 1'b0;
                                end
                        `DDRA:  dat_o <= ddra;
                        `DDRB:  dat_o <= ddrb;
                        `T1CL:
                                begin
                                        dat_o <= t1[pBitsPerByte-1:0];
                                        t1_if <= 1'b0;
                                end
                        `T1CH:
                                dat_o <= t1[pBitsPerByte*2-1:pBitsPerByte];
                        `T1LL:
                                dat_o <= t1l[pBitsPerByte-1:0];
                        `T1LH:
                                dat_o <= t1l[pBitsPerByte*2-1:pBitsPerByte];
                        `T2CL:
                                begin
                                        dat_o <= t2[pBitsPerByte-1:0];
                                        t2_if <= 1'b0;
                                end
                        `T2CH:
                                dat_o <= t2[pBitsPerByte*2-1:pBitsPerByte];
                        `PCR:   dat_o <= {4'd0,cb2_mode,cb1_mode,ca2_mode,ca1_mode};
                        `SR:
                                begin
                                        dat_o <= sr;
                                        if (sr_mode==3'b001)
                                                cb1o <= 1'b1;
                                        sr_cnt <= 5'd11;
                                        sr_if <= 1'b0;
                                end
                        `ACR:   dat_o <= pBitsPerByte==8 ? {t1_mode,t2_mode,sr_mode,pb_le,pa_le} : {3'd0,t3_mode,t1_mode,t2_mode,sr_mode,pb_le,pa_le};
                        `IFR:   dat_o <= pBitsPerByte==8 ? {irq_o,t2_irq,t1_irq,cb1_irq,cb2_irq,sr_irq,ca1_irq,ca2_irq} :
                                                                                                                                                         {irq_o,3'd0,t3_irq,t2_irq,t1_irq,cb1_irq,cb2_irq,sr_irq,ca1_irq,ca2_irq};
                        `IER:   dat_o <= {3'd0,ier};
                        `ORA:   dat_o <= pai;
                        `T3CL:
                                begin
                                        dat_o <= t3[pBitsPerByte-1:0];
                                        t3_if <= 1'b0;
                                end
                        `T3CH:
                                dat_o <= t3[pBitsPerByte*2-1:pBitsPerByte];
                        `T3LL:
                                dat_o <= t3l[pBitsPerByte-1:0];
                        `T3LH:
                                dat_o <= t3l[pBitsPerByte*2-1:pBitsPerByte];
                        `T3CMPL:
                                dat_o <= t3cmp[pBitsPerByte-1:0];
                        `T3CMPH:
                                dat_o <= t3cmp[pBitsPerByte*2-1:pBitsPerByte];
                        default:        dat_o <= {pBitsPerByte{1'h0}};
                        endcase
                end
        end
        // Allows wire-or of data bus
        else
                dat_o <= {pBitsPerByte{1'h0}};
 
        ca2_irq <= ca2_trans & ier[0];
        ca1_irq <= ca1_trans & ier[1];
        sr_irq <= sr_if & ier[2];
        cb2_irq <= cb2_trans & ier[3];
        cb1_irq <= cb1_trans & ier[4];
        t1_irq <= t1_if & ier[5];
        t2_irq <= t2_if & ier[6];
        if (pBitsPerByte > 8)
                t3_irq <= t3_if & ier[7];
        else
                t3_irq <= 1'b0;
 
        irq_o <=
                  (ca2_trans & ier[0])
                | (ca1_trans & ier[1])
                | (sr_if & ier[2])
                | (cb2_trans & ier[3])
                | (cb1_trans & ier[4])
                | (t1_if & ier[5])
                | (t2_if & ier[6])
                | ((t3_if & ier[7]) && pBitsPerByte > 8)
                ;
end
 
// Outputs
 
genvar g;
generate begin : gPorts
        for (g = 0; g < pBitsPerByte; g = g + 1) begin
                assign pa_t[g] = ddra[g];
        end
 
        for (g = 0; g < pBitsPerByte; g = g + 1) begin
                assign pb_t[g] = ddrb[g];
        end
end
endgenerate
 
// CA1 is always an input
 
// CA2,CB1,CB2 output enables
 
assign ca2_t = ca2_mode[2]==1'b0;
assign ca2_o = ca2_mode==3'b100 ? ca2o :
                                                        ca2_mode==3'b101 ? ca2o :
                                                        ca2_mode==3'b110 ? 1'b0 :
                                                        1'b1;
 
assign cb1_t = sr_mode==3'b000 || sr_mode==3'b011 || sr_mode==3'b111;
assign cb1_o = cb1o;
 
assign cb2_t = sr_mode[2]==1'b0 && cb2_mode[2]==1'b0;
assign cb2_o = sr_mode[2]==1'b0 ? (
                                                        cb2_mode[2]==1'b0 ? 1'b1 :
                                                        cb2_mode==3'b100 ? cb2o :
                                                        cb2_mode==3'b101 ? cb2o :
                                                        cb2_mode==3'b110 ? 1'b0 :
                                                        1'b1) :
                                                        cb2o;
 
assign pa_o = pao;
assign pb_o = pbo;
 
endmodule

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[/] [via6522/] [trunk/] [rtl/] [via6522_x12.sv] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2004-2022 Robert Finch, Waterloo`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch@finitron.ca`
6			`// \|\|`
7			`//`
8			`// via6522_x12.sv`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see .`
22			`//`
23			`// ============================================================================`
24
25			`define PB 5'd0
26			`define PA 5'd1
27			`define DDRB 5'd2
28			`define DDRA 5'd3
29			`define T1CL 5'd4
30			`define T1CH 5'd5
31			`define T1LL 5'd6
32			`define T1LH 5'd7
33			`define T2CL 5'd8
34			`define T2CH 5'd9
35			`define SR 5'd10
36			`define ACR 5'd11
37			`define PCR 5'd12
38			`define IFR 5'd13
39			`define IER 5'd14
40			`define ORA 5'd15
41			`define T3CL 5'd16
42			`define T3CH 5'd17
43			`define T3LL 5'd18
44			`define T3LH 5'd19
45			`define T3CMPL 5'd20
46			`define T3CMPH 5'd21
47
48			`module via6522_x12 (rst_i, clk_i, wc_clk_i, irq_o, cs_i,`
49			`cyc_i, stb_i, ack_o, we_i, adr_i, dat_i, dat_o,`
50			`ca1, ca2_i, ca2_o, ca2_t, cb1_i, cb1_o, cb1_t, cb2_i, cb2_o, cb2_t,`
51			`pa_i, pb_i, pa_o, pb_o, pa_t, pb_t,`
52			`t1_if, t2_if, t3_if`
53			`);`
54			`parameter pBitsPerByte=12;`
55			`input rst_i;`
56			`input clk_i;`
57			`input wc_clk_i;`
58			`output reg irq_o;`
59			`input cs_i;`
60			`input cyc_i;`
61			`input stb_i;`
62			`output ack_o;`
63			`input we_i;`
64			`input [4:0] adr_i;`
65			`input [pBitsPerByte-1:0] dat_i;`
66			`output reg [pBitsPerByte-1:0] dat_o;`
67
68			`input ca1;`
69			`input ca2_i;`
70			`output ca2_o;`
71			`output ca2_t;`
72			`input cb1_i;`
73			`output cb1_o;`
74			`output cb1_t;`
75			`input cb2_i;`
76			`output cb2_o;`
77			`output cb2_t;`
78			`input [pBitsPerByte-1:0] pa_i;`
79			`input [pBitsPerByte-1:0] pb_i;`
80			`output [pBitsPerByte-1:0] pa_o;`
81			`output [pBitsPerByte-1:0] pb_o;`
82			`output reg [pBitsPerByte-1:0] pa_t;`
83			`output reg [pBitsPerByte-1:0] pb_t;`
84
85			`output reg t1_if; // timer 1 interrupt flag`
86			`output reg t2_if; // timer 2 interrupt flag`
87			`output reg t3_if; // timer 3 interrupt flag`
88
89			`integer n;`
90
91			`wire cs = cs_i & cyc_i & stb_i;`
92
93			`ack_gen #(`
94			`.READ_STAGES(2),`
95			`.WRITE_STAGES(0),`
96			`.REGISTER_OUTPUT(1)`
97			`) uag1`
98			`(`
99			`.rst_i(rst_i),`
100			`.clk_i(clk_i),`
101			`.ce_i(1'b1),`
102			`.i(cs),`
103			`.we_i(cs & we_i),`
104			`.o(ack_o),`
105			`.rid_i(0),`
106			`.wid_i(0),`
107			`.rid_o(),`
108			`.wid_o()`
109			`);`
110
111			`reg [5:0] ie_delay;`
112			`reg [8:0] ier, ierd; // interrupt enable register / delayed interrupt enable register`
113			`reg [pBitsPerByte-1:0] pai, pbi; // input registers`
114			`reg [pBitsPerByte-1:0] pao, pbo; // output latches`
115			`reg [pBitsPerByte-1:0] pal, pbl; // input latches`
116			`reg pa_le, pb_le; // latching enable`
117			`reg [pBitsPerByte-1:0] ddra, ddrb; // data direction registers`
118			`reg cb1o, cb2o, ca2o;`
119			`reg [1:0] t1_mode;`
120			`reg t2_mode;`
121			`reg t3_mode;`
122			`reg [pBitsPerByte*2-1:0] t1, t2, t3; // 24 bit timers`
123			`reg [pBitsPerByte*2-1:0] t3cmp;`
124			`reg t3_access;`
125			`reg t1_64, t2_64;`
126			`reg [pBitsPerByte*2-1:0] t1l;`
127			`reg [pBitsPerByte*2-1:0] t2l;`
128			`reg [pBitsPerByte*2-1:0] t3l;`
129			`wire ca1_trans, ca2_trans; // active transitions`
130			`wire cb1_trans, cb2_trans;`
131			`reg ca1_mode;`
132			`reg cb1_mode;`
133			`reg [2:0] ca2_mode;`
134			`reg [2:0] cb2_mode;`
135			`reg [4:0] sr_cnt; // shift register counter`
136			`reg [pBitsPerByte-1:0] sr; // shift register`
137			`reg sr_32; // shift register 32 bit mode`
138			`reg [2:0] sr_mode; // shift register mode`
139			`reg sr_if;`
140			`wire ca1_pe, ca1_ne, ca1_ee;`
141			`wire ca2_pe, ca2_ne, ca2_ee;`
142			`wire cb1_pe, cb1_ne, cb1_ee;`
143			`reg ca1_if, cb1_if;`
144			`reg ca2_if, cb2_if;`
145			`wire pb6_ne;`
146			`reg ca1_irq, ca2_irq;`
147			`reg cb1_irq, cb2_irq;`
148			`reg t1_irq, t2_irq, t3_irq;`
149			`reg sr_irq;`
150			`wire pe_t1z, pe_t2z, pe_t3z;`
151
152			`edge_det ued1 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(ca1), .pe(ca1_pe), .ne(ca1_ne), .ee(ca1_ee));`
153			`edge_det ued2 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(ca2_i), .pe(ca2_pe), .ne(ca2_ne), .ee(ca2_ee));`
154			`edge_det ued3 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cb1_i), .pe(cb1_pe), .ne(cb1_ne), .ee(cb1_ee));`
155			`edge_det ued4 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cb2_i), .pe(cb2_pe), .ne(cb2_ne), .ee(cb2_ee));`
156			`edge_det ued5 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(pb_i[10]), .pe(), .ne(pb6_ne), .ee());`
157			`edge_det ued6 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(t3=={pBitsPerByte*2{1'd0}}), .pe(pe_t3z), .ne(), .ee());`
158			`edge_det ued7 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(t2=={pBitsPerByte*2{1'd0}}), .pe(pe_t2z), .ne(), .ee());`
159			`edge_det ued8 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(t1=={pBitsPerByte*2{1'd0}}), .pe(pe_t1z), .ne(), .ee());`
160
161
162			`assign ca1_trans = (ca1_mode & ca1_pe) \| (~ca1_mode & ca1_ne);`
163			`assign ca2_trans = (ca2_mode[2:1]==2'b00&&ca2_ne)\|\|(ca2_mode[2:1]==2'b01&&ca2_pe);`
164			`assign cb1_trans = (cb1_mode & cb1_pe) \| (~cb1_mode & cb1_ne);`
165			`assign cb2_trans = (cb2_mode[2:1]==2'b00&&cb2_ne)\|\|(cb2_mode[2:1]==2'b01&&cb2_pe);`
166
167			`reg wr_t3;`
168
169			`always @(posedge wc_clk_i)`
170			`if (rst_i)`
171			`t3 <= {pBitsPerByte*2{1'd1}};`
172			`else begin`
173			`t3 <= t3 + 2'd1;`
174			`if (wr_t3)`
175			`t3 <= t3l;`
176			`end`
177
178			`always @(posedge clk_i)`
179			`if (rst_i) begin`
180			`ddra <= {pBitsPerByte{1'd0}};`
181			`ddrb <= {pBitsPerByte{1'd0}};`
182			`ca1_irq <= 1'b0;`
183			`ca2_irq <= 1'b0;`
184			`cb1_irq <= 1'b0;`
185			`cb2_irq <= 1'b0;`
186			`ca2o <= 1'b0;`
187			`cb1o <= 1'b0;`
188			`cb2o <= 1'b0;`
189			`t1_64 <= 1'b0;`
190			`t2_64 <= 1'b0;`
191			`sr_mode <= 3'b000;`
192			`sr_32 <= 1'b0;`
193			`sr_if <= 1'b0;`
194			`t1 <= {pBitsPerByte*2{1'd1}};`
195			`t1_if <= 1'b0;`
196			`t2 <= {pBitsPerByte*2{1'd1}};`
197			`t2_if <= 1'b0;`
198			`t3_if <= 1'b0;`
199			`t3_access <= 1'b0;`
200			`wr_t3 <= 1'b0;`
201			`ier <= 9'h00;`
202			`ie_delay <= 6'h00;`
203			`end`
204			`else begin`
205
206			`if (ie_delay!=6'h00)`
207			`ie_delay <= ie_delay - 2'd1;`
208			`if (ie_delay==6'h01)`
209			`ier <= ierd;`
210
211			`// Port A,B input latching`
212			`// Port A input latches always reflect the input pins.`
213			`if (pa_le) begin`
214			`if (ca1_trans)`
215			`pai <= pa_i;`
216			`end`
217			`else`
218			`pai <= pa_i;`
219
220			`// Port B input latches reflect the contents of the output register if the`
221			`// port pin direction is an output.`
222			`if (pb_le) begin`
223			`if (cb1_trans)`
224			`for (n = 0; n < 12; n = n + 1)`
225			`pbi <= ddrb[n] ? pbo[n] : pb_i[n];`
226			`end`
227			`else begin`
228			`for (n = 0; n < 12; n = n + 1)`
229			`pbi <= ddrb[n] ? pbo[n] : pb_i[n];`
230			`end`
231
232			`// Bring ca2 back high on pulse output mode`
233			`if (ca2_mode==3'b100 && ca1_trans)`
234			`ca2o <= 1'b1;`
235			`else if (ca2_mode==3'b101)`
236			`ca2o <= 1'b1;`
237
238			`t1 <= t1 - 2'd1;`
239			`if (pe_t1z) begin`
240			`t1_if <= 1'b1;`
241			`case(t1_mode)`
242			`2'd1: t1 <= t1l;`
243			`2'd2:`
244			`begin`
245			`pbo[pBitsPerByte-1] <= 1'b1;`
246			`ier[5] <= 1'b0;`
247			`end`
248			`2'd3:`
249			`begin`
250			`pbo[pBitsPerByte-1] <= ~pbo[pBitsPerByte-1];`
251			`t1 <= t1l;`
252			`end`
253			`default: ;`
254			`endcase`
255			`end`
256
257			`case(t2_mode)`
258			`1'd0: t2 <= t2 - 2'd1;`
259			`1'd1: if (pb6_ne) t2 <= t2 - 2'd1;`
260			`endcase`
261			`if (pe_t2z) begin`
262			`t2_if <= 1'b1;`
263			`if (t2_mode==1'b0)`
264			`ier[6] <= 1'b0;`
265			`end`
266
267			`// If counting up interrupt on count greater than or equal to compare`
268			`// register.`
269			`if (t3cmp <= t3) begin`
270			`if (t3_mode==1'b0 && pBitsPerByte > 8)`
271			`ier[7] <= 1'b0;`
272			`t3_if <= 1'b1;`
273			`end`
274			`else`
275			`t3_if <= 1'b0;`
276
277			`if (wr_t3) begin`
278			`if (t3==t3l)`
279			`wr_t3 <= 1'b0;`
280			`end`
281
282			`case(sr_mode)`
283			`3'b000: ;`
284			`3'b001:`
285			`begin`
286			`if (cb1_ne) begin`
287			`sr_cnt <= sr_cnt - 2'd1;`
288			`sr <= {sr[pBitsPerByte-2:0],cb2_i};`
289			`if (sr_cnt==5'd0)`
290			`sr_if <= 1'b1;`
291			`end`
292			`end`
293			`3'b010:`
294			`begin`
295			`if (cb1_ne) begin`
296			`sr_cnt <= sr_cnt - 2'd1;`
297			`sr <= {sr[pBitsPerByte-2:0],cb2_i};`
298			`if (sr_cnt==5'd0)`
299			`sr_if <= 1'b1;`
300			`end`
301			`end`
302			`3'b011:`
303			`begin`
304			`if (cb1_ne) begin`
305			`sr_cnt <= sr_cnt - 2'd1;`
306			`sr <= {sr[pBitsPerByte-2:0],cb2_i};`
307			`if (sr_cnt==5'd0)`
308			`sr_if <= 1'b1;`
309			`end`
310			`end`
311			`3'b100:`
312			`if (t2[11:0]==12'h00) begin`
313			`if (cb1_ne) begin`
314			`sr <= {sr[pBitsPerByte-2:0],sr[pBitsPerByte-1]};`
315			`end`
316			`end`
317			`3'b101:`
318			`if (t2[11:0]==12'h00) begin`
319			`if (sr_cnt != 5'd0) begin`
320			`if (cb1_ne) begin`
321			`sr_cnt <= sr_cnt - 2'd1;`
322			`sr <= {sr[pBitsPerByte-2:0],sr[pBitsPerByte-1]};`
323			`if (sr_cnt==5'd1)`
324			`sr_if <= 1'b1;`
325			`end`
326			`end`
327			`end`
328			`3'b110:`
329			`if (sr_cnt != 5'd0) begin`
330			`if (cb1_ne) begin`
331			`sr_cnt <= sr_cnt - 2'd1;`
332			`sr <= {sr[pBitsPerByte-2:0],sr[pBitsPerByte-1]};`
333			`if (sr_cnt==5'd1)`
334			`sr_if <= 1'b1;`
335			`end`
336			`end`
337			`3'b111:`
338			`if (cb1_ne) begin`
339			`sr_cnt <= sr_cnt - 2'd1;`
340			`sr <= {sr[pBitsPerByte-2:0],sr[pBitsPerByte-1]};`
341			`if (sr_cnt==5'd1)`
342			`sr_if <= 1'b1;`
343			`end`
344			`endcase`
345
346			`// CB1 output`
347			`case(sr_mode)`
348			`3'b000: ;`
349			`3'b001:`
350			`if (t2[pBitsPerByte-1:0]=={pBitsPerByte{1'b0}})`
351			`cb1o <= ~cb1o;`
352			`3'b010: cb1o <= ~cb1o;`
353			`3'b011: ; // used as input`
354			`3'b100:`
355			`if (t2[pBitsPerByte-1:0]=={pBitsPerByte{1'b0}})`
356			`cb1o <= ~cb1o;`
357			`3'b101:`
358			`if (t2[pBitsPerByte-1:0]=={pBitsPerByte{1'b0}}) begin`
359			`if (sr_cnt != 5'd0)`
360			`cb1o <= ~cb1o;`
361			`end`
362			`3'b110:`
363			`if (sr_cnt != 5'd0)`
364			`cb1o <= ~cb1o;`
365			`3'b111: ; // used as input`
366			`endcase`
367
368			`// CB2 output`
369			`case(sr_mode)`
370			`3'b000,3'b001,3'b010,3'b011:`
371			`if (cb2_mode==3'b100 && cb1_trans)`
372			`cb2o <= 1'b1;`
373			`else if (cb2_mode==3'b101)`
374			`cb2o <= 1'b1;`
375			`3'b100:`
376			`if (t2[pBitsPerByte-1:0]=={pBitsPerByte{1'b0}}) begin`
377			`if (cb1_ne)`
378			`cb2o <= sr[pBitsPerByte-1];`
379			`end`
380			`3'b101:`
381			`if (t2[pBitsPerByte-1:0]=={pBitsPerByte{1'b0}}) begin`
382			`if (sr_cnt != 5'd0) begin`
383			`if (cb1_ne)`
384			`cb2o <= sr[pBitsPerByte-1];`
385			`end`
386			`if (sr_cnt==5'd0)`
387			`cb2o <= cb2_mode[0];`
388			`end`
389			`3'b110:`
390			`if (sr_cnt != 5'd0) begin`
391			`if (cb1_ne)`
392			`cb2o <= sr[pBitsPerByte-1];`
393			`end`
394			`3'b111:`
395			`if (cb1_ne)`
396			`cb2o <= sr[pBitsPerByte-1];`
397			`endcase`
398
399			`if (cs) begin`
400			`if (we_i) begin`
401			`case(adr_i)`
402			`PA:
403			`begin`
404			`pao <= dat_i;`
405			`if (ca2_mode==3'b100\|\|ca2_mode==3'b101)`
406			`ca2o <= 1'b0;`
407			`ca1_if <= 1'b0;`
408			`ca2_if <= 1'b0;`
409			`end`
410			`PB:
411			`begin`
412			`pbo <= dat_i;`
413			`if (cb2_mode==3'b100\|\|cb2_mode==3'b101)`
414			`cb2o <= 1'b0;`
415			`cb1_if <= 1'b0;`
416			`cb2_if <= 1'b0;`
417			`end`
418			`DDRA:
419			`begin`
420			`ddra <= dat_i;`
421			`end`
422			`DDRB:
423			`begin`
424			`ddrb <= dat_i;`
425			`end`
426			`T1CL:
427			`begin`
428			`t1l[pBitsPerByte-1:0] <= dat_i;`
429			`end`
430			`T1CH:
431			`begin`
432			`t1 <= {dat_i[pBitsPerByte-1:0],t1l[pBitsPerByte-1:0]};`
433			`t1_if <= 1'b0;`
434			`if (t1_mode[1]==1'b1)`
435			`pbo[11] <= 1'b0;`
436			`end`
437			`T1LL:
438			`begin`
439			`t1l[pBitsPerByte-1:0] <= dat_i;`
440			`end`
441			`T1LH:
442			`begin`
443			`t1l[pBitsPerByte*2-1:pBitsPerByte] <= {{pBitsPerByte{1'd0}},dat_i};`
444			`t1_if <= 1'b0;`
445			`end`
446			`T2CL:
447			`begin`
448			`t2l[pBitsPerByte-1:0] <= dat_i;`
449			`end`
450			`T2CH:
451			`begin`
452			`t2 <= {dat_i,t2l[pBitsPerByte-1:0]};`
453			`t2_if <= 1'b0;`
454			`end`
455			`PCR:
456			`begin`
457			`ca1_mode <= dat_i[0];`
458			`ca2_mode <= dat_i[3:1];`
459			`cb1_mode <= dat_i[4];`
460			`cb2_mode <= dat_i[7:5];`
461			`end`
462			`SR:
463			`begin`
464			`sr <= dat_i;`
465			`sr_cnt <= 5'd11;`
466			`if (sr_mode==3'b001)`
467			`cb1o <= 1'b1;`
468			`sr_if <= 1'b0;`
469			`end`
470			`ACR:
471			`begin`
472			`pa_le <= dat_i[0];`
473			`pb_le <= dat_i[1];`
474			`sr_mode <= dat_i[4:2];`
475			`t2_mode <= dat_i[5];`
476			`t1_mode <= dat_i[7:6];`
477			`if (pBitsPerByte > 8)`
478			`t3_mode <= dat_i[8];`
479			`end`
480			`IER:
481			`begin`
482			`if (pBitsPerByte==8) begin`
483			`if (dat_i[pBitsPerByte-1])`
484			`ierd[6:0] <= ier[6:0] \| dat_i[6:0];`
485			`else`
486			`ierd[6:0] <= ier[6:0] & ~dat_i[6:0];`
487			`end`
488			`else begin`
489			`if (dat_i[pBitsPerByte-1])`
490			`ierd[7:0] <= ier[7:0] \| dat_i[7:0];`
491			`else`
492			`ierd[7:0] <= ier[7:0] & ~dat_i[7:0];`
493			`end`
494			`ier[pBitsPerByte-1] <= 1'b0;`
495			`ie_delay <= 6'h01;`
496			`end`
497			`ORA:
498			`begin`
499			`pao <= dat_i;`
500			`end`
501			`T3CL: ;
502			`T3CH: ;
503			`T3LL:
504			`begin`
505			`t3l[pBitsPerByte-1:0] <= dat_i;`
506			`end`
507			`T3LH:
508			`begin`
509			`t3l[pBitsPerByte*2-1:pBitsPerByte] <= dat_i;`
510			`wr_t3 <= 1'b1;`
511			`t3_if <= 1'b0;`
512			`end`
513			`T3CMPL:
514			`begin`
515			`t3cmp[pBitsPerByte-1:0] <= dat_i;`
516			`end`
517			`T3CMPH:
518			`begin`
519			`t3cmp[pBitsPerByte*2-1:pBitsPerByte] <= dat_i;`
520			`end`
521			`endcase`
522			`dat_o <= {pBitsPerByte{1'h0}};`
523			`end`
524			`else begin`
525			`case(adr_i)`
526			`PA:
527			`begin`
528			`dat_o <= pai;`
529			`if (ca2_mode==3'b100\|\|ca2_mode==3'b101)`
530			`ca2o <= 1'b0;`
531			`ca1_if <= 1'b0;`
532			`ca2_if <= 1'b0;`
533			`end`
534			`PB:
535			`begin`
536			`dat_o <= pbi;`
537			`cb1_if <= 1'b0;`
538			`cb2_if <= 1'b0;`
539			`end`
540			`DDRA: dat_o <= ddra;
541			`DDRB: dat_o <= ddrb;
542			`T1CL:
543			`begin`
544			`dat_o <= t1[pBitsPerByte-1:0];`
545			`t1_if <= 1'b0;`
546			`end`
547			`T1CH:
548			`dat_o <= t1[pBitsPerByte*2-1:pBitsPerByte];`
549			`T1LL:
550			`dat_o <= t1l[pBitsPerByte-1:0];`
551			`T1LH:
552			`dat_o <= t1l[pBitsPerByte*2-1:pBitsPerByte];`
553			`T2CL:
554			`begin`
555			`dat_o <= t2[pBitsPerByte-1:0];`
556			`t2_if <= 1'b0;`
557			`end`
558			`T2CH:
559			`dat_o <= t2[pBitsPerByte*2-1:pBitsPerByte];`
560			`PCR: dat_o <= {4'd0,cb2_mode,cb1_mode,ca2_mode,ca1_mode};
561			`SR:
562			`begin`
563			`dat_o <= sr;`
564			`if (sr_mode==3'b001)`
565			`cb1o <= 1'b1;`
566			`sr_cnt <= 5'd11;`
567			`sr_if <= 1'b0;`
568			`end`
569			`ACR: dat_o <= pBitsPerByte==8 ? {t1_mode,t2_mode,sr_mode,pb_le,pa_le} : {3'd0,t3_mode,t1_mode,t2_mode,sr_mode,pb_le,pa_le};
570			`IFR: dat_o <= pBitsPerByte==8 ? {irq_o,t2_irq,t1_irq,cb1_irq,cb2_irq,sr_irq,ca1_irq,ca2_irq} :
571			`{irq_o,3'd0,t3_irq,t2_irq,t1_irq,cb1_irq,cb2_irq,sr_irq,ca1_irq,ca2_irq};`
572			`IER: dat_o <= {3'd0,ier};
573			`ORA: dat_o <= pai;
574			`T3CL:
575			`begin`
576			`dat_o <= t3[pBitsPerByte-1:0];`
577			`t3_if <= 1'b0;`
578			`end`
579			`T3CH:
580			`dat_o <= t3[pBitsPerByte*2-1:pBitsPerByte];`
581			`T3LL:
582			`dat_o <= t3l[pBitsPerByte-1:0];`
583			`T3LH:
584			`dat_o <= t3l[pBitsPerByte*2-1:pBitsPerByte];`
585			`T3CMPL:
586			`dat_o <= t3cmp[pBitsPerByte-1:0];`
587			`T3CMPH:
588			`dat_o <= t3cmp[pBitsPerByte*2-1:pBitsPerByte];`
589			`default: dat_o <= {pBitsPerByte{1'h0}};`
590			`endcase`
591			`end`
592			`end`
593			`// Allows wire-or of data bus`
594			`else`
595			`dat_o <= {pBitsPerByte{1'h0}};`
596
597			`ca2_irq <= ca2_trans & ier[0];`
598			`ca1_irq <= ca1_trans & ier[1];`
599			`sr_irq <= sr_if & ier[2];`
600			`cb2_irq <= cb2_trans & ier[3];`
601			`cb1_irq <= cb1_trans & ier[4];`
602			`t1_irq <= t1_if & ier[5];`
603			`t2_irq <= t2_if & ier[6];`
604			`if (pBitsPerByte > 8)`
605			`t3_irq <= t3_if & ier[7];`
606			`else`
607			`t3_irq <= 1'b0;`
608
609			`irq_o <=`
610			`(ca2_trans & ier[0])`
611			`\| (ca1_trans & ier[1])`
612			`\| (sr_if & ier[2])`
613			`\| (cb2_trans & ier[3])`
614			`\| (cb1_trans & ier[4])`
615			`\| (t1_if & ier[5])`
616			`\| (t2_if & ier[6])`
617			`\| ((t3_if & ier[7]) && pBitsPerByte > 8)`
618			`;`
619			`end`
620
621			`// Outputs`
622
623			`genvar g;`
624			`generate begin : gPorts`
625			`for (g = 0; g < pBitsPerByte; g = g + 1) begin`
626			`assign pa_t[g] = ddra[g];`
627			`end`
628
629			`for (g = 0; g < pBitsPerByte; g = g + 1) begin`
630			`assign pb_t[g] = ddrb[g];`
631			`end`
632			`end`
633			`endgenerate`
634
635			`// CA1 is always an input`
636
637			`// CA2,CB1,CB2 output enables`
638
639			`assign ca2_t = ca2_mode[2]==1'b0;`
640			`assign ca2_o = ca2_mode==3'b100 ? ca2o :`
641			`ca2_mode==3'b101 ? ca2o :`
642			`ca2_mode==3'b110 ? 1'b0 :`
643			`1'b1;`
644
645			`assign cb1_t = sr_mode==3'b000 \|\| sr_mode==3'b011 \|\| sr_mode==3'b111;`
646			`assign cb1_o = cb1o;`
647
648			`assign cb2_t = sr_mode[2]==1'b0 && cb2_mode[2]==1'b0;`
649			`assign cb2_o = sr_mode[2]==1'b0 ? (`
650			`cb2_mode[2]==1'b0 ? 1'b1 :`
651			`cb2_mode==3'b100 ? cb2o :`
652			`cb2_mode==3'b101 ? cb2o :`
653			`cb2_mode==3'b110 ? 1'b0 :`
654			`1'b1) :`
655			`cb2o;`
656
657			`assign pa_o = pao;`
658			`assign pb_o = pbo;`
659
660			`endmodule`