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//////////////////////////////////////////////////////////////////////////////
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//
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// Xilinx, Inc. 2005 www.xilinx.com
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//
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// XAPP 486 - 7:1 LVDS in Spartan3E Devices
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//
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//////////////////////////////////////////////////////////////////////////////
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//
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// File name : serdes_4b_7to1_wrapper.v
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//
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// Description : Wrapper for generic 4-bit serdes_4b_7to1 for Spartan 3E
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//
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// Date - revision : October 16th 2006 - v 1.4
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//
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// Version 1.4 : Brings the DDR registers to the top level and no
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// longer uses 'C0' alignment
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//
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// Author : NJS
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//
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// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
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// provided to you "as is". Xilinx and its licensors make and you
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// receive no warranties or conditions, express, implied,
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// statutory or otherwise, and Xilinx specifically disclaims any
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// implied warranties of merchantability, non-infringement,or
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// fitness for a particular purpose. Xilinx does not warrant that
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// the functions contained in these designs will meet your
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// requirements, or that the operation of these designs will be
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// uninterrupted or error free, or that defects in the Designs
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// will be corrected. Furthermore, Xilinx does not warrantor
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// make any representations regarding use or the results of the
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// use of the designs in terms of correctness, accuracy,
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// reliability, or otherwise.
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//
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// LIMITATION OF LIABILITY. In no event will Xilinx or its
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// licensors be liable for any loss of data, lost profits,cost
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// or procurement of substitute goods or services, or for any
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// special, incidental, consequential, or indirect damages
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// arising from the use or operation of the designs or
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// accompanying documentation, however caused and on any theory
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// of liability. This limitation will apply even if Xilinx
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// has been advised of the possibility of such damage. This
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// limitation shall apply not-withstanding the failure of the
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// essential purpose of any limited remedies herein.
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//
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// Copyright © 2005 Xilinx, Inc.
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// All rights reserved
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//
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//////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1ps
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module serdes_4b_7to1_wrapper (
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input clk, // clock
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input clkx3p5, // 3.5 times clock
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input clkx3p5not, // not 3.5 times clock
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input [27:0] datain, // input data
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input rst, // reset
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output [7:0] dataout, // output data
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output [1:0] clkout) ; // output clock (1x)
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(* RLOC = "x0y0" *) serdes_4b_7to1 tx0(
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.clk (clk),
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.clkx3p5 (clkx3p5),
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.clkx3p5not (clkx3p5not),
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.datain (datain),
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.rst (rst),
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.dataout (dataout),
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.clkout (clkout)) ;
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endmodule
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