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[/] [vitdec/] [trunk/] [acs.v] - Blame information for rev 3

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Line No. Rev Author Line
1 3 yuhuang198 
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date:    11:50:09 12/01/2010
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// Design Name:
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// Module Name:    acs
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module acs(clk, rst, frame_rst, en, in1, in2, out);
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parameter       r                                       =       1,      //r = 2 radix4; r = 3 radix8; r = 1 radix2;
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                                n                                       =       2,  //current version only support n = 2
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                                m                                       =       7,
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                                k                                       =       1,
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                                nu                                      =       6,
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                                state                           =       64,
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                                tb_length               =       128,
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                                tb_length_log   =       7,
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                                bitwise                 =       1,
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                                reglen                  =       11;
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input                   clk, rst, frame_rst, en;
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input           [0:bitwise-1]                    in1;
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input           [0:bitwise-1]                    in2;
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input           [0:bitwise-1]                    in3;
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input           [0:bitwise-1]                    in4;
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input           [0:bitwise-1]                    in5;
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input           [0:bitwise-1]                    in6;
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input           [0:bitwise-1]                    in7;
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input           [0:bitwise-1]                    in8;
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output  [0:state-1]                              out;
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wire            [0:state-1]                              out;
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reg             [0:bitwise+1+(r-1)-1]                                            hamm_dist1                                      [0:2**(n*r)-1];
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wire            [0:reglen-1]                     branch_metric_calc_w            [0:2*r-1][0:state-1];             //wire
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wire            [0:2*r*(2*r-1)-1]                decision_tmp_w                          [0:state-1];                                     //wire
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reg             [0:reglen-1]                     branch_metric                           [0:state-1];                                     //reg
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reg             [0:r-1]                                  decision                                                [0:state-1];                                     //reg
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integer                 i, j, fid, rcv, hdf, bmf;
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reg             [0:(r*n)-1]                              hamming_index_reg                       [0:state-1][0:2**r-1];
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reg             [0:3]                                    en_reg;
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genvar                  gi, gj, gk, gii, gjj, gkk;
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//`include "hamming_index_16.v"
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//`include "hamming_index_8.v"
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//`include "hamming_index_4.v"
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//`include "hamming_index_2.v"
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initial
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begin
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        hdf = $fopen("hamming_dist.txt","w");
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        bmf = $fopen("branch_metric.txt","w");
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        if (r == 1)
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                fid = $fopen("hamming_index_reg_2.txt", "r");
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        else if (r == 2)
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                fid = $fopen("hamming_index_reg_4.txt", "r");
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        else if (r == 8)
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                fid = $fopen("hamming_index_reg_8.txt", "r");
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        for (i = 0; i < state; i = i + 1)
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                for (j = 0; j < 2**r; j = j + 1)
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                        rcv = $fscanf(fid, "%b", hamming_index_reg[i][j]);
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end
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always @(clk, rst, en)
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begin
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        if (rst == 0)
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                en_reg = 0;
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        else if (clk == 1)
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                if (frame_rst == 1)
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                        en_reg = 0;
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                else if (en == 1)
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                        en_reg = { en, en_reg[0:2] };
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end
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always @ (clk, rst, en)
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begin
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        if(rst == 0)
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        begin
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                hamm_dist1[0] = 0;
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                hamm_dist1[1] = 0;
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                hamm_dist1[2] = 0;
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                hamm_dist1[3] = 0;
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        end
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        else if(clk == 1)
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        begin
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                if(frame_rst == 1)
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                begin
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                        hamm_dist1[0] = 0;
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                        hamm_dist1[1] = 0;
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                        hamm_dist1[2] = 0;
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                        hamm_dist1[3] = 0;
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                end
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                else if(en_reg[1] == 1)
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                begin
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                        hamm_dist1[0] = {1'b0, ( in1)} + {1'b0, ( in2)};
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                        hamm_dist1[1] = {1'b0, ( in1)} + {1'b0, (~in2)};
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                        hamm_dist1[2] = {1'b0, (~in1)} + {1'b0, ( in2)};
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                        hamm_dist1[3] = {1'b0, (~in1)} + {1'b0, (~in2)};
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                        for (i = 0; i < 2**(n*r); i = i + 1)
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                                $fdisplay(hdf, "%d", hamm_dist1[i]);
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                end
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        end
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end
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generate for (gi = 0; gi < state; gi = gi + 1) begin : g10
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        for (gj = 0; gj < 2**r; gj = gj + 1) begin : g11
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                assign branch_metric_calc_w[gj][gi] = branch_metric[(gi*(2**r)+gj)%state] + hamm_dist1[hamming_index_reg[gi][gj]];
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        end
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end
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endgenerate
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generate for (gi = 0; gi < state; gi = gi + 1) begin : g12
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        assign decision_tmp_w[gi] = branch_metric_calc_w[0][gi] > branch_metric_calc_w[1][gi];
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end
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endgenerate
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generate for (gi = 0; gi < state; gi = gi + 1)
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begin : g15
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        always @ (clk, rst)
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        begin
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                if (rst == 0)
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                        decision[gi] = 0;
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                else if (clk == 1)
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                        if (frame_rst == 1)
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                                decision[gi] = 0;
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                        else if (en_reg[2] == 1)
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                                decision[gi] = decision_tmp_w[gi];
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        end
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end
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endgenerate
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generate for (gi = 0; gi < state; gi = gi + 1)
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begin : g16
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        always @ (clk, rst)
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        begin : g16_1
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                if (rst == 0)
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                        branch_metric[gi] = 0;
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                else if (clk == 1)
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                        if (frame_rst == 1)
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                                branch_metric[gi] = 0;
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                        else if (en_reg[2] == 1)
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                                branch_metric[gi] = branch_metric_calc_w[decision_tmp_w[gi]][gi];
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        end
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end
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endgenerate
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always @ (posedge clk)
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begin
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        for (i = 0; i < state; i = i + 1)
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                $fwrite(bmf, "cmp %4.3d with %4.3d, decision is %2.1d, decision_w is %2.1d, result is %4.3d\n", branch_metric_calc_w[0][i], branch_metric_calc_w[1][i], decision[i], decision_tmp_w[i], branch_metric[i]);
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        $fwrite(bmf, "================================================================================================================================\n");
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end
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generate for (gi = 0; gi < state; gi = gi + 1)
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begin : assgn_out
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        assign out[gi] = decision[gi];
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end
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endgenerate;
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endmodule

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