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[/] [vitdec/] [trunk/] [tb_ram.v] - Blame information for rev 3

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Line No. Rev Author Line
1 3 yuhuang198 
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date:    09:38:56 11/29/2010
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// Design Name:
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// Module Name:    tb_ram
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_ram(rst, clk, frame_rst, en, in1, in2, in3, in4, out_tb, out_dc);
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parameter               state                                   =       64;
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parameter               nu                                              =       6;
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parameter               tb_length                       =       128;
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parameter               tb_length_log           =       7;
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parameter               radix                                   =       4;              //1: radix-2;   2: radix-4              3: radix-8
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localparam              data_width                      =       state;
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localparam              ram_depth                       =       tb_length/radix;
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localparam              addr_width                      =       tb_length_log;
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input                                                           rst, clk, frame_rst, en;
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input           [0:data_width-1] in1;
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input           [0:data_width-1] in2;
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input           [0:data_width-1] in3;
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input           [0:data_width-1] in4;
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output  [0:radix-1]                      out_tb;
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output  [0:radix-1]                      out_dc;
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reg     [0:3]                                    en_reg;
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reg     [0:nu-1]                         tb_state;
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reg     [0:nu-1]                         dec_state;
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wire    [0:radix-1]                      tb_tmp;
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wire    [0:radix-1]                      dc_tmp;
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wire    [0:radix-1]                      dc_tmp_tmp;
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wire    [0:data_width-1] out_w                   [0:3][0:radix-1];
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reg     [0:data_width-1] in_reg  [0:radix-1];
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reg     [0:addr_width-1] counter_tb              ;
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reg     [0:addr_width-1] counter_tbn             ;
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wire    [0:addr_width-1] counter_tb_w    ;
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wire    [0:addr_width-1] counter_tbn_w   ;
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reg     [0:1]            counter_id0             ;
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reg     [0:1]            counter_id1             ;
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reg     [0:1]            counter_id2             ;
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reg     [0:1]            counter_id3             ;
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wire    [0:1]            counter_id0_w   ;
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wire    [0:1]            counter_id1_w   ;
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wire    [0:1]            counter_id2_w   ;
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wire    [0:1]            counter_id3_w   ;
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genvar gi, gj;
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initial
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begin
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        dec_state = 7;
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        tb_state  = 7;
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        counter_id0 = 0;
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        counter_id1 = 1;
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        counter_id2 = 2;
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        counter_id3 = 3;
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        counter_tb = 0;
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        counter_tbn = -1;
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end
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always @ (clk, rst)
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begin
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        if      (rst == 0)               counter_tb = 0;
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        else if(clk == 1)
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                if      (frame_rst == 1)        counter_tb = 0;
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                else if (en == 1)               counter_tb = (counter_tb + 1) % ram_depth;
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end
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assign counter_tb_w = counter_tb;
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assign counter_tbn_w = ~counter_tb;
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always @ (clk, rst)
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begin
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        if      (rst == 0)
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        begin
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                counter_id0 = 0;
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                counter_id1 = 1;
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                counter_id2 = 2;
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                counter_id3 = 3;
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        end
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        else if (clk == 1)
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                if      (frame_rst == 1)
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                begin
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                        counter_id0 = 0;
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                        counter_id1 = 1;
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                        counter_id2 = 2;
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                        counter_id3 = 3;
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                end
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                else if (counter_tb == ram_depth - 1)
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                begin
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                        counter_id0 = (counter_id0 + 1) % 4;
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                        counter_id1 = (counter_id1 + 1) % 4;
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                        counter_id2 = (counter_id2 + 1) % 4;
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                        counter_id3 = (counter_id3 + 1) % 4;
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                end
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end
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assign counter_id0_w = counter_id0;
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assign counter_id1_w = counter_id1;
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assign counter_id2_w = counter_id2;
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assign counter_id3_w = counter_id3;
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always @ (counter_id0_w)
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begin
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        case(counter_id0_w)
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                2'b00   :       en_reg = 4'b1000;
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                2'b01   :       en_reg = 4'b0100;
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                2'b10   :       en_reg = 4'b0010;
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                2'b11   :       en_reg = 4'b0001;
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        endcase
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end
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generate
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        if (radix == 1)
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        begin
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                always @ (in1, clk)
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                begin
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                        in_reg[0] = in1;
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                end
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        end
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        else if (radix == 2)
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        begin
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                always @ (in1, in2, clk)
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                begin
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                        in_reg[0] = in1;
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                        in_reg[1] = in2;
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                end
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        end
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        else if (radix == 3)
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        begin
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                always @ (in1, in2, in3, clk)
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                begin
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                        in_reg[0] = in1;
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                        in_reg[1] = in2;
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                        in_reg[2] = in3;
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                end
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        end
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        else if (radix == 4)
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        begin
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                always @ (in1, in2, in3, in4, clk)
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                begin
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                        in_reg[0] = in1;
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                        in_reg[1] = in2;
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                        in_reg[2] = in3;
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                        in_reg[3] = in4;
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                end
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        end
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endgenerate
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generate for (gi = 0; gi < radix; gi = gi + 1)
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begin : sel
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        assign tb_tmp[gi] = out_w[counter_id3_w][gi][tb_state];
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        assign dc_tmp[gi] = out_w[counter_id1_w][gi][dec_state];
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        assign dc_tmp_tmp[gi] = out_w[counter_id1_w][gi][tb_state];
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end
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endgenerate
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generate for (gi = 0; gi < 4; gi = gi + 1)
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begin : ram
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        for (gj = 0; gj < radix; gj = gj + 1)
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        begin : r
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                dpram           #(      data_width,
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                                                ram_depth,
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                                                addr_width)
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                ram_inst        (       in_reg[gj],
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                                                out_w[gi][gj],
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                                                counter_tbn_w,
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                                                counter_tb_w,
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                                                clk,
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                                                rst,
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                                                frame_rst,
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                                                en_reg[gi]);
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        end
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end
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endgenerate
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always @ (posedge clk)
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begin
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        if (counter_tb == ram_depth - 1)
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        begin
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                dec_state = {tb_state[radix:nu-1], dc_tmp_tmp};
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                tb_state = 7;
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        end
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        else
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        begin
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                dec_state = {dec_state[radix:nu-1], dc_tmp};
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                tb_state = {tb_state[radix:nu-1], tb_tmp};
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        end
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end
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generate for (gi = 0; gi < radix; gi = gi + 1)
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begin : assgn_out
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        assign out_tb[gi] = tb_state[gi];
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        assign out_dc[gi] = dec_state[gi];
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end
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endgenerate
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endmodule

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