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#!/usr/bin/perl -w
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# $Id: tmuconv 334 2010-10-23 08:24:24Z mueller $
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#
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# Copyright 2008-2010 by Walter F.J. Mueller
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#
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# This program is free software; you may redistribute and/or modify it under
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# the terms of the GNU General Public License as published by the Free
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# Software Foundation, either version 2, or at your option any later version.
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#
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# This program is distributed in the hope that it will be useful, but
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# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# for complete details.
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#
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# Revision History:
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# Date Rev Version Comment
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# 2010-10-22 334 1.0.9 adapt to ibus V2 signals: req,we,dip->aval,re,we,rmw
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# 2010-06-26 309 1.0.8 add ibimres.cacc/racc handling
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# 2010-04-26 284 1.0.7 add error check for GetOptions
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# 2009-09-19 240 1.0.6 add more VFETCH addr defs; add 2nd DL11 defs
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# 2009-06-04 223 1.0.5 add IIST and PC11 defs
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# 2009-05-03 212 1.0.4 add defs for mmu par/pdr's and some unibus dev's
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# 2008-12-14 177 1.0.3 add -t_ru; use dp_ireg_we_last; add ibus names
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# 2008-11-30 174 1.0.2 SPUSH and VFETCH tags for em cycles; psw in id lines
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# 2008-04-25 138 1.0.1 show ccc/scc for code 000257/000277 in disassembler
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# 2008-04-19 137 1.0 Initial version
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#
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# Current fields in tmu_ofile:
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# clkcycle:d
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# cpu:o
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# dp.pc:o
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# dp.psw:o
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# dp.ireg:o
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# dp.ireg_we:b
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# dp.ireg_we_last:b
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# dp.dsrc:o
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# dp.ddst:o
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# dp.dtmp:o
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# dp.dres:o
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# dp.gpr_adst:o
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# dp.gpr_mode:o
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# dp.gpr_bytop:b
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# dp.gpr_we:b
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# vm.ibmreq.aval:b
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# vm.ibmreq.re:b
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# vm.ibmreq.we:b
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# vm.ibmreq.rmw:b
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# vm.ibmreq.be0:b
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# vm.ibmreq.be1:b
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# vm.ibmreq.cacc:b
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# vm.ibmreq.racc:b
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# vm.ibmreq.addr:o
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# vm.ibmreq.din:o
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# vm.ibsres.ack:b
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# vm.ibsres.busy:b
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# vm.ibsres.dout:o
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# co.cpugo:b
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# co.cpuhalt:b
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# sy.emmreq.req:b
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# sy.emmreq.we:b
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# sy.emmreq.be:b
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# sy.emmreq.cancel:b
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# sy.emmreq.addr:o
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# sy.emmreq.din:o
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# sy.emsres.ack_r:b
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# sy.emsres.ack_w:b
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# sy.emsres.dout:o
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# sy.chit:b
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#
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use 5.005; # require Perl 5.005 or higher
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use strict; # require strict checking
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use FileHandle;
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use Getopt::Long;
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my %opts = ();
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GetOptions(\%opts, "help", "dump", "cdump",
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"t_id", "t_ru", "t_em", "t_ib")
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or die "bad options";
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sub print_help;
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sub do_file;
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sub code2mnemo;
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sub regmod;
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my @var_name;
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my @var_type;
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my @var_dec;
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my @var_oct;
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my %name;
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my @val_curr_text;
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my @val_curr;
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my @val_last;
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my @reg_05 = ("------","------","------","------","------","------", # set 0
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"------","------","------","------","------","------",); # set 1
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my @reg_sp = ("------","------","------","------"); # ksp,ssp,???,usp
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my $ind_dp_pc;
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my $ind_dp_psw;
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my $ind_dp_ireg;
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my $ind_dp_ireg_we;
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my $ind_dp_ireg_we_last;
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my $ind_dp_dres;
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my $ind_dp_gpr_adst;
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my $ind_dp_gpr_mode;
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my $ind_dp_gpr_bytop;
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my $ind_dp_gpr_we;
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my $ind_vm_ibmreq_aval;
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my $ind_vm_ibmreq_re;
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my $ind_vm_ibmreq_we;
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my $ind_vm_ibmreq_rmw;
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my $ind_vm_ibmreq_be0;
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my $ind_vm_ibmreq_be1;
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my $ind_vm_ibmreq_cacc;
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my $ind_vm_ibmreq_racc;
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my $ind_vm_ibmreq_addr;
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my $ind_vm_ibmreq_din;
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my $ind_vm_ibsres_ack;
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my $ind_vm_ibsres_busy;
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my $ind_vm_ibsres_dout;
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my $ind_sy_emmreq_req;
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my $ind_sy_emmreq_we;
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my $ind_sy_emmreq_be;
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my $ind_sy_emmreq_cancel;
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my $ind_sy_emmreq_addr;
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my $ind_sy_emmreq_din;
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my $ind_sy_emsres_ack_r;
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my $ind_sy_emsres_ack_w;
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my $ind_sy_emsres_dout;
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| 136 |
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my $ind_sy_chit;
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my @pdp11_opcode_tbl = (
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{code=>0000000, mask=>0000000, name=>"halt", type=>"0arg"},
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{code=>0000001, mask=>0000000, name=>"wait", type=>"0arg"},
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| 141 |
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{code=>0000002, mask=>0000000, name=>"rti ", type=>"0arg"},
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| 142 |
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{code=>0000003, mask=>0000000, name=>"bpt ", type=>"0arg"},
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| 143 |
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{code=>0000004, mask=>0000000, name=>"iot ", type=>"0arg"},
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| 144 |
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{code=>0000005, mask=>0000000, name=>"reset",type=>"0arg"},
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| 145 |
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{code=>0000006, mask=>0000000, name=>"rtt ", type=>"0arg"},
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| 146 |
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{code=>0000007, mask=>0000000, name=>"!!mfpt", type=>"0arg"},
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| 147 |
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{code=>0000100, mask=>0000077, name=>"jmp ", type=>"1arg"},
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| 148 |
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{code=>0000200, mask=>0000007, name=>"rts ", type=>"1reg"},
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| 149 |
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{code=>0000230, mask=>0000007, name=>"spl ", type=>"spl"},
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| 150 |
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{code=>0000240, mask=>0000017, name=>"cl", type=>"ccop"},
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| 151 |
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{code=>0000260, mask=>0000017, name=>"se", type=>"ccop"},
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| 152 |
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{code=>0000300, mask=>0000077, name=>"swap", type=>"1arg"},
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| 153 |
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{code=>0000400, mask=>0000377, name=>"br ", type=>"br"},
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| 154 |
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{code=>0001000, mask=>0000377, name=>"bne ", type=>"br"},
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| 155 |
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{code=>0001400, mask=>0000377, name=>"beq ", type=>"br"},
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| 156 |
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{code=>0002000, mask=>0000377, name=>"bge ", type=>"br"},
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| 157 |
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{code=>0002400, mask=>0000377, name=>"blt ", type=>"br"},
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| 158 |
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{code=>0003000, mask=>0000377, name=>"bgt ", type=>"br"},
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| 159 |
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{code=>0003400, mask=>0000377, name=>"ble ", type=>"br"},
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| 160 |
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{code=>0004000, mask=>0000777, name=>"jsr ", type=>"jsr"},
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| 161 |
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{code=>0005000, mask=>0000077, name=>"clr ", type=>"1arg"},
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| 162 |
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{code=>0005100, mask=>0000077, name=>"com ", type=>"1arg"},
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| 163 |
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{code=>0005200, mask=>0000077, name=>"inc ", type=>"1arg"},
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| 164 |
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{code=>0005300, mask=>0000077, name=>"dec ", type=>"1arg"},
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| 165 |
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{code=>0005400, mask=>0000077, name=>"neg ", type=>"1arg"},
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| 166 |
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{code=>0005500, mask=>0000077, name=>"adc ", type=>"1arg"},
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| 167 |
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{code=>0005600, mask=>0000077, name=>"sbc ", type=>"1arg"},
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| 168 |
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{code=>0005700, mask=>0000077, name=>"tst ", type=>"1arg"},
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| 169 |
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{code=>0006000, mask=>0000077, name=>"ror ", type=>"1arg"},
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| 170 |
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{code=>0006100, mask=>0000077, name=>"rol ", type=>"1arg"},
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| 171 |
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{code=>0006200, mask=>0000077, name=>"asr ", type=>"1arg"},
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| 172 |
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{code=>0006300, mask=>0000077, name=>"asl ", type=>"1arg"},
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| 173 |
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{code=>0006400, mask=>0000077, name=>"mark", type=>"mark"},
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| 174 |
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{code=>0006500, mask=>0000077, name=>"mfpi", type=>"1arg"},
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| 175 |
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{code=>0006600, mask=>0000077, name=>"mtpi", type=>"1arg"},
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| 176 |
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{code=>0006700, mask=>0000077, name=>"sxt ", type=>"1arg"},
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| 177 |
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{code=>0007000, mask=>0000077, name=>"!!csm", type=>"1arg"},
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| 178 |
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{code=>0007200, mask=>0000077, name=>"!!tstset",type=>"1arg"},
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| 179 |
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{code=>0007300, mask=>0000077, name=>"!!wrtlck",type=>"1arg"},
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| 180 |
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{code=>0010000, mask=>0007777, name=>"mov ", type=>"2arg"},
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| 181 |
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{code=>0020000, mask=>0007777, name=>"cmp ", type=>"2arg"},
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| 182 |
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{code=>0030000, mask=>0007777, name=>"bit ", type=>"2arg"},
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| 183 |
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{code=>0040000, mask=>0007777, name=>"bic ", type=>"2arg"},
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| 184 |
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{code=>0050000, mask=>0007777, name=>"bis ", type=>"2arg"},
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| 185 |
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{code=>0060000, mask=>0007777, name=>"add ", type=>"2arg"},
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| 186 |
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{code=>0070000, mask=>0000777, name=>"mul ", type=>"rdst"},
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| 187 |
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{code=>0071000, mask=>0000777, name=>"div ", type=>"rdst"},
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| 188 |
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{code=>0072000, mask=>0000777, name=>"ash ", type=>"rdst"},
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| 189 |
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{code=>0073000, mask=>0000777, name=>"ashc", type=>"rdst"},
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| 190 |
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{code=>0074000, mask=>0000777, name=>"xor ", type=>"rdst"},
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| 191 |
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{code=>0077000, mask=>0000777, name=>"sob ", type=>"sob"},
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| 192 |
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{code=>0100000, mask=>0000377, name=>"bpl ", type=>"br"},
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| 193 |
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{code=>0100400, mask=>0000377, name=>"bmi ", type=>"br"},
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| 194 |
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{code=>0101000, mask=>0000377, name=>"bhi ", type=>"br"},
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| 195 |
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{code=>0101400, mask=>0000377, name=>"blos", type=>"br"},
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| 196 |
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{code=>0102000, mask=>0000377, name=>"bvc ", type=>"br"},
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| 197 |
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{code=>0102400, mask=>0000377, name=>"bvs ", type=>"br"},
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| 198 |
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{code=>0103000, mask=>0000377, name=>"bcc ", type=>"br"},
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| 199 |
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{code=>0103400, mask=>0000377, name=>"bcs ", type=>"br"},
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| 200 |
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{code=>0104000, mask=>0000377, name=>"emt ", type=>"trap"},
|
| 201 |
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{code=>0104400, mask=>0000377, name=>"trap", type=>"trap"},
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| 202 |
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{code=>0105000, mask=>0000077, name=>"clrb", type=>"1arg"},
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| 203 |
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{code=>0105100, mask=>0000077, name=>"comb", type=>"1arg"},
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| 204 |
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{code=>0105200, mask=>0000077, name=>"incb", type=>"1arg"},
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| 205 |
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{code=>0105300, mask=>0000077, name=>"decb", type=>"1arg"},
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| 206 |
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{code=>0105400, mask=>0000077, name=>"negb", type=>"1arg"},
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| 207 |
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{code=>0105500, mask=>0000077, name=>"adcb", type=>"1arg"},
|
| 208 |
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{code=>0105600, mask=>0000077, name=>"sbcb", type=>"1arg"},
|
| 209 |
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{code=>0105700, mask=>0000077, name=>"tstb", type=>"1arg"},
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| 210 |
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{code=>0106000, mask=>0000077, name=>"rorb", type=>"1arg"},
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| 211 |
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{code=>0106100, mask=>0000077, name=>"rolb", type=>"1arg"},
|
| 212 |
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{code=>0106200, mask=>0000077, name=>"asrb", type=>"1arg"},
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| 213 |
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{code=>0106300, mask=>0000077, name=>"aslb", type=>"1arg"},
|
| 214 |
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{code=>0106400, mask=>0000077, name=>"!!mtps", type=>"1arg"},
|
| 215 |
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{code=>0106500, mask=>0000077, name=>"mfpd", type=>"1arg"},
|
| 216 |
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{code=>0106600, mask=>0000077, name=>"mtpd", type=>"1arg"},
|
| 217 |
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{code=>0106700, mask=>0000077, name=>"!!mfps", type=>"1arg"},
|
| 218 |
|
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{code=>0110000, mask=>0007777, name=>"movb", type=>"2arg"},
|
| 219 |
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{code=>0120000, mask=>0007777, name=>"cmpb", type=>"2arg"},
|
| 220 |
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{code=>0130000, mask=>0007777, name=>"bitb", type=>"2arg"},
|
| 221 |
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{code=>0140000, mask=>0007777, name=>"bicb", type=>"2arg"},
|
| 222 |
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{code=>0150000, mask=>0007777, name=>"bisb", type=>"2arg"},
|
| 223 |
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{code=>0160000, mask=>0007777, name=>"sub ", type=>"2arg"},
|
| 224 |
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{code=>0170000, mask=>0000000, name=>"!!cfcc", type=>"0arg"},
|
| 225 |
|
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{code=>0170001, mask=>0000000, name=>"!!setf", type=>"0arg"},
|
| 226 |
|
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{code=>0170011, mask=>0000000, name=>"!!setd", type=>"0arg"},
|
| 227 |
|
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{code=>0170002, mask=>0000000, name=>"!!seti", type=>"0arg"},
|
| 228 |
|
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{code=>0170012, mask=>0000000, name=>"!!setl", type=>"0arg"},
|
| 229 |
|
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{code=>0170100, mask=>0000077, name=>"!!ldfps",type=>"1fpp"},
|
| 230 |
|
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{code=>0170200, mask=>0000077, name=>"!!stfps",type=>"1fpp"},
|
| 231 |
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{code=>0170300, mask=>0000077, name=>"!!stst", type=>"1fpp"},
|
| 232 |
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{code=>0170400, mask=>0000077, name=>"!!clrf", type=>"1fpp"},
|
| 233 |
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{code=>0170500, mask=>0000077, name=>"!!tstf", type=>"1fpp"},
|
| 234 |
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{code=>0170600, mask=>0000077, name=>"!!absf", type=>"1fpp"},
|
| 235 |
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{code=>0170700, mask=>0000077, name=>"!!negf", type=>"1fpp"},
|
| 236 |
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{code=>0171000, mask=>0000377, name=>"!!mulf", type=>"rfpp"},
|
| 237 |
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{code=>0171400, mask=>0000377, name=>"!!modf", type=>"rfpp"},
|
| 238 |
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{code=>0172000, mask=>0000377, name=>"!!addf", type=>"rfpp"},
|
| 239 |
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{code=>0172400, mask=>0000377, name=>"!!ldf", type=>"rfpp"},
|
| 240 |
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{code=>0173000, mask=>0000377, name=>"!!subf", type=>"rfpp"},
|
| 241 |
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{code=>0173400, mask=>0000377, name=>"!!cmpf", type=>"rfpp"},
|
| 242 |
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{code=>0174000, mask=>0000377, name=>"!!stf", type=>"rfpp"},
|
| 243 |
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{code=>0174400, mask=>0000377, name=>"!!divf", type=>"rfpp"},
|
| 244 |
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{code=>0175000, mask=>0000377, name=>"!!stexp",type=>"rfpp"},
|
| 245 |
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{code=>0175400, mask=>0000377, name=>"!!stcif",type=>"rfpp"},
|
| 246 |
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{code=>0176000, mask=>0000377, name=>"!!stcfd",type=>"rfpp"},
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| 247 |
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{code=>0176400, mask=>0000377, name=>"!!ldexp",type=>"rfpp"},
|
| 248 |
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{code=>0177000, mask=>0000377, name=>"!!ldcif",type=>"rfpp"},
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| 249 |
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{code=>0177400, mask=>0000377, name=>"!!ldcdf",type=>"rfpp"}
|
| 250 |
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);
|
| 251 |
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| 252 |
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my %pdp11_regs = ( # use simh naming convention
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| 253 |
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177776=> "psw",
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| 254 |
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177774=> "stklim",
|
| 255 |
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177772=> "pirq",
|
| 256 |
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177770=> "mbrk",
|
| 257 |
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177766=> "cpuerr",
|
| 258 |
|
|
177764=> "sysid",
|
| 259 |
|
|
177600=> "uipdr0",
|
| 260 |
|
|
177602=> "uipdr1",
|
| 261 |
|
|
177604=> "uipdr2",
|
| 262 |
|
|
177606=> "uipdr3",
|
| 263 |
|
|
177610=> "uipdr4",
|
| 264 |
|
|
177612=> "uipdr5",
|
| 265 |
|
|
177614=> "uipdr6",
|
| 266 |
|
|
177616=> "uipdr7",
|
| 267 |
|
|
177620=> "udpdr0",
|
| 268 |
|
|
177622=> "udpdr1",
|
| 269 |
|
|
177624=> "udpdr2",
|
| 270 |
|
|
177626=> "udpdr3",
|
| 271 |
|
|
177630=> "udpdr4",
|
| 272 |
|
|
177632=> "udpdr5",
|
| 273 |
|
|
177634=> "udpdr6",
|
| 274 |
|
|
177636=> "udpdr7",
|
| 275 |
|
|
177640=> "uipar0",
|
| 276 |
|
|
177642=> "uipar1",
|
| 277 |
|
|
177644=> "uipar2",
|
| 278 |
|
|
177646=> "uipar3",
|
| 279 |
|
|
177650=> "uipar4",
|
| 280 |
|
|
177652=> "uipar5",
|
| 281 |
|
|
177654=> "uipar6",
|
| 282 |
|
|
177656=> "uipar7",
|
| 283 |
|
|
177660=> "udpar0",
|
| 284 |
|
|
177662=> "udpar1",
|
| 285 |
|
|
177664=> "udpar2",
|
| 286 |
|
|
177666=> "udpar3",
|
| 287 |
|
|
177670=> "udpar4",
|
| 288 |
|
|
177672=> "udpar5",
|
| 289 |
|
|
177674=> "udpar6",
|
| 290 |
|
|
177676=> "udpar7",
|
| 291 |
|
|
177576=> "mmr2",
|
| 292 |
|
|
177574=> "mmr1",
|
| 293 |
|
|
177572=> "mmr0",
|
| 294 |
|
|
177570=> "sdreg", # not a simh name !!
|
| 295 |
|
|
177560=> "ti.csr",
|
| 296 |
|
|
177562=> "ti.buf",
|
| 297 |
|
|
177564=> "to.csr",
|
| 298 |
|
|
177566=> "to.buf",
|
| 299 |
|
|
177550=> "pr.csr",
|
| 300 |
|
|
177552=> "pr.buf",
|
| 301 |
|
|
177554=> "pp.csr",
|
| 302 |
|
|
177556=> "pp.buf",
|
| 303 |
|
|
177546=> "kl.csr",
|
| 304 |
|
|
177514=> "lp.csr",
|
| 305 |
|
|
177516=> "lp.buf",
|
| 306 |
|
|
177500=> "ii.acr",
|
| 307 |
|
|
177502=> "ii.adr",
|
| 308 |
|
|
177400=> "rk.ds ",
|
| 309 |
|
|
177402=> "rk.er ",
|
| 310 |
|
|
177404=> "rk.cs ",
|
| 311 |
|
|
177406=> "rk.wc ",
|
| 312 |
|
|
177410=> "rk.ba ",
|
| 313 |
|
|
177412=> "rk.da ",
|
| 314 |
|
|
177414=> "rk.mr ",
|
| 315 |
|
|
177416=> "rk.db ",
|
| 316 |
|
|
177060=> "xor.cs", # XOR Tester
|
| 317 |
|
|
176500=> "ti2.cs",
|
| 318 |
|
|
176502=> "ti2.bu",
|
| 319 |
|
|
176504=> "to2.cs",
|
| 320 |
|
|
176506=> "to2.bu",
|
| 321 |
|
|
174400=> "rl.cs ",
|
| 322 |
|
|
174402=> "rl.ba ",
|
| 323 |
|
|
174404=> "rl.da ",
|
| 324 |
|
|
174406=> "rl.mp ",
|
| 325 |
|
|
172540=> "kp.csr",
|
| 326 |
|
|
172542=> "kp.buf",
|
| 327 |
|
|
172544=> "kp.cnt",
|
| 328 |
|
|
172520=> "tm.mts",
|
| 329 |
|
|
172522=> "tm.mtc",
|
| 330 |
|
|
172524=> "tm.brc",
|
| 331 |
|
|
172526=> "tm.cma",
|
| 332 |
|
|
172530=> "tm.mtd",
|
| 333 |
|
|
172532=> "tm.rda",
|
| 334 |
|
|
172516=> "mmr3",
|
| 335 |
|
|
172200=> "sipdr0",
|
| 336 |
|
|
172202=> "sipdr1",
|
| 337 |
|
|
172204=> "sipdr2",
|
| 338 |
|
|
172206=> "sipdr3",
|
| 339 |
|
|
172210=> "sipdr4",
|
| 340 |
|
|
172212=> "sipdr5",
|
| 341 |
|
|
172214=> "sipdr6",
|
| 342 |
|
|
172216=> "sipdr7",
|
| 343 |
|
|
172220=> "sdpdr0",
|
| 344 |
|
|
172222=> "sdpdr1",
|
| 345 |
|
|
172224=> "sdpdr2",
|
| 346 |
|
|
172226=> "sdpdr3",
|
| 347 |
|
|
172230=> "sdpdr4",
|
| 348 |
|
|
172232=> "sdpdr5",
|
| 349 |
|
|
172234=> "sdpdr6",
|
| 350 |
|
|
172236=> "sdpdr7",
|
| 351 |
|
|
172240=> "sipar0",
|
| 352 |
|
|
172242=> "sipar1",
|
| 353 |
|
|
172244=> "sipar2",
|
| 354 |
|
|
172246=> "sipar3",
|
| 355 |
|
|
172250=> "sipar4",
|
| 356 |
|
|
172252=> "sipar5",
|
| 357 |
|
|
172254=> "sipar6",
|
| 358 |
|
|
172256=> "sipar7",
|
| 359 |
|
|
172260=> "sdpar0",
|
| 360 |
|
|
172262=> "sdpar1",
|
| 361 |
|
|
172264=> "sdpar2",
|
| 362 |
|
|
172266=> "sdpar3",
|
| 363 |
|
|
172270=> "sdpar4",
|
| 364 |
|
|
172272=> "sdpar5",
|
| 365 |
|
|
172274=> "sdpar6",
|
| 366 |
|
|
172276=> "sdpar7",
|
| 367 |
|
|
172300=> "kipdr0",
|
| 368 |
|
|
172302=> "kipdr1",
|
| 369 |
|
|
172304=> "kipdr2",
|
| 370 |
|
|
172306=> "kipdr3",
|
| 371 |
|
|
172310=> "kipdr4",
|
| 372 |
|
|
172312=> "kipdr5",
|
| 373 |
|
|
172314=> "kipdr6",
|
| 374 |
|
|
172316=> "kipdr7",
|
| 375 |
|
|
172320=> "kdpdr0",
|
| 376 |
|
|
172322=> "kdpdr1",
|
| 377 |
|
|
172324=> "kdpdr2",
|
| 378 |
|
|
172326=> "kdpdr3",
|
| 379 |
|
|
172330=> "kdpdr4",
|
| 380 |
|
|
172332=> "kdpdr5",
|
| 381 |
|
|
172334=> "kdpdr6",
|
| 382 |
|
|
172336=> "kdpdr7",
|
| 383 |
|
|
172340=> "kipar0",
|
| 384 |
|
|
172342=> "kipar1",
|
| 385 |
|
|
172344=> "kipar2",
|
| 386 |
|
|
172346=> "kipar3",
|
| 387 |
|
|
172350=> "kipar4",
|
| 388 |
|
|
172352=> "kipar5",
|
| 389 |
|
|
172354=> "kipar6",
|
| 390 |
|
|
172356=> "kipar7",
|
| 391 |
|
|
172360=> "kdpar0",
|
| 392 |
|
|
172362=> "kdpar1",
|
| 393 |
|
|
172364=> "kdpar2",
|
| 394 |
|
|
172366=> "kdpar3",
|
| 395 |
|
|
172370=> "kdpar4",
|
| 396 |
|
|
172372=> "kdpar5",
|
| 397 |
|
|
172374=> "kdpar6",
|
| 398 |
|
|
172376=> "kdpar7",
|
| 399 |
|
|
160100=> "dz.csr",
|
| 400 |
|
|
160102=> "dz.mp2",
|
| 401 |
|
|
160104=> "dz.tcr",
|
| 402 |
|
|
160106=> "dz.mp6"
|
| 403 |
|
|
);
|
| 404 |
|
|
|
| 405 |
|
|
autoflush STDOUT 1 if (-p STDOUT); # autoflush if output into pipe
|
| 406 |
|
|
|
| 407 |
|
|
if (exists $opts{help}) {
|
| 408 |
|
|
print_help;
|
| 409 |
|
|
exit 0;
|
| 410 |
|
|
}
|
| 411 |
|
|
|
| 412 |
|
|
foreach my $file (@ARGV) {
|
| 413 |
|
|
do_file($file);
|
| 414 |
|
|
}
|
| 415 |
|
|
|
| 416 |
|
|
|
| 417 |
|
|
#-------------------------------------------------------------------------------
|
| 418 |
|
|
|
| 419 |
|
|
sub do_file {
|
| 420 |
|
|
my ($file) = @_;
|
| 421 |
|
|
|
| 422 |
|
|
open IFILE,"<$file" or die "failed to open $file";
|
| 423 |
|
|
|
| 424 |
|
|
my $idec_cyc = 0;
|
| 425 |
|
|
my $change_cyc = 0;
|
| 426 |
|
|
my $emreq_cyc = 0;
|
| 427 |
|
|
my $emreq_str = "";
|
| 428 |
|
|
my $ibreq_cyc = 0;
|
| 429 |
|
|
my $ibreq_typ = "";
|
| 430 |
|
|
my $ibreq_str = "";
|
| 431 |
|
|
my $ibreq_nam = "";
|
| 432 |
|
|
|
| 433 |
|
|
my $emcurr_we = 0; # curr em write enable (or undef)
|
| 434 |
|
|
my $emcurr_addr = undef; # curr em address
|
| 435 |
|
|
my $emlast_we = 0; # prev em write enable (or undef)
|
| 436 |
|
|
my $emlast_addr = undef; # prev em address
|
| 437 |
|
|
|
| 438 |
|
|
while () {
|
| 439 |
|
|
chomp;
|
| 440 |
|
|
if (/^#\s+/) {
|
| 441 |
|
|
@var_name = ();
|
| 442 |
|
|
@var_type = ();
|
| 443 |
|
|
my $dsc_str = $';
|
| 444 |
|
|
my @dsc_list = split /\s+/,$dsc_str;
|
| 445 |
|
|
foreach my $dsc (@dsc_list) {
|
| 446 |
|
|
if ($dsc =~ /^(.*):([bdo])$/) {
|
| 447 |
|
|
my $ind = scalar(@var_name);
|
| 448 |
|
|
$name{$1} = {ind=>$ind,
|
| 449 |
|
|
typ=>$2};
|
| 450 |
|
|
push @var_name, $1;
|
| 451 |
|
|
push @var_type, $2;
|
| 452 |
|
|
push @var_dec, $ind if $2 eq "d";
|
| 453 |
|
|
push @var_oct, $ind if $2 eq "o";
|
| 454 |
|
|
} else {
|
| 455 |
|
|
print "tmuconv-E: bad descriptor $dsc\n";
|
| 456 |
|
|
}
|
| 457 |
|
|
}
|
| 458 |
|
|
|
| 459 |
|
|
$ind_dp_pc = $name{'dp.pc'}->{ind};
|
| 460 |
|
|
$ind_dp_psw = $name{'dp.psw'}->{ind};
|
| 461 |
|
|
$ind_dp_ireg = $name{'dp.ireg'}->{ind};
|
| 462 |
|
|
$ind_dp_ireg_we = $name{'dp.ireg_we'}->{ind};
|
| 463 |
|
|
$ind_dp_ireg_we_last = $name{'dp.ireg_we_last'}->{ind};
|
| 464 |
|
|
$ind_dp_dres = $name{'dp.dres'}->{ind};
|
| 465 |
|
|
$ind_dp_gpr_adst = $name{'dp.gpr_adst'}->{ind};
|
| 466 |
|
|
$ind_dp_gpr_mode = $name{'dp.gpr_mode'}->{ind};
|
| 467 |
|
|
$ind_dp_gpr_bytop = $name{'dp.gpr_bytop'}->{ind};
|
| 468 |
|
|
$ind_dp_gpr_we = $name{'dp.gpr_we'}->{ind};
|
| 469 |
|
|
|
| 470 |
8 |
wfjm |
$ind_vm_ibmreq_aval = $name{'vm.ibmreq.aval'}->{ind};
|
| 471 |
|
|
$ind_vm_ibmreq_re = $name{'vm.ibmreq.re'}->{ind};
|
| 472 |
2 |
wfjm |
$ind_vm_ibmreq_we = $name{'vm.ibmreq.we'}->{ind};
|
| 473 |
8 |
wfjm |
$ind_vm_ibmreq_rmw = $name{'vm.ibmreq.rmw'}->{ind};
|
| 474 |
2 |
wfjm |
$ind_vm_ibmreq_be0 = $name{'vm.ibmreq.be0'}->{ind};
|
| 475 |
|
|
$ind_vm_ibmreq_be1 = $name{'vm.ibmreq.be1'}->{ind};
|
| 476 |
|
|
$ind_vm_ibmreq_cacc = $name{'vm.ibmreq.cacc'}->{ind};
|
| 477 |
|
|
$ind_vm_ibmreq_racc = $name{'vm.ibmreq.racc'}->{ind};
|
| 478 |
|
|
$ind_vm_ibmreq_addr = $name{'vm.ibmreq.addr'}->{ind};
|
| 479 |
|
|
$ind_vm_ibmreq_din = $name{'vm.ibmreq.din'}->{ind};
|
| 480 |
|
|
$ind_vm_ibsres_ack = $name{'vm.ibsres.ack'}->{ind};
|
| 481 |
|
|
$ind_vm_ibsres_busy = $name{'vm.ibsres.busy'}->{ind};
|
| 482 |
|
|
$ind_vm_ibsres_dout = $name{'vm.ibsres.dout'}->{ind};
|
| 483 |
|
|
|
| 484 |
|
|
$ind_sy_emmreq_req = $name{'sy.emmreq.req'}->{ind};
|
| 485 |
|
|
$ind_sy_emmreq_we = $name{'sy.emmreq.we'}->{ind};
|
| 486 |
|
|
$ind_sy_emmreq_be = $name{'sy.emmreq.be'}->{ind};
|
| 487 |
|
|
$ind_sy_emmreq_cancel = $name{'sy.emmreq.cancel'}->{ind};
|
| 488 |
|
|
$ind_sy_emmreq_addr = $name{'sy.emmreq.addr'}->{ind};
|
| 489 |
|
|
$ind_sy_emmreq_din = $name{'sy.emmreq.din'}->{ind};
|
| 490 |
|
|
$ind_sy_emsres_ack_r = $name{'sy.emsres.ack_r'}->{ind};
|
| 491 |
|
|
$ind_sy_emsres_ack_w = $name{'sy.emsres.ack_w'}->{ind};
|
| 492 |
|
|
$ind_sy_emsres_dout = $name{'sy.emsres.dout'}->{ind};
|
| 493 |
|
|
$ind_sy_chit = $name{'sy.chit'}->{ind};
|
| 494 |
|
|
|
| 495 |
|
|
} else {
|
| 496 |
|
|
@val_last = @val_curr;
|
| 497 |
|
|
my $notfirst = scalar(@val_last) > 0;
|
| 498 |
|
|
|
| 499 |
|
|
$_ =~ s/^\s*//;
|
| 500 |
|
|
$_ =~ s/\s*$//;
|
| 501 |
|
|
@val_curr = split /\s+/,$_;
|
| 502 |
|
|
if (scalar(@val_curr) != scalar(@var_name)) {
|
| 503 |
|
|
printf "tmuconv-E: value list length mismatch, seen %d, expected %d\n",
|
| 504 |
|
|
scalar(@val_curr), scalar(@var_name);
|
| 505 |
|
|
for (my $i=0; $i
|
| 506 |
|
|
printf "%3d: %s\n", $i,$val_curr[$i];
|
| 507 |
|
|
}
|
| 508 |
|
|
next;
|
| 509 |
|
|
}
|
| 510 |
|
|
|
| 511 |
|
|
@val_curr_text = @val_curr if exists $opts{dump} || exists $opts{cdump};
|
| 512 |
|
|
|
| 513 |
|
|
my $cyc_curr = int $val_curr[0];
|
| 514 |
|
|
my $cyc_str = sprintf "%8d", $cyc_curr;
|
| 515 |
|
|
|
| 516 |
|
|
foreach my $ind (@var_dec) {
|
| 517 |
|
|
$val_curr[$ind] = int ($val_curr[$ind]);
|
| 518 |
|
|
}
|
| 519 |
|
|
foreach my $ind (@var_oct) {
|
| 520 |
|
|
$val_curr[$ind] = oct ($val_curr[$ind]);
|
| 521 |
|
|
}
|
| 522 |
|
|
|
| 523 |
|
|
my $id_str = "";
|
| 524 |
|
|
my $ru_str = "";
|
| 525 |
|
|
my $emres_str = "";
|
| 526 |
|
|
my $emtyp_str = "";
|
| 527 |
|
|
my $ibres_str = "";
|
| 528 |
|
|
my $ibreq_we = 0;
|
| 529 |
|
|
my $ibreq_act = 0;
|
| 530 |
|
|
|
| 531 |
|
|
if (exists $opts{dump} || exists $opts{cdump}) {
|
| 532 |
|
|
my @val_change;
|
| 533 |
|
|
my $any_change;
|
| 534 |
|
|
|
| 535 |
|
|
for (my $i=1; $i
|
| 536 |
|
|
my $change = (not $notfirst) || ($val_curr[$i] != $val_last[$i]);
|
| 537 |
|
|
$val_change[$i] = $change;
|
| 538 |
|
|
$any_change |= $change;
|
| 539 |
|
|
}
|
| 540 |
|
|
|
| 541 |
|
|
if (exists $opts{dump} || $any_change) {
|
| 542 |
|
|
printf "cycle $cyc_str %s", "-" x 32;
|
| 543 |
|
|
if ($notfirst && exists $opts{cdump}) {
|
| 544 |
|
|
printf " (%d)",$cyc_curr-$change_cyc;
|
| 545 |
|
|
}
|
| 546 |
|
|
print "\n";
|
| 547 |
|
|
|
| 548 |
|
|
for (my $i=1; $i
|
| 549 |
|
|
my $oper = $val_change[$i] ? "<=" : " =";
|
| 550 |
|
|
if (exists $opts{dump} || $val_change[$i]) {
|
| 551 |
|
|
printf " %-16s:%s %s %s\n", $var_name[$i], $var_type[$i],
|
| 552 |
|
|
$oper, $val_curr_text[$i];
|
| 553 |
|
|
}
|
| 554 |
|
|
}
|
| 555 |
|
|
$change_cyc = $cyc_curr;
|
| 556 |
|
|
}
|
| 557 |
|
|
}
|
| 558 |
|
|
#
|
| 559 |
|
|
# handle t_id
|
| 560 |
|
|
# uses cycles with dp_ireg_we = '1'
|
| 561 |
|
|
#
|
| 562 |
|
|
if (exists $opts{t_id} and $notfirst) {
|
| 563 |
|
|
if ($val_curr[$ind_dp_ireg_we_last]) {
|
| 564 |
|
|
my $pc = $val_curr[$ind_dp_pc] - 2;
|
| 565 |
|
|
my $psw = $val_curr[$ind_dp_psw];
|
| 566 |
|
|
my $ireg = $val_curr[$ind_dp_ireg];
|
| 567 |
|
|
my $code = code2mnemo($ireg);
|
| 568 |
|
|
$id_str = sprintf " %6.6o %6.6o %6.6o %s",
|
| 569 |
|
|
$pc, $psw, $ireg, $code;
|
| 570 |
|
|
$id_str .= " " x (20-length($code));
|
| 571 |
|
|
$id_str .= sprintf " (%d)",$cyc_curr-$idec_cyc;
|
| 572 |
|
|
$idec_cyc = $cyc_curr;
|
| 573 |
|
|
}
|
| 574 |
|
|
}
|
| 575 |
|
|
#
|
| 576 |
|
|
|
| 577 |
|
|
# 1706 ru 0 06 000002 000002 000002 000002 000002 000002 000002 ksp
|
| 578 |
|
|
# 1694 id 002012 000340 010036 mov r0,@(sp)+ (8)
|
| 579 |
|
|
|
| 580 |
|
|
|
| 581 |
|
|
# handle t_ru
|
| 582 |
|
|
# uses cycles with dp_gpr_we = '1'
|
| 583 |
|
|
#
|
| 584 |
|
|
if (exists $opts{t_ru}) {
|
| 585 |
|
|
if ($val_curr[$ind_dp_gpr_we]) {
|
| 586 |
|
|
my $adst = $val_curr[$ind_dp_gpr_adst];
|
| 587 |
|
|
my $mode = $val_curr[$ind_dp_gpr_mode];
|
| 588 |
|
|
my $bytop = $val_curr[$ind_dp_gpr_bytop];
|
| 589 |
|
|
my $psw = $val_curr[$ind_dp_psw];
|
| 590 |
|
|
my $dres = $val_curr[$ind_dp_dres];
|
| 591 |
|
|
my $rset = $psw>>11 & 01;
|
| 592 |
|
|
$ru_str = sprintf "%o %o%o %6.6o", $bytop, $rset, $adst, $dres;
|
| 593 |
|
|
$ru_str .= " ";
|
| 594 |
|
|
if ($adst eq "7") {
|
| 595 |
|
|
$ru_str .= "pc";
|
| 596 |
|
|
} elsif ($adst eq "6") {
|
| 597 |
|
|
$reg_sp[$mode] = sprintf "%6.6o",$dres;
|
| 598 |
|
|
$ru_str .= $reg_sp[0];
|
| 599 |
|
|
$ru_str .= ($mode == 0) ? "*" : " ";
|
| 600 |
|
|
$ru_str .= $reg_sp[1];
|
| 601 |
|
|
$ru_str .= ($mode == 1) ? "*" : " ";
|
| 602 |
|
|
$ru_str .= $reg_sp[3];
|
| 603 |
|
|
$ru_str .= ($mode == 3) ? "*" : " ";
|
| 604 |
|
|
$ru_str .= " ksp" if $mode eq "0";
|
| 605 |
|
|
$ru_str .= " ssp" if $mode eq "1";
|
| 606 |
|
|
$ru_str .= " usp" if $mode eq "3";
|
| 607 |
|
|
} else {
|
| 608 |
|
|
my $rbase = ($rset==0) ? 0 : 6;
|
| 609 |
|
|
$reg_05[$rbase+$adst] = sprintf "%6.6o",$dres;
|
| 610 |
|
|
for (my $i=0; $i<6; $i++) {
|
| 611 |
|
|
$ru_str .= $reg_05[$rbase+$i];
|
| 612 |
|
|
$ru_str .= ($adst==$i) ? "*" : " ";
|
| 613 |
|
|
}
|
| 614 |
|
|
$ru_str .= sprintf " r%o%o", $rset, $adst;
|
| 615 |
|
|
}
|
| 616 |
|
|
}
|
| 617 |
|
|
}
|
| 618 |
|
|
#
|
| 619 |
|
|
# handle t_em
|
| 620 |
|
|
# uses cycles with sy_emmreq_req = '1'
|
| 621 |
|
|
# sy_emsres_ack_r = '1'
|
| 622 |
|
|
# sy_emsres_ack_w = '1'
|
| 623 |
|
|
# sy_emsreq_cancel = '1'
|
| 624 |
|
|
#
|
| 625 |
|
|
if (exists $opts{t_em}) {
|
| 626 |
|
|
if ($val_curr[$ind_sy_emmreq_req]) {
|
| 627 |
|
|
$emreq_cyc = $cyc_curr;
|
| 628 |
|
|
$emreq_str = sprintf "%s %s %8.8o",
|
| 629 |
|
|
($val_curr[$ind_sy_emmreq_we] ? "w" : "r"),
|
| 630 |
|
|
$val_curr[$ind_sy_emmreq_be],
|
| 631 |
|
|
$val_curr[$ind_sy_emmreq_addr];
|
| 632 |
|
|
$emcurr_we = $val_curr[$ind_sy_emmreq_we];
|
| 633 |
|
|
$emcurr_addr = $val_curr[$ind_sy_emmreq_addr];
|
| 634 |
|
|
if ($emcurr_we) {
|
| 635 |
|
|
$emreq_str .= sprintf " %6.6o", $val_curr[$ind_sy_emmreq_din];
|
| 636 |
|
|
} else {
|
| 637 |
|
|
$emreq_str .= " " x 7;
|
| 638 |
|
|
}
|
| 639 |
|
|
}
|
| 640 |
|
|
if ($val_curr[$ind_sy_emsres_ack_r] ||
|
| 641 |
|
|
$val_curr[$ind_sy_emsres_ack_w] ||
|
| 642 |
|
|
$val_curr[$ind_sy_emmreq_cancel]) {
|
| 643 |
|
|
$emres_str = sprintf "%s%s%s%s",
|
| 644 |
|
|
$val_curr[$ind_sy_emmreq_cancel],
|
| 645 |
|
|
$val_curr[$ind_sy_emsres_ack_r],
|
| 646 |
|
|
$val_curr[$ind_sy_emsres_ack_w],
|
| 647 |
|
|
$val_curr[$ind_sy_chit];
|
| 648 |
|
|
if ($val_curr[$ind_sy_emmreq_cancel]) {
|
| 649 |
|
|
$emreq_str .= " cancel";
|
| 650 |
|
|
$emcurr_we = undef;
|
| 651 |
|
|
} else {
|
| 652 |
|
|
if ($val_curr[$ind_sy_emsres_ack_r]) {
|
| 653 |
|
|
$emreq_str .= sprintf " %6.6o", $val_curr[$ind_sy_emsres_dout];
|
| 654 |
|
|
} else {
|
| 655 |
|
|
$emreq_str .= " " x 7;
|
| 656 |
|
|
}
|
| 657 |
|
|
if (defined $emlast_we && $emcurr_we == $emlast_we) {
|
| 658 |
|
|
if ($emcurr_we && $emcurr_addr == $emlast_addr-2) {
|
| 659 |
|
|
$emtyp_str = "SPUSH";
|
| 660 |
|
|
} elsif ((not $emcurr_we) && $emcurr_addr == $emlast_addr+2 &&
|
| 661 |
|
|
$emcurr_addr < 0400 && ($emcurr_addr % 04) == 02) {
|
| 662 |
|
|
$emtyp_str = "VFETCH";
|
| 663 |
|
|
$emtyp_str .= " 004 ill.inst" if ($emlast_addr == 0004);
|
| 664 |
|
|
$emtyp_str .= " 010 res.inst" if ($emlast_addr == 0010);
|
| 665 |
|
|
$emtyp_str .= " 014 BPT" if ($emlast_addr == 0014);
|
| 666 |
|
|
$emtyp_str .= " 020 IOT" if ($emlast_addr == 0020);
|
| 667 |
|
|
$emtyp_str .= " 030 EMT" if ($emlast_addr == 0030);
|
| 668 |
|
|
$emtyp_str .= " 034 TRAP" if ($emlast_addr == 0034);
|
| 669 |
|
|
$emtyp_str .= " 060 DL11-TTI" if ($emlast_addr == 0060);
|
| 670 |
|
|
$emtyp_str .= " 064 DL11-TTO" if ($emlast_addr == 0064);
|
| 671 |
|
|
$emtyp_str .= " 070 PC11-PTR" if ($emlast_addr == 0070);
|
| 672 |
|
|
$emtyp_str .= " 074 PC11-PTP" if ($emlast_addr == 0074);
|
| 673 |
|
|
$emtyp_str .= " 100 KW11-L" if ($emlast_addr == 0100);
|
| 674 |
|
|
$emtyp_str .= " 104 KW11-P" if ($emlast_addr == 0104);
|
| 675 |
|
|
$emtyp_str .= " 160 RL11" if ($emlast_addr == 0160);
|
| 676 |
|
|
$emtyp_str .= " 200 LP11" if ($emlast_addr == 0200);
|
| 677 |
|
|
$emtyp_str .= " 220 RK11" if ($emlast_addr == 0220);
|
| 678 |
|
|
$emtyp_str .= " 224 TM11" if ($emlast_addr == 0224);
|
| 679 |
|
|
$emtyp_str .= " 240 PIRQ" if ($emlast_addr == 0240);
|
| 680 |
|
|
$emtyp_str .= " 244 FPP exp" if ($emlast_addr == 0244);
|
| 681 |
|
|
$emtyp_str .= " 250 MMU trap" if ($emlast_addr == 0250);
|
| 682 |
|
|
$emtyp_str .= " 260 IIST" if ($emlast_addr == 0260);
|
| 683 |
|
|
$emtyp_str .= " 300 DL11-2-TTI" if ($emlast_addr == 0300);
|
| 684 |
|
|
$emtyp_str .= " 304 DL11-2-TTO" if ($emlast_addr == 0304);
|
| 685 |
|
|
}
|
| 686 |
|
|
}
|
| 687 |
|
|
}
|
| 688 |
|
|
$emlast_we = $emcurr_we;
|
| 689 |
|
|
$emlast_addr = $emcurr_addr;
|
| 690 |
|
|
}
|
| 691 |
|
|
}
|
| 692 |
|
|
#
|
| 693 |
|
|
# handle t_ib
|
| 694 |
8 |
wfjm |
# uses cycles with sy_ibmreq_re = '1' or sy_ibmreq_we = '1'
|
| 695 |
2 |
wfjm |
# sy_ibsres_ack = '1'
|
| 696 |
|
|
# vm_ibsres_busy '1' -> '0' transition
|
| 697 |
|
|
#
|
| 698 |
|
|
if (exists $opts{t_ib}) {
|
| 699 |
8 |
wfjm |
if ($val_curr[$ind_vm_ibmreq_re] || $val_curr[$ind_vm_ibmreq_we]) {
|
| 700 |
2 |
wfjm |
my $addr_str = sprintf "%6.6o", $val_curr[$ind_vm_ibmreq_addr];
|
| 701 |
|
|
$ibreq_cyc = $cyc_curr;
|
| 702 |
|
|
$ibreq_typ = sprintf "%s%s",
|
| 703 |
|
|
($val_curr[$ind_vm_ibmreq_cacc] ? "c" : "-"),
|
| 704 |
|
|
($val_curr[$ind_vm_ibmreq_racc] ? "r" : "-");
|
| 705 |
8 |
wfjm |
$ibreq_str = sprintf "%s%s%s%s %s",
|
| 706 |
|
|
($val_curr[$ind_vm_ibmreq_we] ? "w" : "r"),
|
| 707 |
|
|
($val_curr[$ind_vm_ibmreq_rmw] ? "m" : " "),
|
| 708 |
2 |
wfjm |
$val_curr[$ind_vm_ibmreq_be1],
|
| 709 |
|
|
$val_curr[$ind_vm_ibmreq_be0],
|
| 710 |
|
|
$addr_str;
|
| 711 |
|
|
$ibreq_we = $val_curr[$ind_vm_ibmreq_we];
|
| 712 |
|
|
$ibreq_act = 1;
|
| 713 |
|
|
if ($ibreq_we) {
|
| 714 |
|
|
$ibreq_str .= sprintf " %6.6o", $val_curr[$ind_vm_ibmreq_din];
|
| 715 |
|
|
} else {
|
| 716 |
|
|
$ibreq_str .= " " x 7;
|
| 717 |
|
|
}
|
| 718 |
|
|
$ibreq_nam = $pdp11_regs{$addr_str};
|
| 719 |
|
|
$ibreq_nam = "" if not defined $ibreq_nam;
|
| 720 |
|
|
}
|
| 721 |
|
|
|
| 722 |
|
|
if ($val_curr[$ind_vm_ibsres_ack]) {
|
| 723 |
|
|
$ibreq_act = 0;
|
| 724 |
|
|
$ibres_str .= sprintf " %s", $val_curr[$ind_vm_ibsres_ack];
|
| 725 |
|
|
if (not $ibreq_we) {
|
| 726 |
|
|
$ibreq_str .= sprintf " %6.6o", $val_curr[$ind_vm_ibsres_dout];
|
| 727 |
|
|
} else {
|
| 728 |
|
|
$ibreq_str .= " " x 7;
|
| 729 |
|
|
}
|
| 730 |
|
|
}
|
| 731 |
|
|
|
| 732 |
|
|
if ($ibreq_act && $val_curr[$ind_vm_ibsres_busy]==0) {
|
| 733 |
|
|
$ibres_str .= "no ACK, no BUSY";
|
| 734 |
|
|
$ibreq_act = 0;
|
| 735 |
|
|
}
|
| 736 |
|
|
}
|
| 737 |
|
|
|
| 738 |
|
|
print "$cyc_str id $id_str\n" if $id_str;
|
| 739 |
|
|
print "$cyc_str ru $ru_str\n" if $ru_str;
|
| 740 |
|
|
if ($emres_str) {
|
| 741 |
|
|
printf "$cyc_str em $emreq_str $emres_str (%d) $emtyp_str\n",
|
| 742 |
|
|
$cyc_curr-$emreq_cyc;
|
| 743 |
|
|
}
|
| 744 |
|
|
if ($ibres_str) {
|
| 745 |
|
|
printf "$cyc_str ib %s $ibreq_str $ibres_str (%d) $ibreq_nam\n",
|
| 746 |
|
|
$ibreq_typ, $cyc_curr-$ibreq_cyc;
|
| 747 |
|
|
}
|
| 748 |
|
|
}
|
| 749 |
|
|
}
|
| 750 |
|
|
|
| 751 |
|
|
close IFILE;
|
| 752 |
|
|
}
|
| 753 |
|
|
|
| 754 |
|
|
#-------------------------------------------------------------------------------
|
| 755 |
|
|
|
| 756 |
|
|
sub code2mnemo {
|
| 757 |
|
|
my ($code) = @_;
|
| 758 |
|
|
|
| 759 |
|
|
foreach my $ele (@pdp11_opcode_tbl) {
|
| 760 |
|
|
if (($code & (~($ele->{mask})) ) == $ele->{code}) {
|
| 761 |
|
|
my $name = $ele->{name};
|
| 762 |
|
|
my $type = $ele->{type};
|
| 763 |
|
|
my $str = $name;
|
| 764 |
|
|
if ($type eq "0arg") {
|
| 765 |
|
|
return $name;
|
| 766 |
|
|
|
| 767 |
|
|
} elsif ($type eq "1arg" or $type eq "1fpp") {
|
| 768 |
|
|
my $dst = $code & 077;
|
| 769 |
|
|
my $dst_str = regmod($dst);
|
| 770 |
|
|
return "$name $dst_str";
|
| 771 |
|
|
|
| 772 |
|
|
} elsif ($type eq "2arg") {
|
| 773 |
|
|
my $src = ($code>>6) & 077;
|
| 774 |
|
|
my $dst = $code & 077;
|
| 775 |
|
|
my $src_str = regmod($src);
|
| 776 |
|
|
my $dst_str = regmod($dst);
|
| 777 |
|
|
return "$name $src_str,$dst_str";
|
| 778 |
|
|
|
| 779 |
|
|
} elsif ($type eq "rdst") {
|
| 780 |
|
|
my $reg = ($code>>6) & 07;
|
| 781 |
|
|
my $src = $code & 077;
|
| 782 |
|
|
my $src_str = regmod($src);
|
| 783 |
|
|
return "$name $src_str,r$reg";
|
| 784 |
|
|
|
| 785 |
|
|
} elsif ($type eq "1reg") {
|
| 786 |
|
|
my $reg = $code & 07;
|
| 787 |
|
|
my $reg_str = "r$reg";
|
| 788 |
|
|
$reg_str = "sp" if $reg == 6;
|
| 789 |
|
|
$reg_str = "pc" if $reg == 7;
|
| 790 |
|
|
return "$name $reg_str";
|
| 791 |
|
|
|
| 792 |
|
|
} elsif ($type eq "br") {
|
| 793 |
|
|
my $off = $code & 0177;
|
| 794 |
|
|
my $sign = "+";
|
| 795 |
|
|
if ($code & 0200) {
|
| 796 |
|
|
$off = -(((~$off) & 0177)+1);
|
| 797 |
|
|
$sign = "-";
|
| 798 |
|
|
}
|
| 799 |
|
|
return sprintf "$name .%s%d.", $sign, abs(2*$off);
|
| 800 |
|
|
|
| 801 |
|
|
} elsif ($type eq "sob") {
|
| 802 |
|
|
my $reg = ($code>>6) & 07;
|
| 803 |
|
|
my $off = $code & 077;
|
| 804 |
|
|
return sprintf "$name r%d,.-%d.", $reg, 2*$off;
|
| 805 |
|
|
|
| 806 |
|
|
} elsif ($type eq "trap") {
|
| 807 |
|
|
my $off = $code & 0377;
|
| 808 |
|
|
return sprintf "$name %3.3o", $off;
|
| 809 |
|
|
|
| 810 |
|
|
} elsif ($type eq "spl") {
|
| 811 |
|
|
my $off = $code & 07;
|
| 812 |
|
|
return sprintf "$name %d", $off;
|
| 813 |
|
|
|
| 814 |
|
|
} elsif ($type eq "ccop") {
|
| 815 |
|
|
my $cc = $code & 017;
|
| 816 |
|
|
return "nop" if ($cc == 0);
|
| 817 |
|
|
return "ccc" if ($code == 0257);
|
| 818 |
|
|
return "scc" if ($code == 0277);
|
| 819 |
|
|
my $str = "";
|
| 820 |
|
|
my $del = "";
|
| 821 |
|
|
if ($code & 010) { $str .= $del . $name . "n", $del = "+" }
|
| 822 |
|
|
if ($code & 004) { $str .= $del . $name . "z", $del = "+" }
|
| 823 |
|
|
if ($code & 002) { $str .= $del . $name . "v", $del = "+" }
|
| 824 |
|
|
if ($code & 001) { $str .= $del . $name . "c", $del = "+" }
|
| 825 |
|
|
return $str;
|
| 826 |
|
|
|
| 827 |
|
|
} elsif ($type eq "jsr") {
|
| 828 |
|
|
my $reg = ($code>>6) & 07;
|
| 829 |
|
|
my $dst = $code & 077;
|
| 830 |
|
|
my $dst_str = regmod($dst);
|
| 831 |
|
|
return "$name r$reg,$dst_str";
|
| 832 |
|
|
|
| 833 |
|
|
} elsif ($type eq "mark") {
|
| 834 |
|
|
my $off = $code & 077;
|
| 835 |
|
|
return sprintf "$name %3.3o", $off;
|
| 836 |
|
|
|
| 837 |
|
|
} elsif ($type eq "rfpp") {
|
| 838 |
|
|
my $reg = ($code>>6) & 03;
|
| 839 |
|
|
my $dst = $code & 077;
|
| 840 |
|
|
my $dst_str = regmod($dst,"f");
|
| 841 |
|
|
return "$name f$reg,$dst_str";
|
| 842 |
|
|
|
| 843 |
|
|
} else {
|
| 844 |
|
|
return "?type?";
|
| 845 |
|
|
}
|
| 846 |
|
|
}
|
| 847 |
|
|
}
|
| 848 |
|
|
return "=inval=";
|
| 849 |
|
|
}
|
| 850 |
|
|
|
| 851 |
|
|
#-------------------------------------------------------------------------------
|
| 852 |
|
|
sub regmod {
|
| 853 |
|
|
my ($regmod,$pref) = @_;
|
| 854 |
|
|
my $mod = ($regmod>>3) & 07;
|
| 855 |
|
|
my $reg = $regmod & 07;
|
| 856 |
|
|
|
| 857 |
|
|
$pref = "r" if not defined $pref or $reg>5;
|
| 858 |
|
|
|
| 859 |
|
|
my $reg_str = "r$reg";
|
| 860 |
|
|
$reg_str = "sp" if $reg == 6;
|
| 861 |
|
|
$reg_str = "pc" if $reg == 7;
|
| 862 |
|
|
|
| 863 |
|
|
if ($mod == 0) { # mode 0: Rx { Fx for float }
|
| 864 |
|
|
$reg_str = "f$reg" if defined $pref && $pref eq "f" && $reg<=5;
|
| 865 |
|
|
return $reg_str;
|
| 866 |
|
|
} elsif ($mod == 1) { # mode 1: (Rx)
|
| 867 |
|
|
return "($reg_str)";
|
| 868 |
|
|
} elsif ($mod == 2 || $mod == 3) { # mode 2/3: (Rx)+ @(Rx)+
|
| 869 |
|
|
my $ind = ($mod == 3) ? "@" : "";
|
| 870 |
|
|
if ($reg != 7) { # if reg != pc
|
| 871 |
|
|
return "$ind($reg_str)+";
|
| 872 |
|
|
} else { # if reg == pc
|
| 873 |
|
|
my $str = sprintf "$ind#nnn"; # 27 -> #nnn; 37 -> @#nnn
|
| 874 |
|
|
return $str;
|
| 875 |
|
|
}
|
| 876 |
|
|
} elsif ($mod == 4 || $mod == 5) { # mode 4/5: -(Rx) @-(Rx)
|
| 877 |
|
|
my $ind = ($mod == 5) ? "@" : "";
|
| 878 |
|
|
return "$ind-($reg_str)";
|
| 879 |
|
|
} elsif ($mod == 6 || $mod == 7) { # mode 6/7: nn(Rx) @nn(Rx)
|
| 880 |
|
|
my $ind = ($mod == 7) ? "@" : "";
|
| 881 |
|
|
return "${ind}nnn($reg_str)";
|
| 882 |
|
|
}
|
| 883 |
|
|
}
|
| 884 |
|
|
|
| 885 |
|
|
#-------------------------------------------------------------------------------
|
| 886 |
|
|
|
| 887 |
|
|
sub print_help {
|
| 888 |
|
|
print "usage: tmuconf file\n";
|
| 889 |
|
|
print " --help this message\n";
|
| 890 |
|
|
print " --dump dump all information\n";
|
| 891 |
|
|
print " --cdump dump only changes relative to prev cycle\n";
|
| 892 |
|
|
print " --t_id trace instruction decodes\n";
|
| 893 |
|
|
print " --t_ru trace register updates\n";
|
| 894 |
|
|
print " --t_em trace em transactions\n";
|
| 895 |
|
|
print " --t_ib trace ib transactions\n";
|
| 896 |
|
|
}
|
