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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: faxil_master.v (Formal properties of an AXI lite master)
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//
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// Project: Pipelined Wishbone to AXI converter
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//
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// Purpose:
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2018-2019, Gisselquist Technology, LLC
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//
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// This file is part of the pipelined Wishbone to AXI converter project, a
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// project that contains multiple bus bridging designs and formal bus property
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// sets.
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//
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// The bus bridge designs and property sets are free RTL designs: you can
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// redistribute them and/or modify any of them under the terms of the GNU
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// Lesser General Public License as published by the Free Software Foundation,
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// either version 3 of the License, or (at your option) any later version.
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//
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// The bus bridge designs and property sets are distributed in the hope that
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// they will be useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with these designs. (It's in the $(ROOT)/doc directory. Run make
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// with no target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: LGPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/lgpl.html
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype none
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//
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module faxil_master #(
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parameter C_AXI_DATA_WIDTH = 32,// Fixed, width of the AXI R&W data
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parameter C_AXI_ADDR_WIDTH = 28,// AXI Address width (log wordsize)
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localparam DW = C_AXI_DATA_WIDTH,
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localparam AW = C_AXI_ADDR_WIDTH,
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parameter [0:0] F_OPT_HAS_CACHE = 1'b0,
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parameter [0:0] F_OPT_NO_READS = 1'b0,
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parameter [0:0] F_OPT_NO_WRITES = 1'b0,
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parameter [0:0] F_OPT_BRESP = 1'b1,
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parameter [0:0] F_OPT_RRESP = 1'b1,
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parameter [0:0] F_OPT_ASSUME_RESET = 1'b0,
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parameter F_LGDEPTH = 4,
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parameter [(F_LGDEPTH-1):0] F_AXI_MAXWAIT = 12,
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parameter [(F_LGDEPTH-1):0] F_AXI_MAXDELAY = 12
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) (
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input wire i_clk, // System clock
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input wire i_axi_reset_n,
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// AXI write address channel signals
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input wire i_axi_awready,//Slave is ready to accept
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input wire [AW-1:0] i_axi_awaddr, // Write address
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input wire [3:0] i_axi_awcache, // Write Cache type
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input wire [2:0] i_axi_awprot, // Write Protection type
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input wire i_axi_awvalid, // Write address valid
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// AXI write data channel signals
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input wire i_axi_wready, // Write data ready
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input wire [DW-1:0] i_axi_wdata, // Write data
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input wire [DW/8-1:0] i_axi_wstrb, // Write strobes
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input wire i_axi_wvalid, // Write valid
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// AXI write response channel signals
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input wire [1:0] i_axi_bresp, // Write response
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input wire i_axi_bvalid, // Write reponse valid
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input wire i_axi_bready, // Response ready
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// AXI read address channel signals
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input wire i_axi_arready, // Read address ready
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input wire [AW-1:0] i_axi_araddr, // Read address
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input wire [3:0] i_axi_arcache, // Read Cache type
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input wire [2:0] i_axi_arprot, // Read Protection type
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input wire i_axi_arvalid, // Read address valid
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// AXI read data channel signals
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input wire [1:0] i_axi_rresp, // Read response
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input wire i_axi_rvalid, // Read reponse valid
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input wire [DW-1:0] i_axi_rdata, // Read data
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input wire i_axi_rready, // Read Response ready
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//
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output reg [(F_LGDEPTH-1):0] f_axi_rd_outstanding,
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output reg [(F_LGDEPTH-1):0] f_axi_wr_outstanding,
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output reg [(F_LGDEPTH-1):0] f_axi_awr_outstanding
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);
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//*****************************************************************************
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// Parameter declarations
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//*****************************************************************************
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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// wire w_fifo_full;
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wire axi_rd_ack, axi_wr_ack, axi_ard_req, axi_awr_req, axi_wr_req,
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axi_rd_err, axi_wr_err;
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//
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assign axi_ard_req = (i_axi_arvalid)&&(i_axi_arready);
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assign axi_awr_req = (i_axi_awvalid)&&(i_axi_awready);
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assign axi_wr_req = (i_axi_wvalid )&&(i_axi_wready);
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//
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assign axi_rd_ack = (i_axi_rvalid)&&(i_axi_rready);
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assign axi_wr_ack = (i_axi_bvalid)&&(i_axi_bready);
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assign axi_rd_err = (axi_rd_ack)&&(i_axi_rresp[1]);
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assign axi_wr_err = (axi_wr_ack)&&(i_axi_bresp[1]);
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`define SLAVE_ASSUME assert
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`define SLAVE_ASSERT assume
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//
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// Setup
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//
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reg f_past_valid;
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integer k;
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initial f_past_valid = 1'b0;
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always @(posedge i_clk)
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f_past_valid <= 1'b1;
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generate if (F_OPT_ASSUME_RESET)
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begin : ASSUME_INIITAL_RESET
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always @(*)
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if (!f_past_valid)
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assume(!i_axi_reset_n);
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end else begin : ASSERT_INIITAL_RESET
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always @(*)
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if (!f_past_valid)
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assert(!i_axi_reset_n);
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end endgenerate
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////////////////////////////////////////////////////////////////////////
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//
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//
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// Reset properties
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//
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//
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////////////////////////////////////////////////////////////////////////
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//
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// If asserted, the reset must be asserted for a minimum of 16 clocks
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reg [3:0] f_reset_length;
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initial f_reset_length = 0;
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always @(posedge i_clk)
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if (i_axi_reset_n)
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f_reset_length <= 0;
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else if (!(&f_reset_length))
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f_reset_length <= f_reset_length + 1'b1;
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generate if (F_OPT_ASSUME_RESET)
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begin : ASSUME_RESET
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_axi_reset_n))&&(!$past(&f_reset_length)))
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assume(!i_axi_reset_n);
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always @(*)
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if ((f_reset_length > 0)&&(f_reset_length < 4'hf))
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assume(!i_axi_reset_n);
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end else begin : ASSERT_RESET
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_axi_reset_n))&&(!$past(&f_reset_length)))
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assert(!i_axi_reset_n);
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always @(*)
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if ((f_reset_length > 0)&&(f_reset_length < 4'hf))
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assert(!i_axi_reset_n);
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end endgenerate
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always @(posedge i_clk)
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if ((!f_past_valid)||(!$past(i_axi_reset_n)))
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begin
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`SLAVE_ASSUME(!i_axi_arvalid);
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`SLAVE_ASSUME(!i_axi_awvalid);
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`SLAVE_ASSUME(!i_axi_wvalid);
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//
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`SLAVE_ASSERT(!i_axi_bvalid);
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`SLAVE_ASSERT(!i_axi_rvalid);
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end
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////////////////////////////////////////////////////////////////////////
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//
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//
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// Constant input assumptions (cache and prot)
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//
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//
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////////////////////////////////////////////////////////////////////////
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always @(*)
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if (i_axi_awvalid)
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begin
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`SLAVE_ASSUME(i_axi_awprot == 3'h0);
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if (F_OPT_HAS_CACHE)
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// Normal non-cachable, but bufferable
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`SLAVE_ASSUME(i_axi_awcache == 4'h3);
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else
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// No caching capability
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`SLAVE_ASSUME(i_axi_awcache == 4'h0);
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end
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always @(*)
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if (i_axi_arvalid)
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begin
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`SLAVE_ASSUME(i_axi_arprot == 3'h0);
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if (F_OPT_HAS_CACHE)
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// Normal non-cachable, but bufferable
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`SLAVE_ASSUME(i_axi_arcache == 4'h3);
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else
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// No caching capability
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`SLAVE_ASSUME(i_axi_arcache == 4'h0);
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end
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always @(*)
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if ((i_axi_bvalid)&&(!F_OPT_BRESP))
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`SLAVE_ASSERT(i_axi_bresp == 0);
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always @(*)
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if ((i_axi_rvalid)&&(!F_OPT_RRESP))
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`SLAVE_ASSERT(i_axi_rresp == 0);
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always @(*)
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if (i_axi_bvalid)
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`SLAVE_ASSERT(i_axi_bresp != 2'b01); // Exclusive access not allowed
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always @(*)
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if (i_axi_rvalid)
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`SLAVE_ASSERT(i_axi_rresp != 2'b01); // Exclusive access not allowed
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////////////////////////////////////////////////////////////////////////
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//
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//
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// Stability assumptions
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//
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//
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////////////////////////////////////////////////////////////////////////
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// Assume any response from the bus will not change prior to that
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// response being accepted
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always @(posedge i_clk)
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if ((f_past_valid)&&($past(i_axi_reset_n)))
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begin
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// Write address channel
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if ((f_past_valid)&&($past(i_axi_awvalid))&&(!$past(i_axi_awready)))
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begin
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`SLAVE_ASSUME(i_axi_awvalid);
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`SLAVE_ASSUME($stable(i_axi_awaddr));
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end
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// Write data channel
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if ((f_past_valid)&&($past(i_axi_wvalid))&&(!$past(i_axi_wready)))
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begin
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`SLAVE_ASSUME(i_axi_wvalid);
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`SLAVE_ASSUME($stable(i_axi_wstrb));
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`SLAVE_ASSUME($stable(i_axi_wdata));
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end
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// Incoming Read address channel
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if ((f_past_valid)&&($past(i_axi_arvalid))&&(!$past(i_axi_arready)))
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begin
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`SLAVE_ASSUME(i_axi_arvalid);
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`SLAVE_ASSUME($stable(i_axi_araddr));
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end
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if ((f_past_valid)&&($past(i_axi_rvalid))&&(!$past(i_axi_rready)))
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begin
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`SLAVE_ASSERT(i_axi_rvalid);
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`SLAVE_ASSERT($stable(i_axi_rresp));
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`SLAVE_ASSERT($stable(i_axi_rdata));
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end
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if ((f_past_valid)&&($past(i_axi_bvalid))&&(!$past(i_axi_bready)))
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begin
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`SLAVE_ASSERT(i_axi_bvalid);
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`SLAVE_ASSERT($stable(i_axi_bresp));
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end
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end
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// Nothing should be returned or requested on the first clock
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initial `SLAVE_ASSUME(!i_axi_arvalid);
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initial `SLAVE_ASSUME(!i_axi_awvalid);
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initial `SLAVE_ASSUME(!i_axi_wvalid);
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//
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initial `SLAVE_ASSERT(!i_axi_bvalid);
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initial `SLAVE_ASSERT(!i_axi_rvalid);
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////////////////////////////////////////////////////////////////////////
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//
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//
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// Insist upon a maximum delay before a request is accepted
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//
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//
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////////////////////////////////////////////////////////////////////////
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generate if (F_AXI_MAXWAIT > 0)
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begin : CHECK_STALL_COUNT
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//
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// AXI write address channel
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//
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//
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reg [(F_LGDEPTH-1):0] f_axi_awstall,
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f_axi_wstall,
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f_axi_arstall,
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f_axi_bstall,
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f_axi_rstall;
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initial f_axi_awstall = 0;
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always @(posedge i_clk)
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if ((!i_axi_reset_n)||(!i_axi_awvalid)||(i_axi_awready))
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f_axi_awstall <= 0;
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else if ((f_axi_awr_outstanding >= f_axi_wr_outstanding)
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&&(i_axi_awvalid && !i_axi_wvalid))
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|
|
// If we are waiting for the write channel to be valid
|
| 324 |
|
|
// then don't count stalls
|
| 325 |
|
|
f_axi_awstall <= 0;
|
| 326 |
|
|
else if ((!i_axi_bvalid)||(i_axi_bready))
|
| 327 |
|
|
f_axi_awstall <= f_axi_awstall + 1'b1;
|
| 328 |
|
|
|
| 329 |
|
|
always @(*)
|
| 330 |
|
|
`SLAVE_ASSERT(f_axi_awstall < F_AXI_MAXWAIT);
|
| 331 |
|
|
|
| 332 |
|
|
//
|
| 333 |
|
|
// AXI write data channel
|
| 334 |
|
|
//
|
| 335 |
|
|
//
|
| 336 |
|
|
initial f_axi_wstall = 0;
|
| 337 |
|
|
always @(posedge i_clk)
|
| 338 |
|
|
if ((!i_axi_reset_n)||(!i_axi_wvalid)||(i_axi_wready))
|
| 339 |
|
|
f_axi_wstall <= 0;
|
| 340 |
|
|
else if ((f_axi_wr_outstanding >= f_axi_awr_outstanding)
|
| 341 |
|
|
&&(!i_axi_awvalid && i_axi_wvalid))
|
| 342 |
|
|
// If we are waiting for the write address channel
|
| 343 |
|
|
// to be valid, then don't count stalls
|
| 344 |
|
|
f_axi_wstall <= 0;
|
| 345 |
|
|
else if ((!i_axi_bvalid)||(i_axi_bready))
|
| 346 |
|
|
f_axi_wstall <= f_axi_wstall + 1'b1;
|
| 347 |
|
|
|
| 348 |
|
|
always @(*)
|
| 349 |
|
|
`SLAVE_ASSERT(f_axi_wstall < F_AXI_MAXWAIT);
|
| 350 |
|
|
|
| 351 |
|
|
//
|
| 352 |
|
|
// AXI read address channel
|
| 353 |
|
|
//
|
| 354 |
|
|
//
|
| 355 |
|
|
initial f_axi_arstall = 0;
|
| 356 |
|
|
always @(posedge i_clk)
|
| 357 |
|
|
if ((!i_axi_reset_n)||(!i_axi_arvalid)||(i_axi_arready))
|
| 358 |
|
|
f_axi_arstall <= 0;
|
| 359 |
|
|
else if ((!i_axi_rvalid)||(i_axi_rready))
|
| 360 |
|
|
f_axi_arstall <= f_axi_arstall + 1'b1;
|
| 361 |
|
|
|
| 362 |
|
|
always @(*)
|
| 363 |
|
|
`SLAVE_ASSERT(f_axi_arstall < F_AXI_MAXWAIT);
|
| 364 |
|
|
|
| 365 |
|
|
// AXI write response channel
|
| 366 |
|
|
initial f_axi_bstall = 0;
|
| 367 |
|
|
always @(posedge i_clk)
|
| 368 |
|
|
if ((!i_axi_reset_n)||(!i_axi_bvalid)||(i_axi_bready))
|
| 369 |
|
|
f_axi_bstall <= 0;
|
| 370 |
|
|
else
|
| 371 |
|
|
f_axi_bstall <= f_axi_bstall + 1'b1;
|
| 372 |
|
|
|
| 373 |
|
|
always @(*)
|
| 374 |
|
|
`SLAVE_ASSUME(f_axi_bstall < F_AXI_MAXWAIT);
|
| 375 |
|
|
|
| 376 |
|
|
// AXI read response channel
|
| 377 |
|
|
initial f_axi_rstall = 0;
|
| 378 |
|
|
always @(posedge i_clk)
|
| 379 |
|
|
if ((!i_axi_reset_n)||(!i_axi_rvalid)||(i_axi_rready))
|
| 380 |
|
|
f_axi_rstall <= 0;
|
| 381 |
|
|
else
|
| 382 |
|
|
f_axi_rstall <= f_axi_rstall + 1'b1;
|
| 383 |
|
|
|
| 384 |
|
|
always @(*)
|
| 385 |
|
|
`SLAVE_ASSUME(f_axi_rstall < F_AXI_MAXWAIT);
|
| 386 |
|
|
|
| 387 |
|
|
end endgenerate
|
| 388 |
|
|
|
| 389 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 390 |
|
|
//
|
| 391 |
|
|
//
|
| 392 |
|
|
// Xilinx extensions/guarantees to the AXI protocol
|
| 393 |
|
|
//
|
| 394 |
|
|
// 1. The address line will never be more than two clocks ahead of
|
| 395 |
|
|
// the write data channel, and
|
| 396 |
|
|
// 2. The write data channel will never be more than one clock
|
| 397 |
|
|
// ahead of the address channel.
|
| 398 |
|
|
//
|
| 399 |
|
|
//
|
| 400 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 401 |
|
|
//
|
| 402 |
|
|
//
|
| 403 |
|
|
// Rule number one:
|
| 404 |
|
|
always @(posedge i_clk)
|
| 405 |
|
|
if ((i_axi_reset_n)&&($past(i_axi_reset_n))
|
| 406 |
|
|
&&($past(i_axi_awvalid && !i_axi_wvalid,2))
|
| 407 |
|
|
&&($past(f_axi_awr_outstanding>=f_axi_wr_outstanding,2))
|
| 408 |
|
|
&&(!$past(i_axi_wvalid)))
|
| 409 |
|
|
`SLAVE_ASSUME(i_axi_wvalid);
|
| 410 |
|
|
|
| 411 |
|
|
// Rule number two:
|
| 412 |
|
|
always @(posedge i_clk)
|
| 413 |
|
|
if ((i_axi_reset_n)&&(!$past(i_axi_awvalid))&&($past(i_axi_wvalid))
|
| 414 |
|
|
&&(f_axi_awr_outstanding < f_axi_wr_outstanding))
|
| 415 |
|
|
`SLAVE_ASSUME(i_axi_awvalid);
|
| 416 |
|
|
|
| 417 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 418 |
|
|
//
|
| 419 |
|
|
//
|
| 420 |
|
|
// Count outstanding transactions. With these measures, we count
|
| 421 |
|
|
// once per any burst.
|
| 422 |
|
|
//
|
| 423 |
|
|
//
|
| 424 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 425 |
|
|
initial f_axi_awr_outstanding = 0;
|
| 426 |
|
|
always @(posedge i_clk)
|
| 427 |
|
|
if (!i_axi_reset_n)
|
| 428 |
|
|
f_axi_awr_outstanding <= 0;
|
| 429 |
|
|
else case({ (axi_awr_req), (axi_wr_ack) })
|
| 430 |
|
|
2'b10: f_axi_awr_outstanding <= f_axi_awr_outstanding + 1'b1;
|
| 431 |
|
|
2'b01: f_axi_awr_outstanding <= f_axi_awr_outstanding - 1'b1;
|
| 432 |
|
|
default: begin end
|
| 433 |
|
|
endcase
|
| 434 |
|
|
|
| 435 |
|
|
initial f_axi_wr_outstanding = 0;
|
| 436 |
|
|
always @(posedge i_clk)
|
| 437 |
|
|
if (!i_axi_reset_n)
|
| 438 |
|
|
f_axi_wr_outstanding <= 0;
|
| 439 |
|
|
else case({ (axi_wr_req), (axi_wr_ack) })
|
| 440 |
|
|
2'b01: f_axi_wr_outstanding <= f_axi_wr_outstanding - 1'b1;
|
| 441 |
|
|
2'b10: f_axi_wr_outstanding <= f_axi_wr_outstanding + 1'b1;
|
| 442 |
|
|
endcase
|
| 443 |
|
|
|
| 444 |
|
|
initial f_axi_rd_outstanding = 0;
|
| 445 |
|
|
always @(posedge i_clk)
|
| 446 |
|
|
if (!i_axi_reset_n)
|
| 447 |
|
|
f_axi_rd_outstanding <= 0;
|
| 448 |
|
|
else case({ (axi_ard_req), (axi_rd_ack) })
|
| 449 |
|
|
2'b01: f_axi_rd_outstanding <= f_axi_rd_outstanding - 1'b1;
|
| 450 |
|
|
2'b10: f_axi_rd_outstanding <= f_axi_rd_outstanding + 1'b1;
|
| 451 |
|
|
endcase
|
| 452 |
|
|
|
| 453 |
|
|
//
|
| 454 |
|
|
// Do not let the number of outstanding requests overflow
|
| 455 |
|
|
always @(posedge i_clk)
|
| 456 |
|
|
`SLAVE_ASSERT(f_axi_wr_outstanding < {(F_LGDEPTH){1'b1}});
|
| 457 |
|
|
always @(posedge i_clk)
|
| 458 |
|
|
`SLAVE_ASSERT(f_axi_awr_outstanding < {(F_LGDEPTH){1'b1}});
|
| 459 |
|
|
always @(posedge i_clk)
|
| 460 |
|
|
`SLAVE_ASSERT(f_axi_rd_outstanding < {(F_LGDEPTH){1'b1}});
|
| 461 |
|
|
|
| 462 |
|
|
//
|
| 463 |
|
|
// That means that requests need to stop when we're almost full
|
| 464 |
|
|
always @(posedge i_clk)
|
| 465 |
|
|
if (f_axi_awr_outstanding == { {(F_LGDEPTH-1){1'b1}}, 1'b0} )
|
| 466 |
|
|
assert(!i_axi_awvalid);
|
| 467 |
|
|
always @(posedge i_clk)
|
| 468 |
|
|
if (f_axi_wr_outstanding == { {(F_LGDEPTH-1){1'b1}}, 1'b0} )
|
| 469 |
|
|
assert(!i_axi_wvalid);
|
| 470 |
|
|
always @(posedge i_clk)
|
| 471 |
|
|
if (f_axi_rd_outstanding == { {(F_LGDEPTH-1){1'b1}}, 1'b0} )
|
| 472 |
|
|
assert(!i_axi_arvalid);
|
| 473 |
|
|
|
| 474 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 475 |
|
|
//
|
| 476 |
|
|
//
|
| 477 |
|
|
// Insist that all responses are returned in less than a maximum delay
|
| 478 |
|
|
// In this case, we count responses within a burst, rather than entire
|
| 479 |
|
|
// bursts.
|
| 480 |
|
|
//
|
| 481 |
|
|
//
|
| 482 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 483 |
|
|
generate if (F_AXI_MAXDELAY > 0)
|
| 484 |
|
|
begin : CHECK_MAX_DELAY
|
| 485 |
|
|
|
| 486 |
|
|
reg [(F_LGDEPTH-1):0] f_axi_wr_ack_delay,
|
| 487 |
|
|
f_axi_rd_ack_delay;
|
| 488 |
|
|
|
| 489 |
|
|
initial f_axi_rd_ack_delay = 0;
|
| 490 |
|
|
always @(posedge i_clk)
|
| 491 |
|
|
if ((!i_axi_reset_n)||(i_axi_rvalid)||(f_axi_rd_outstanding==0))
|
| 492 |
|
|
f_axi_rd_ack_delay <= 0;
|
| 493 |
|
|
else
|
| 494 |
|
|
f_axi_rd_ack_delay <= f_axi_rd_ack_delay + 1'b1;
|
| 495 |
|
|
|
| 496 |
|
|
initial f_axi_wr_ack_delay = 0;
|
| 497 |
|
|
always @(posedge i_clk)
|
| 498 |
|
|
if ((!i_axi_reset_n)||(i_axi_bvalid)||(f_axi_wr_outstanding==0))
|
| 499 |
|
|
f_axi_wr_ack_delay <= 0;
|
| 500 |
|
|
else if (f_axi_wr_outstanding > 0)
|
| 501 |
|
|
f_axi_wr_ack_delay <= f_axi_wr_ack_delay + 1'b1;
|
| 502 |
|
|
|
| 503 |
|
|
always @(*)
|
| 504 |
|
|
`SLAVE_ASSERT(f_axi_rd_ack_delay < F_AXI_MAXDELAY);
|
| 505 |
|
|
|
| 506 |
|
|
always @(*)
|
| 507 |
|
|
`SLAVE_ASSERT(f_axi_wr_ack_delay < F_AXI_MAXDELAY);
|
| 508 |
|
|
|
| 509 |
|
|
end endgenerate
|
| 510 |
|
|
|
| 511 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 512 |
|
|
//
|
| 513 |
|
|
//
|
| 514 |
|
|
// Assume acknowledgements must follow requests
|
| 515 |
|
|
//
|
| 516 |
|
|
// The f_axi*outstanding counters count the number of requests. No
|
| 517 |
|
|
// acknowledgment should issue without a pending request
|
| 518 |
|
|
// burst. Further, the spec is clear: you can't acknowledge something
|
| 519 |
|
|
// on the same clock you get the request. There must be at least one
|
| 520 |
|
|
// clock delay.
|
| 521 |
|
|
//
|
| 522 |
|
|
//
|
| 523 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 524 |
|
|
|
| 525 |
|
|
//
|
| 526 |
|
|
// AXI write response channel
|
| 527 |
|
|
//
|
| 528 |
|
|
always @(posedge i_clk)
|
| 529 |
|
|
if (i_axi_bvalid)
|
| 530 |
|
|
begin
|
| 531 |
|
|
`SLAVE_ASSERT(f_axi_awr_outstanding > 0);
|
| 532 |
|
|
`SLAVE_ASSERT(f_axi_wr_outstanding > 0);
|
| 533 |
|
|
end
|
| 534 |
|
|
|
| 535 |
|
|
//
|
| 536 |
|
|
// AXI read data channel signals
|
| 537 |
|
|
//
|
| 538 |
|
|
always @(posedge i_clk)
|
| 539 |
|
|
if (i_axi_rvalid)
|
| 540 |
|
|
`SLAVE_ASSERT(f_axi_rd_outstanding > 0);
|
| 541 |
|
|
|
| 542 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 543 |
|
|
//
|
| 544 |
|
|
//
|
| 545 |
|
|
// Optionally disable either read or write channels (or both??)
|
| 546 |
|
|
//
|
| 547 |
|
|
//
|
| 548 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 549 |
|
|
|
| 550 |
|
|
initial assert((!F_OPT_NO_READS)||(!F_OPT_NO_WRITES));
|
| 551 |
|
|
|
| 552 |
|
|
generate if (F_OPT_NO_READS)
|
| 553 |
|
|
begin : NO_READS
|
| 554 |
|
|
|
| 555 |
|
|
always @(*)
|
| 556 |
|
|
`SLAVE_ASSUME(i_axi_arvalid == 0);
|
| 557 |
|
|
always @(*)
|
| 558 |
|
|
`SLAVE_ASSERT(f_axi_rd_outstanding == 0);
|
| 559 |
|
|
always @(*)
|
| 560 |
|
|
`SLAVE_ASSERT(i_axi_rvalid == 0);
|
| 561 |
|
|
|
| 562 |
|
|
end endgenerate
|
| 563 |
|
|
|
| 564 |
|
|
generate if (F_OPT_NO_WRITES)
|
| 565 |
|
|
begin : NO_WRITES
|
| 566 |
|
|
|
| 567 |
|
|
always @(*)
|
| 568 |
|
|
`SLAVE_ASSUME(i_axi_awvalid == 0);
|
| 569 |
|
|
always @(*)
|
| 570 |
|
|
`SLAVE_ASSUME(i_axi_wvalid == 0);
|
| 571 |
|
|
always @(*)
|
| 572 |
|
|
`SLAVE_ASSERT(f_axi_wr_outstanding == 0);
|
| 573 |
|
|
always @(*)
|
| 574 |
|
|
`SLAVE_ASSERT(f_axi_awr_outstanding == 0);
|
| 575 |
|
|
always @(*)
|
| 576 |
|
|
`SLAVE_ASSERT(i_axi_bvalid == 0);
|
| 577 |
|
|
|
| 578 |
|
|
end endgenerate
|
| 579 |
|
|
|
| 580 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 581 |
|
|
//
|
| 582 |
|
|
//
|
| 583 |
|
|
// Cover properties
|
| 584 |
|
|
//
|
| 585 |
|
|
// We'll use this to prove that transactions are even possible, and
|
| 586 |
|
|
// hence that we haven't so constrained the bus that nothing can take
|
| 587 |
|
|
// place.
|
| 588 |
|
|
//
|
| 589 |
|
|
//
|
| 590 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 591 |
|
|
|
| 592 |
|
|
//
|
| 593 |
|
|
// AXI write response channel
|
| 594 |
|
|
//
|
| 595 |
|
|
always @(posedge i_clk)
|
| 596 |
|
|
if (!F_OPT_NO_WRITES)
|
| 597 |
|
|
cover((i_axi_bvalid)&&(i_axi_bready));
|
| 598 |
|
|
|
| 599 |
|
|
//
|
| 600 |
|
|
// AXI read response channel
|
| 601 |
|
|
//
|
| 602 |
|
|
always @(posedge i_clk)
|
| 603 |
|
|
if (!F_OPT_NO_READS)
|
| 604 |
|
|
cover((i_axi_rvalid)&&(i_axi_rready));
|
| 605 |
|
|
endmodule
|
