URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

Subversion Repositories wb2axip

[/] [wb2axip/] [trunk/] [bench/] [formal/] [wbm2axisp.ys] - Blame information for rev 10

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read_verilog -D WBM2AXISP -formal ../../rtl/wbm2axisp.v
read_verilog -D WBM2AXISP -formal faxi_master.v
read_verilog -D WBM2AXISP -formal fwb_slave.v
prep -top wbm2axisp -nordff
clk2fflogic
opt -share_all
write_smt2 -wires wbm2axisp.smt2

Line No.	Rev	Author	Line
1	10	dgisselq	`read_verilog -D WBM2AXISP -formal ../../rtl/wbm2axisp.v`
2			`read_verilog -D WBM2AXISP -formal faxi_master.v`
3			`read_verilog -D WBM2AXISP -formal fwb_slave.v`
4			`prep -top wbm2axisp -nordff`
5			`clk2fflogic`
6			`opt -share_all`
7			`write_smt2 -wires wbm2axisp.smt2`

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Subversion Repositories wb2axip

[/] [wb2axip/] [trunk/] [bench/] [formal/] [wbm2axisp.ys] - Blame information for rev 10