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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: axilrd2wbsp.v (AXI lite to wishbone slave, read channel)
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//
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// Project: Pipelined Wishbone to AXI converter
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//
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// Purpose: Bridge an AXI lite read channel pair to a single wishbone read
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// channel.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2016-2019, Gisselquist Technology, LLC
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//
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// This file is part of the pipelined Wishbone to AXI converter project, a
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// project that contains multiple bus bridging designs and formal bus property
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// sets.
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//
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// The bus bridge designs and property sets are free RTL designs: you can
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// redistribute them and/or modify any of them under the terms of the GNU
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// Lesser General Public License as published by the Free Software Foundation,
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// either version 3 of the License, or (at your option) any later version.
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//
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// The bus bridge designs and property sets are distributed in the hope that
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// they will be useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with these designs. (It's in the $(ROOT)/doc directory. Run make
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// with no target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: LGPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/lgpl.html
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype none
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//
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module axilrd2wbsp(i_clk, i_axi_reset_n,
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// AXI read address channel signals
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o_axi_arready, i_axi_araddr, i_axi_arcache, i_axi_arprot, i_axi_arvalid,
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// AXI read data channel signals
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o_axi_rresp, o_axi_rvalid, o_axi_rdata, i_axi_rready,
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// We'll share the clock and the reset
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o_wb_cyc, o_wb_stb, o_wb_addr,
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i_wb_ack, i_wb_stall, i_wb_data, i_wb_err
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`ifdef FORMAL
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, f_first, f_mid, f_last
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`endif
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);
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localparam C_AXI_DATA_WIDTH = 32;// Width of the AXI R&W data
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parameter C_AXI_ADDR_WIDTH = 28; // AXI Address width
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localparam AW = C_AXI_ADDR_WIDTH-2;// WB Address width
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parameter LGFIFO = 3;
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input wire i_clk; // Bus clock
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input wire i_axi_reset_n; // Bus reset
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// AXI read address channel signals
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output reg o_axi_arready; // Read address ready
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input wire [C_AXI_ADDR_WIDTH-1:0] i_axi_araddr; // Read address
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input wire [3:0] i_axi_arcache; // Read Cache type
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input wire [2:0] i_axi_arprot; // Read Protection type
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input wire i_axi_arvalid; // Read address valid
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// AXI read data channel signals
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output reg [1:0] o_axi_rresp; // Read response
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output reg o_axi_rvalid; // Read reponse valid
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output wire [C_AXI_DATA_WIDTH-1:0] o_axi_rdata; // Read data
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input wire i_axi_rready; // Read Response ready
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// We'll share the clock and the reset
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output reg o_wb_cyc;
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output reg o_wb_stb;
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output reg [(AW-1):0] o_wb_addr;
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input wire i_wb_ack;
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input wire i_wb_stall;
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input [(C_AXI_DATA_WIDTH-1):0] i_wb_data;
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input wire i_wb_err;
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`ifdef FORMAL
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// Output connections only used in formal mode
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output wire [LGFIFO:0] f_first;
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output wire [LGFIFO:0] f_mid;
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output wire [LGFIFO:0] f_last;
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`endif
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localparam DW = C_AXI_DATA_WIDTH;
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wire w_reset;
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assign w_reset = (!i_axi_reset_n);
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reg r_stb;
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reg [AW-1:0] r_addr;
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localparam FLEN=(1<<LGFIFO);
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reg [DW-1:0] dfifo [0:(FLEN-1)];
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reg fifo_full, fifo_empty;
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reg [LGFIFO:0] r_first, r_mid, r_last, r_next;
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wire [LGFIFO:0] w_first_plus_one;
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wire [LGFIFO:0] next_first, next_last, next_mid, fifo_fill;
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reg wb_pending, last_ack;
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reg [LGFIFO:0] wb_outstanding;
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initial o_wb_cyc = 1'b0;
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initial o_wb_stb = 1'b0;
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always @(posedge i_clk)
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if ((w_reset)||((o_wb_cyc)&&(i_wb_err))||(err_state))
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o_wb_stb <= 1'b0;
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else if (r_stb || ((i_axi_arvalid)&&(o_axi_arready)))
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o_wb_stb <= 1'b1;
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else if ((o_wb_cyc)&&(!i_wb_stall))
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o_wb_stb <= 1'b0;
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always @(*)
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o_wb_cyc = (wb_pending)||(o_wb_stb);
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always @(posedge i_clk)
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if (r_stb && !i_wb_stall)
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o_wb_addr <= r_addr;
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else if ((o_axi_arready)&&((!o_wb_stb)||(!i_wb_stall)))
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o_wb_addr <= i_axi_araddr[AW+1:2];
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// Shadow request
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// r_stb, r_addr
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initial r_stb = 1'b0;
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always @(posedge i_clk)
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begin
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if ((i_axi_arvalid)&&(o_axi_arready)&&(o_wb_stb)&&(i_wb_stall))
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begin
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r_stb <= 1'b1;
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r_addr <= i_axi_araddr[AW+1:2];
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end else if ((!i_wb_stall)||(!o_wb_cyc))
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r_stb <= 1'b0;
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if ((w_reset)||(o_wb_cyc)&&(i_wb_err)||(err_state))
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r_stb <= 1'b0;
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end
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initial wb_pending = 0;
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initial wb_outstanding = 0;
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initial last_ack = 1;
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always @(posedge i_clk)
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if ((w_reset)||(!o_wb_cyc)||(i_wb_err)||(err_state))
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begin
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wb_pending <= 1'b0;
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wb_outstanding <= 0;
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last_ack <= 1;
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end else case({ (o_wb_stb)&&(!i_wb_stall), i_wb_ack })
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2'b01: begin
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wb_outstanding <= wb_outstanding - 1'b1;
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wb_pending <= (wb_outstanding >= 2);
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last_ack <= (wb_outstanding <= 2);
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end
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2'b10: begin
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wb_outstanding <= wb_outstanding + 1'b1;
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wb_pending <= 1'b1;
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last_ack <= (wb_outstanding == 0);
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end
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default: begin end
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endcase
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assign next_first = r_first + 1'b1;
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assign next_last = r_last + 1'b1;
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assign next_mid = r_mid + 1'b1;
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assign fifo_fill = (r_first - r_last);
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initial fifo_full = 1'b0;
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initial fifo_empty = 1'b1;
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always @(posedge i_clk)
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if (w_reset)
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begin
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fifo_full <= 1'b0;
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fifo_empty <= 1'b1;
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end else case({ (o_axi_rvalid)&&(i_axi_rready),
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(i_axi_arvalid)&&(o_axi_arready) })
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2'b01: begin
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fifo_full <= (next_first[LGFIFO-1:0] == r_last[LGFIFO-1:0])
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&&(next_first[LGFIFO]!=r_last[LGFIFO]);
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fifo_empty <= 1'b0;
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end
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2'b10: begin
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fifo_full <= 1'b0;
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fifo_empty <= 1'b0;
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end
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default: begin end
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endcase
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initial o_axi_arready = 1'b1;
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always @(posedge i_clk)
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if (w_reset)
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o_axi_arready <= 1'b1;
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else if ((o_wb_cyc && i_wb_err) || err_state)
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// On any error, drop the ready flag until it's been flushed
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o_axi_arready <= 1'b0;
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else if ((i_axi_arvalid)&&(o_axi_arready)&&(o_wb_stb)&&(i_wb_stall))
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// On any request where we are already busy, r_stb will get
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// set and we drop arready
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o_axi_arready <= 1'b0;
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else if (!o_axi_arready && o_wb_stb && i_wb_stall)
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// If we've already stalled on o_wb_stb, remain stalled until
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// the bus clears
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o_axi_arready <= 1'b0;
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else if (fifo_full && (!o_axi_rvalid || !i_axi_rready))
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// If the FIFO is full, we must remain not ready until at
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// least one acknowledgment is accepted
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o_axi_arready <= 1'b0;
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else if ( (!o_axi_rvalid || !i_axi_rready)
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&& (i_axi_arvalid && o_axi_arready))
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o_axi_arready <= (next_first[LGFIFO-1:0] != r_last[LGFIFO-1:0])
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||(next_first[LGFIFO]==r_last[LGFIFO]);
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else
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o_axi_arready <= 1'b1;
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initial r_first = 0;
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always @(posedge i_clk)
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if (w_reset)
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r_first <= 0;
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else if ((i_axi_arvalid)&&(o_axi_arready))
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r_first <= r_first + 1'b1;
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initial r_mid = 0;
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always @(posedge i_clk)
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if (w_reset)
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r_mid <= 0;
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else if ((o_wb_cyc)&&((i_wb_ack)||(i_wb_err)))
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r_mid <= r_mid + 1'b1;
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else if ((err_state)&&(r_mid != r_first))
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r_mid <= r_mid + 1'b1;
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initial r_last = 0;
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always @(posedge i_clk)
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if (w_reset)
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r_last <= 0;
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else if ((o_axi_rvalid)&&(i_axi_rready))
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r_last <= r_last + 1'b1;
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always @(posedge i_clk)
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if ((o_wb_cyc)&&((i_wb_ack)||(i_wb_err)))
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dfifo[r_mid[(LGFIFO-1):0]] <= i_wb_data;
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reg [LGFIFO:0] err_loc;
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_err))
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err_loc <= r_mid;
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wire [DW-1:0] read_data;
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assign read_data = dfifo[r_last[LGFIFO-1:0]];
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assign o_axi_rdata = read_data[DW-1:0];
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initial o_axi_rresp = 2'b00;
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always @(posedge i_clk)
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if (w_reset)
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o_axi_rresp <= 0;
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else if ((!o_axi_rvalid)||(i_axi_rready))
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begin
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if ((!err_state)&&((!o_wb_cyc)||(!i_wb_err)))
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o_axi_rresp <= 2'b00;
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else if ((!err_state)&&(o_wb_cyc)&&(i_wb_err))
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begin
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if (o_axi_rvalid)
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o_axi_rresp <= (r_mid == next_last) ? 2'b10 : 2'b00;
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else
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o_axi_rresp <= (r_mid == r_last) ? 2'b10 : 2'b00;
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end else if (err_state)
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begin
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if (next_last == err_loc)
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o_axi_rresp <= 2'b10;
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else if (o_axi_rresp[1])
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o_axi_rresp <= 2'b11;
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end else
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o_axi_rresp <= 0;
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end
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reg err_state;
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initial err_state = 0;
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always @(posedge i_clk)
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if (w_reset)
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err_state <= 0;
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else if (r_first == r_last)
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err_state <= 0;
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else if ((o_wb_cyc)&&(i_wb_err))
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err_state <= 1'b1;
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initial o_axi_rvalid = 1'b0;
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always @(posedge i_clk)
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if (w_reset)
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o_axi_rvalid <= 0;
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else if ((o_wb_cyc)&&((i_wb_ack)||(i_wb_err)))
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o_axi_rvalid <= 1'b1;
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else if ((o_axi_rvalid)&&(i_axi_rready))
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begin
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if (err_state)
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o_axi_rvalid <= (next_last != r_first);
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else
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o_axi_rvalid <= (next_last != r_mid);
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end
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// Make Verilator happy
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// verilator lint_off UNUSED
|
| 309 |
|
|
// verilator lint_on UNUSED
|
| 310 |
|
|
|
| 311 |
|
|
`ifdef FORMAL
|
| 312 |
|
|
reg f_past_valid;
|
| 313 |
|
|
initial f_past_valid = 1'b0;
|
| 314 |
|
|
always @(posedge i_clk)
|
| 315 |
|
|
f_past_valid <= 1'b1;
|
| 316 |
|
|
|
| 317 |
|
|
always @(*)
|
| 318 |
|
|
if (!f_past_valid)
|
| 319 |
|
|
assume(w_reset);
|
| 320 |
|
|
|
| 321 |
|
|
always @(*)
|
| 322 |
|
|
if (err_state)
|
| 323 |
|
|
assert(!o_axi_arready);
|
| 324 |
|
|
|
| 325 |
|
|
always @(*)
|
| 326 |
|
|
if (err_state)
|
| 327 |
|
|
assert((!o_wb_cyc)&&(!o_axi_arready));
|
| 328 |
|
|
|
| 329 |
|
|
always @(*)
|
| 330 |
|
|
if ((fifo_empty)&&(!w_reset))
|
| 331 |
|
|
assert((!fifo_full)&&(r_first == r_last)&&(r_mid == r_last));
|
| 332 |
|
|
|
| 333 |
|
|
always @(*)
|
| 334 |
|
|
if (fifo_full)
|
| 335 |
|
|
assert((!fifo_empty)
|
| 336 |
|
|
&&(r_first[LGFIFO-1:0] == r_last[LGFIFO-1:0])
|
| 337 |
|
|
&&(r_first[LGFIFO] != r_last[LGFIFO]));
|
| 338 |
|
|
|
| 339 |
|
|
always @(*)
|
| 340 |
|
|
assert(fifo_fill <= (1<<LGFIFO));
|
| 341 |
|
|
|
| 342 |
|
|
always @(*)
|
| 343 |
|
|
if (fifo_full)
|
| 344 |
|
|
assert(!o_axi_arready);
|
| 345 |
|
|
always @(*)
|
| 346 |
|
|
assert(fifo_full == (fifo_fill == (1<<LGFIFO)));
|
| 347 |
|
|
always @(*)
|
| 348 |
|
|
if (fifo_fill == (1<<LGFIFO))
|
| 349 |
|
|
assert(!o_axi_arready);
|
| 350 |
|
|
always @(*)
|
| 351 |
|
|
assert(wb_pending == (wb_outstanding != 0));
|
| 352 |
|
|
|
| 353 |
|
|
always @(*)
|
| 354 |
|
|
assert(last_ack == (wb_outstanding <= 1));
|
| 355 |
|
|
|
| 356 |
|
|
|
| 357 |
|
|
assign f_first = r_first;
|
| 358 |
|
|
assign f_mid = r_mid;
|
| 359 |
|
|
assign f_last = r_last;
|
| 360 |
|
|
|
| 361 |
|
|
wire [LGFIFO:0] f_wb_nreqs, f_wb_nacks, f_wb_outstanding;
|
| 362 |
|
|
fwb_master #(
|
| 363 |
|
|
.AW(AW), .DW(DW), .F_LGDEPTH(LGFIFO+1)
|
| 364 |
|
|
) fwb(i_clk, w_reset,
|
| 365 |
|
|
o_wb_cyc, o_wb_stb, 1'b0, o_wb_addr, 32'h0, 4'h0,
|
| 366 |
|
|
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
|
| 367 |
|
|
f_wb_nreqs,f_wb_nacks, f_wb_outstanding);
|
| 368 |
|
|
|
| 369 |
|
|
always @(*)
|
| 370 |
|
|
if (o_wb_cyc)
|
| 371 |
|
|
assert(f_wb_outstanding == wb_outstanding);
|
| 372 |
|
|
|
| 373 |
|
|
always @(*)
|
| 374 |
|
|
if (o_wb_cyc)
|
| 375 |
|
|
assert(wb_outstanding <= (1<<LGFIFO));
|
| 376 |
|
|
|
| 377 |
|
|
wire [LGFIFO:0] wb_fill;
|
| 378 |
|
|
assign wb_fill = r_first - r_mid;
|
| 379 |
|
|
always @(*)
|
| 380 |
|
|
assert(wb_fill <= fifo_fill);
|
| 381 |
|
|
always @(*)
|
| 382 |
|
|
if (o_wb_stb)
|
| 383 |
|
|
assert(wb_outstanding+1+((r_stb)?1:0) == wb_fill);
|
| 384 |
|
|
|
| 385 |
|
|
else if (o_wb_cyc)
|
| 386 |
|
|
assert(wb_outstanding == wb_fill);
|
| 387 |
|
|
|
| 388 |
|
|
always @(*)
|
| 389 |
|
|
if (r_stb)
|
| 390 |
|
|
begin
|
| 391 |
|
|
assert(o_wb_stb);
|
| 392 |
|
|
assert(!o_axi_arready);
|
| 393 |
|
|
end
|
| 394 |
|
|
|
| 395 |
|
|
wire [LGFIFO:0] f_axi_rd_outstanding,
|
| 396 |
|
|
f_axi_wr_outstanding,
|
| 397 |
|
|
f_axi_awr_outstanding;
|
| 398 |
|
|
|
| 399 |
|
|
faxil_slave #(
|
| 400 |
|
|
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
|
| 401 |
|
|
.F_LGDEPTH(LGFIFO+1),
|
| 402 |
|
|
.F_OPT_NO_WRITES(1'b1),
|
| 403 |
|
|
.F_AXI_MAXWAIT(0),
|
| 404 |
|
|
.F_AXI_MAXDELAY(0)
|
| 405 |
|
|
) faxil(i_clk, i_axi_reset_n,
|
| 406 |
|
|
//
|
| 407 |
|
|
// AXI write address channel signals
|
| 408 |
|
|
1'b0, i_axi_araddr, i_axi_arcache, i_axi_arprot, 1'b0,
|
| 409 |
|
|
// AXI write data channel signals
|
| 410 |
|
|
1'b0, 32'h0, 4'h0, 1'b0,
|
| 411 |
|
|
// AXI write response channel signals
|
| 412 |
|
|
2'b00, 1'b0, 1'b0,
|
| 413 |
|
|
// AXI read address channel signals
|
| 414 |
|
|
o_axi_arready, i_axi_araddr, i_axi_arcache, i_axi_arprot,
|
| 415 |
|
|
i_axi_arvalid,
|
| 416 |
|
|
// AXI read data channel signals
|
| 417 |
|
|
o_axi_rresp, o_axi_rvalid, o_axi_rdata, i_axi_rready,
|
| 418 |
|
|
f_axi_rd_outstanding, f_axi_wr_outstanding,
|
| 419 |
|
|
f_axi_awr_outstanding);
|
| 420 |
|
|
|
| 421 |
|
|
always @(*)
|
| 422 |
|
|
assert(f_axi_wr_outstanding == 0);
|
| 423 |
|
|
always @(*)
|
| 424 |
|
|
assert(f_axi_awr_outstanding == 0);
|
| 425 |
|
|
always @(*)
|
| 426 |
|
|
assert(f_axi_rd_outstanding == fifo_fill);
|
| 427 |
|
|
|
| 428 |
|
|
wire [LGFIFO:0] f_mid_minus_err, f_err_minus_last,
|
| 429 |
|
|
f_first_minus_err;
|
| 430 |
|
|
assign f_mid_minus_err = f_mid - err_loc;
|
| 431 |
|
|
assign f_err_minus_last = err_loc - f_last;
|
| 432 |
|
|
assign f_first_minus_err = f_first - err_loc;
|
| 433 |
|
|
always @(*)
|
| 434 |
|
|
if (o_axi_rvalid)
|
| 435 |
|
|
begin
|
| 436 |
|
|
if (!err_state)
|
| 437 |
|
|
assert(!o_axi_rresp[1]);
|
| 438 |
|
|
else if (err_loc == f_last)
|
| 439 |
|
|
assert(o_axi_rresp == 2'b10);
|
| 440 |
|
|
else if (f_err_minus_last < (1<<LGFIFO))
|
| 441 |
|
|
assert(!o_axi_rresp[1]);
|
| 442 |
|
|
else
|
| 443 |
|
|
assert(o_axi_rresp[1]);
|
| 444 |
|
|
end
|
| 445 |
|
|
|
| 446 |
|
|
always @(*)
|
| 447 |
|
|
if (err_state)
|
| 448 |
|
|
assert(o_axi_rvalid == (r_first != r_last));
|
| 449 |
|
|
else
|
| 450 |
|
|
assert(o_axi_rvalid == (r_mid != r_last));
|
| 451 |
|
|
|
| 452 |
|
|
always @(*)
|
| 453 |
|
|
if (err_state)
|
| 454 |
|
|
assert(f_first_minus_err <= (1<<LGFIFO));
|
| 455 |
|
|
|
| 456 |
|
|
always @(*)
|
| 457 |
|
|
if (err_state)
|
| 458 |
|
|
assert(f_first_minus_err != 0);
|
| 459 |
|
|
|
| 460 |
|
|
always @(*)
|
| 461 |
|
|
if (err_state)
|
| 462 |
|
|
assert(f_mid_minus_err <= f_first_minus_err);
|
| 463 |
|
|
|
| 464 |
|
|
always @(*)
|
| 465 |
|
|
if ((f_past_valid)&&(i_axi_reset_n)&&(f_axi_rd_outstanding > 0))
|
| 466 |
|
|
begin
|
| 467 |
|
|
if (err_state)
|
| 468 |
|
|
assert((!o_wb_cyc)&&(f_wb_outstanding == 0));
|
| 469 |
|
|
else if (!o_wb_cyc)
|
| 470 |
|
|
assert((o_axi_rvalid)&&(f_axi_rd_outstanding>0)
|
| 471 |
|
|
&&(wb_fill == 0));
|
| 472 |
|
|
end
|
| 473 |
|
|
|
| 474 |
|
|
// WB covers
|
| 475 |
|
|
always @(*)
|
| 476 |
|
|
cover(o_wb_cyc && o_wb_stb);
|
| 477 |
|
|
|
| 478 |
|
|
always @(*)
|
| 479 |
|
|
if (LGFIFO > 2)
|
| 480 |
|
|
cover(o_wb_cyc && f_wb_outstanding > 2);
|
| 481 |
|
|
|
| 482 |
|
|
always @(posedge i_clk)
|
| 483 |
|
|
cover(o_wb_cyc && i_wb_ack
|
| 484 |
|
|
&& $past(o_wb_cyc && i_wb_ack)
|
| 485 |
|
|
&& $past(o_wb_cyc && i_wb_ack,2));
|
| 486 |
|
|
|
| 487 |
|
|
// AXI covers
|
| 488 |
|
|
always @(*)
|
| 489 |
|
|
cover(o_axi_rvalid && i_axi_rready);
|
| 490 |
|
|
|
| 491 |
|
|
always @(posedge i_clk)
|
| 492 |
|
|
cover(i_axi_arvalid && o_axi_arready
|
| 493 |
|
|
&& $past(i_axi_arvalid && o_axi_arready)
|
| 494 |
|
|
&& $past(i_axi_arvalid && o_axi_arready,2));
|
| 495 |
|
|
|
| 496 |
|
|
always @(posedge i_clk)
|
| 497 |
|
|
cover(o_axi_rvalid && i_axi_rready
|
| 498 |
|
|
&& $past(o_axi_rvalid && i_axi_rready)
|
| 499 |
|
|
&& $past(o_axi_rvalid && i_axi_rready,2));
|
| 500 |
|
|
`endif
|
| 501 |
|
|
endmodule
|
