| 1 |
16 |
dgisselq |
`error This full featured AXI to WB converter does not (yet) work
|
| 2 |
8 |
dgisselq |
////////////////////////////////////////////////////////////////////////////////
|
| 3 |
|
|
//
|
| 4 |
|
|
// Filename: axim2wbsp.v
|
| 5 |
|
|
//
|
| 6 |
|
|
// Project: Pipelined Wishbone to AXI converter
|
| 7 |
|
|
//
|
| 8 |
16 |
dgisselq |
// Purpose: So ... this converter works in the other direction from
|
| 9 |
|
|
// wbm2axisp. This converter takes AXI commands, and organizes
|
| 10 |
|
|
// them into pipelined wishbone commands.
|
| 11 |
8 |
dgisselq |
//
|
| 12 |
|
|
//
|
| 13 |
|
|
// We'll treat AXI as two separate busses: one for writes, another for
|
| 14 |
|
|
// reads, further, we'll insist that the two channels AXI uses for writes
|
| 15 |
|
|
// combine into one channel for our purposes.
|
| 16 |
|
|
//
|
| 17 |
|
|
//
|
| 18 |
|
|
// Creator: Dan Gisselquist, Ph.D.
|
| 19 |
|
|
// Gisselquist Technology, LLC
|
| 20 |
|
|
//
|
| 21 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 22 |
|
|
//
|
| 23 |
16 |
dgisselq |
// Copyright (C) 2016-2019, Gisselquist Technology, LLC
|
| 24 |
8 |
dgisselq |
//
|
| 25 |
16 |
dgisselq |
// This file is part of the pipelined Wishbone to AXI converter project, a
|
| 26 |
|
|
// project that contains multiple bus bridging designs and formal bus property
|
| 27 |
|
|
// sets.
|
| 28 |
8 |
dgisselq |
//
|
| 29 |
16 |
dgisselq |
// The bus bridge designs and property sets are free RTL designs: you can
|
| 30 |
|
|
// redistribute them and/or modify any of them under the terms of the GNU
|
| 31 |
|
|
// Lesser General Public License as published by the Free Software Foundation,
|
| 32 |
|
|
// either version 3 of the License, or (at your option) any later version.
|
| 33 |
8 |
dgisselq |
//
|
| 34 |
16 |
dgisselq |
// The bus bridge designs and property sets are distributed in the hope that
|
| 35 |
|
|
// they will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
| 36 |
|
|
// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 37 |
|
|
// GNU Lesser General Public License for more details.
|
| 38 |
|
|
//
|
| 39 |
|
|
// You should have received a copy of the GNU Lesser General Public License
|
| 40 |
|
|
// along with these designs. (It's in the $(ROOT)/doc directory. Run make
|
| 41 |
|
|
// with no target there if the PDF file isn't present.) If not, see
|
| 42 |
8 |
dgisselq |
// <http://www.gnu.org/licenses/> for a copy.
|
| 43 |
|
|
//
|
| 44 |
16 |
dgisselq |
// License: LGPL, v3, as defined and found on www.gnu.org,
|
| 45 |
|
|
// http://www.gnu.org/licenses/lgpl.html
|
| 46 |
8 |
dgisselq |
//
|
| 47 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 48 |
|
|
//
|
| 49 |
|
|
//
|
| 50 |
16 |
dgisselq |
`default_nettype none
|
| 51 |
|
|
//
|
| 52 |
8 |
dgisselq |
module axim2wbsp( i_clk, i_axi_reset_n,
|
| 53 |
|
|
//
|
| 54 |
|
|
o_axi_awready, // Slave is ready to accept
|
| 55 |
|
|
i_axi_awid, i_axi_awaddr, i_axi_awlen, i_axi_awsize, i_axi_awburst,
|
| 56 |
|
|
i_axi_awlock, i_axi_awcache, i_axi_awprot, i_axi_awqos, i_axi_awvalid,
|
| 57 |
|
|
//
|
| 58 |
|
|
o_axi_wready, i_axi_wdata, i_axi_wstrb, i_axi_wlast, i_axi_wvalid,
|
| 59 |
|
|
//
|
| 60 |
|
|
o_axi_bid, o_axi_bresp, o_axi_bvalid, i_axi_bready,
|
| 61 |
|
|
//
|
| 62 |
|
|
o_axi_arready, // Read address ready
|
| 63 |
|
|
i_axi_arid, // Read ID
|
| 64 |
|
|
i_axi_araddr, // Read address
|
| 65 |
|
|
i_axi_arlen, // Read Burst Length
|
| 66 |
|
|
i_axi_arsize, // Read Burst size
|
| 67 |
|
|
i_axi_arburst, // Read Burst type
|
| 68 |
|
|
i_axi_arlock, // Read lock type
|
| 69 |
|
|
i_axi_arcache, // Read Cache type
|
| 70 |
|
|
i_axi_arprot, // Read Protection type
|
| 71 |
|
|
i_axi_arqos, // Read Protection type
|
| 72 |
|
|
i_axi_arvalid, // Read address valid
|
| 73 |
|
|
//
|
| 74 |
16 |
dgisselq |
o_axi_rid, // Response ID
|
| 75 |
|
|
o_axi_rresp, // Read response
|
| 76 |
|
|
o_axi_rvalid, // Read reponse valid
|
| 77 |
|
|
o_axi_rdata, // Read data
|
| 78 |
|
|
o_axi_rlast, // Read last
|
| 79 |
|
|
i_axi_rready, // Read Response ready
|
| 80 |
8 |
dgisselq |
// Wishbone interface
|
| 81 |
|
|
o_reset, o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
|
| 82 |
|
|
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err);
|
| 83 |
|
|
//
|
| 84 |
16 |
dgisselq |
parameter C_AXI_ID_WIDTH = 2; // The AXI id width used for R&W
|
| 85 |
8 |
dgisselq |
// This is an int between 1-16
|
| 86 |
|
|
parameter C_AXI_DATA_WIDTH = 32;// Width of the AXI R&W data
|
| 87 |
|
|
parameter C_AXI_ADDR_WIDTH = 28; // AXI Address width
|
| 88 |
|
|
localparam DW = C_AXI_DATA_WIDTH;
|
| 89 |
|
|
localparam AW = (C_AXI_DATA_WIDTH== 8) ? (C_AXI_ADDR_WIDTH)
|
| 90 |
|
|
:((C_AXI_DATA_WIDTH== 16) ? (C_AXI_ADDR_WIDTH-1)
|
| 91 |
|
|
:((C_AXI_DATA_WIDTH== 32) ? (C_AXI_ADDR_WIDTH-2)
|
| 92 |
|
|
:((C_AXI_DATA_WIDTH== 64) ? (C_AXI_ADDR_WIDTH-3)
|
| 93 |
|
|
:((C_AXI_DATA_WIDTH==128) ? (C_AXI_ADDR_WIDTH-4)
|
| 94 |
|
|
:(C_AXI_ADDR_WIDTH-5)))));
|
| 95 |
16 |
dgisselq |
parameter LGFIFO = 4;
|
| 96 |
|
|
parameter [0:0] F_STRICT_ORDER = 0;
|
| 97 |
|
|
parameter [0:0] F_CONSECUTIVE_IDS = 0;
|
| 98 |
|
|
parameter [0:0] F_OPT_BURSTS = 1'b0;
|
| 99 |
|
|
parameter [0:0] F_OPT_CLK2FFLOGIC = 1'b0;
|
| 100 |
|
|
parameter F_MAXSTALL = 3;
|
| 101 |
|
|
parameter F_MAXDELAY = 3;
|
| 102 |
|
|
parameter [0:0] OPT_READONLY = 1'b1;
|
| 103 |
|
|
parameter [0:0] OPT_WRITEONLY = 1'b0;
|
| 104 |
|
|
parameter [7:0] OPT_MAXBURST = 8'h3;
|
| 105 |
8 |
dgisselq |
//
|
| 106 |
|
|
input wire i_clk; // System clock
|
| 107 |
|
|
input wire i_axi_reset_n;
|
| 108 |
|
|
|
| 109 |
|
|
// AXI write address channel signals
|
| 110 |
|
|
output wire o_axi_awready; // Slave is ready to accept
|
| 111 |
|
|
input wire [C_AXI_ID_WIDTH-1:0] i_axi_awid; // Write ID
|
| 112 |
|
|
input wire [C_AXI_ADDR_WIDTH-1:0] i_axi_awaddr; // Write address
|
| 113 |
|
|
input wire [7:0] i_axi_awlen; // Write Burst Length
|
| 114 |
|
|
input wire [2:0] i_axi_awsize; // Write Burst size
|
| 115 |
|
|
input wire [1:0] i_axi_awburst; // Write Burst type
|
| 116 |
|
|
input wire [0:0] i_axi_awlock; // Write lock type
|
| 117 |
|
|
input wire [3:0] i_axi_awcache; // Write Cache type
|
| 118 |
|
|
input wire [2:0] i_axi_awprot; // Write Protection type
|
| 119 |
|
|
input wire [3:0] i_axi_awqos; // Write Quality of Svc
|
| 120 |
|
|
input wire i_axi_awvalid; // Write address valid
|
| 121 |
16 |
dgisselq |
|
| 122 |
8 |
dgisselq |
// AXI write data channel signals
|
| 123 |
|
|
output wire o_axi_wready; // Write data ready
|
| 124 |
|
|
input wire [C_AXI_DATA_WIDTH-1:0] i_axi_wdata; // Write data
|
| 125 |
|
|
input wire [C_AXI_DATA_WIDTH/8-1:0] i_axi_wstrb; // Write strobes
|
| 126 |
16 |
dgisselq |
input wire i_axi_wlast; // Last write transaction
|
| 127 |
8 |
dgisselq |
input wire i_axi_wvalid; // Write valid
|
| 128 |
16 |
dgisselq |
|
| 129 |
8 |
dgisselq |
// AXI write response channel signals
|
| 130 |
|
|
output wire [C_AXI_ID_WIDTH-1:0] o_axi_bid; // Response ID
|
| 131 |
|
|
output wire [1:0] o_axi_bresp; // Write response
|
| 132 |
|
|
output wire o_axi_bvalid; // Write reponse valid
|
| 133 |
|
|
input wire i_axi_bready; // Response ready
|
| 134 |
16 |
dgisselq |
|
| 135 |
8 |
dgisselq |
// AXI read address channel signals
|
| 136 |
|
|
output wire o_axi_arready; // Read address ready
|
| 137 |
|
|
input wire [C_AXI_ID_WIDTH-1:0] i_axi_arid; // Read ID
|
| 138 |
|
|
input wire [C_AXI_ADDR_WIDTH-1:0] i_axi_araddr; // Read address
|
| 139 |
|
|
input wire [7:0] i_axi_arlen; // Read Burst Length
|
| 140 |
|
|
input wire [2:0] i_axi_arsize; // Read Burst size
|
| 141 |
|
|
input wire [1:0] i_axi_arburst; // Read Burst type
|
| 142 |
|
|
input wire [0:0] i_axi_arlock; // Read lock type
|
| 143 |
|
|
input wire [3:0] i_axi_arcache; // Read Cache type
|
| 144 |
|
|
input wire [2:0] i_axi_arprot; // Read Protection type
|
| 145 |
|
|
input wire [3:0] i_axi_arqos; // Read Protection type
|
| 146 |
|
|
input wire i_axi_arvalid; // Read address valid
|
| 147 |
16 |
dgisselq |
|
| 148 |
|
|
// AXI read data channel signals
|
| 149 |
8 |
dgisselq |
output wire [C_AXI_ID_WIDTH-1:0] o_axi_rid; // Response ID
|
| 150 |
|
|
output wire [1:0] o_axi_rresp; // Read response
|
| 151 |
|
|
output wire o_axi_rvalid; // Read reponse valid
|
| 152 |
|
|
output wire [C_AXI_DATA_WIDTH-1:0] o_axi_rdata; // Read data
|
| 153 |
|
|
output wire o_axi_rlast; // Read last
|
| 154 |
|
|
input wire i_axi_rready; // Read Response ready
|
| 155 |
|
|
|
| 156 |
|
|
// We'll share the clock and the reset
|
| 157 |
|
|
output wire o_reset;
|
| 158 |
|
|
output wire o_wb_cyc;
|
| 159 |
|
|
output wire o_wb_stb;
|
| 160 |
|
|
output wire o_wb_we;
|
| 161 |
|
|
output wire [(AW-1):0] o_wb_addr;
|
| 162 |
|
|
output wire [(C_AXI_DATA_WIDTH-1):0] o_wb_data;
|
| 163 |
|
|
output wire [(C_AXI_DATA_WIDTH/8-1):0] o_wb_sel;
|
| 164 |
|
|
input wire i_wb_ack;
|
| 165 |
|
|
input wire i_wb_stall;
|
| 166 |
|
|
input wire [(C_AXI_DATA_WIDTH-1):0] i_wb_data;
|
| 167 |
|
|
input wire i_wb_err;
|
| 168 |
|
|
|
| 169 |
|
|
|
| 170 |
|
|
//
|
| 171 |
|
|
//
|
| 172 |
|
|
//
|
| 173 |
|
|
|
| 174 |
|
|
|
| 175 |
|
|
wire [(AW-1):0] w_wb_addr, r_wb_addr;
|
| 176 |
|
|
wire [(C_AXI_DATA_WIDTH-1):0] w_wb_data;
|
| 177 |
|
|
wire [(C_AXI_DATA_WIDTH/8-1):0] w_wb_sel;
|
| 178 |
|
|
wire r_wb_err, r_wb_cyc, r_wb_stb, r_wb_stall, r_wb_ack;
|
| 179 |
|
|
wire w_wb_err, w_wb_cyc, w_wb_stb, w_wb_stall, w_wb_ack;
|
| 180 |
|
|
|
| 181 |
|
|
// verilator lint_off UNUSED
|
| 182 |
|
|
wire r_wb_we, w_wb_we;
|
| 183 |
|
|
|
| 184 |
|
|
assign r_wb_we = 1'b0;
|
| 185 |
|
|
assign w_wb_we = 1'b1;
|
| 186 |
|
|
// verilator lint_on UNUSED
|
| 187 |
|
|
|
| 188 |
16 |
dgisselq |
`ifdef FORMAL
|
| 189 |
|
|
wire [(LGFIFO-1):0] f_wr_fifo_ahead, f_wr_fifo_dhead,
|
| 190 |
|
|
f_wr_fifo_neck, f_wr_fifo_torso,
|
| 191 |
|
|
f_wr_fifo_tail,
|
| 192 |
|
|
f_rd_fifo_head, f_rd_fifo_neck,
|
| 193 |
|
|
f_rd_fifo_torso, f_rd_fifo_tail;
|
| 194 |
|
|
wire [(LGFIFO-1):0] f_wb_nreqs, f_wb_nacks,
|
| 195 |
|
|
f_wb_outstanding;
|
| 196 |
|
|
wire [(LGFIFO-1):0] f_wb_wr_nreqs, f_wb_wr_nacks,
|
| 197 |
|
|
f_wb_wr_outstanding;
|
| 198 |
|
|
wire [(LGFIFO-1):0] f_wb_rd_nreqs, f_wb_rd_nacks,
|
| 199 |
|
|
f_wb_rd_outstanding;
|
| 200 |
|
|
`endif
|
| 201 |
|
|
|
| 202 |
|
|
generate if (!OPT_READONLY)
|
| 203 |
|
|
begin : AXI_WR
|
| 204 |
8 |
dgisselq |
aximwr2wbsp #(
|
| 205 |
|
|
.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
|
| 206 |
|
|
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
|
| 207 |
16 |
dgisselq |
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), .AW(AW),
|
| 208 |
|
|
.LGFIFO(LGFIFO))
|
| 209 |
8 |
dgisselq |
axi_write_decoder(
|
| 210 |
|
|
.i_axi_clk(i_clk), .i_axi_reset_n(i_axi_reset_n),
|
| 211 |
|
|
//
|
| 212 |
|
|
.o_axi_awready(o_axi_awready),
|
| 213 |
|
|
.i_axi_awid( i_axi_awid),
|
| 214 |
|
|
.i_axi_awaddr( i_axi_awaddr),
|
| 215 |
|
|
.i_axi_awlen( i_axi_awlen),
|
| 216 |
|
|
.i_axi_awsize( i_axi_awsize),
|
| 217 |
|
|
.i_axi_awburst(i_axi_awburst),
|
| 218 |
|
|
.i_axi_awlock( i_axi_awlock),
|
| 219 |
|
|
.i_axi_awcache(i_axi_awcache),
|
| 220 |
|
|
.i_axi_awprot( i_axi_awprot),
|
| 221 |
|
|
.i_axi_awqos( i_axi_awqos),
|
| 222 |
|
|
.i_axi_awvalid(i_axi_awvalid),
|
| 223 |
|
|
//
|
| 224 |
|
|
.o_axi_wready( o_axi_wready),
|
| 225 |
|
|
.i_axi_wdata( i_axi_wdata),
|
| 226 |
|
|
.i_axi_wstrb( i_axi_wstrb),
|
| 227 |
|
|
.i_axi_wlast( i_axi_wlast),
|
| 228 |
|
|
.i_axi_wvalid( i_axi_wvalid),
|
| 229 |
|
|
//
|
| 230 |
|
|
.o_axi_bid(o_axi_bid),
|
| 231 |
|
|
.o_axi_bresp(o_axi_bresp),
|
| 232 |
|
|
.o_axi_bvalid(o_axi_bvalid),
|
| 233 |
|
|
.i_axi_bready(i_axi_bready),
|
| 234 |
|
|
//
|
| 235 |
|
|
.o_wb_cyc( w_wb_cyc),
|
| 236 |
|
|
.o_wb_stb( w_wb_stb),
|
| 237 |
|
|
.o_wb_addr( w_wb_addr),
|
| 238 |
|
|
.o_wb_data( w_wb_data),
|
| 239 |
|
|
.o_wb_sel( w_wb_sel),
|
| 240 |
|
|
.i_wb_ack( w_wb_ack),
|
| 241 |
|
|
.i_wb_stall(w_wb_stall),
|
| 242 |
16 |
dgisselq |
.i_wb_err( w_wb_err)
|
| 243 |
|
|
`ifdef FORMAL
|
| 244 |
|
|
,
|
| 245 |
|
|
.f_fifo_ahead(f_wr_fifo_ahead),
|
| 246 |
|
|
.f_fifo_dhead(f_wr_fifo_dhead),
|
| 247 |
|
|
.f_fifo_neck( f_wr_fifo_neck),
|
| 248 |
|
|
.f_fifo_torso(f_wr_fifo_torso),
|
| 249 |
|
|
.f_fifo_tail( f_wr_fifo_tail)
|
| 250 |
|
|
`endif
|
| 251 |
|
|
);
|
| 252 |
|
|
end else begin
|
| 253 |
|
|
assign w_wb_cyc = 0;
|
| 254 |
|
|
assign w_wb_stb = 0;
|
| 255 |
|
|
assign w_wb_addr = 0;
|
| 256 |
|
|
assign w_wb_data = 0;
|
| 257 |
|
|
assign w_wb_sel = 0;
|
| 258 |
|
|
assign o_axi_awready = 0;
|
| 259 |
|
|
assign o_axi_wready = 0;
|
| 260 |
|
|
assign o_axi_bvalid = (i_axi_wvalid)&&(i_axi_wlast);
|
| 261 |
|
|
assign o_axi_bresp = 2'b11;
|
| 262 |
|
|
assign o_axi_bid = i_axi_awid;
|
| 263 |
|
|
`ifdef FORMAL
|
| 264 |
|
|
assign f_wr_fifo_ahead = 0;
|
| 265 |
|
|
assign f_wr_fifo_dhead = 0;
|
| 266 |
|
|
assign f_wr_fifo_neck = 0;
|
| 267 |
|
|
assign f_wr_fifo_torso = 0;
|
| 268 |
|
|
assign f_wr_fifo_tail = 0;
|
| 269 |
|
|
`endif
|
| 270 |
|
|
end endgenerate
|
| 271 |
8 |
dgisselq |
assign w_wb_we = 1'b1;
|
| 272 |
|
|
|
| 273 |
16 |
dgisselq |
generate if (!OPT_WRITEONLY)
|
| 274 |
|
|
begin : AXI_RD
|
| 275 |
8 |
dgisselq |
aximrd2wbsp #(
|
| 276 |
|
|
.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
|
| 277 |
|
|
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
|
| 278 |
16 |
dgisselq |
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), .AW(AW),
|
| 279 |
|
|
.LGFIFO(LGFIFO))
|
| 280 |
8 |
dgisselq |
axi_read_decoder(
|
| 281 |
|
|
.i_axi_clk(i_clk), .i_axi_reset_n(i_axi_reset_n),
|
| 282 |
|
|
//
|
| 283 |
|
|
.o_axi_arready(o_axi_arready),
|
| 284 |
|
|
.i_axi_arid( i_axi_arid),
|
| 285 |
|
|
.i_axi_araddr( i_axi_araddr),
|
| 286 |
|
|
.i_axi_arlen( i_axi_arlen),
|
| 287 |
|
|
.i_axi_arsize( i_axi_arsize),
|
| 288 |
|
|
.i_axi_arburst(i_axi_arburst),
|
| 289 |
|
|
.i_axi_arlock( i_axi_arlock),
|
| 290 |
|
|
.i_axi_arcache(i_axi_arcache),
|
| 291 |
|
|
.i_axi_arprot( i_axi_arprot),
|
| 292 |
|
|
.i_axi_arqos( i_axi_arqos),
|
| 293 |
|
|
.i_axi_arvalid(i_axi_arvalid),
|
| 294 |
|
|
//
|
| 295 |
|
|
.o_axi_rid( o_axi_rid),
|
| 296 |
|
|
.o_axi_rresp( o_axi_rresp),
|
| 297 |
|
|
.o_axi_rvalid(o_axi_rvalid),
|
| 298 |
|
|
.o_axi_rdata( o_axi_rdata),
|
| 299 |
|
|
.o_axi_rlast( o_axi_rlast),
|
| 300 |
|
|
.i_axi_rready(i_axi_rready),
|
| 301 |
|
|
//
|
| 302 |
|
|
.o_wb_cyc( r_wb_cyc),
|
| 303 |
|
|
.o_wb_stb( r_wb_stb),
|
| 304 |
|
|
.o_wb_addr( r_wb_addr),
|
| 305 |
|
|
.i_wb_ack( r_wb_ack),
|
| 306 |
|
|
.i_wb_stall(r_wb_stall),
|
| 307 |
|
|
.i_wb_data( i_wb_data),
|
| 308 |
16 |
dgisselq |
.i_wb_err( r_wb_err)
|
| 309 |
|
|
`ifdef FORMAL
|
| 310 |
|
|
,
|
| 311 |
|
|
.f_fifo_head(f_rd_fifo_head),
|
| 312 |
|
|
.f_fifo_neck(f_rd_fifo_neck),
|
| 313 |
|
|
.f_fifo_torso(f_rd_fifo_torso),
|
| 314 |
|
|
.f_fifo_tail(f_rd_fifo_tail)
|
| 315 |
|
|
`endif
|
| 316 |
|
|
);
|
| 317 |
|
|
end else begin
|
| 318 |
|
|
assign r_wb_cyc = 0;
|
| 319 |
|
|
assign r_wb_stb = 0;
|
| 320 |
|
|
assign r_wb_addr = 0;
|
| 321 |
|
|
//
|
| 322 |
|
|
assign o_axi_arready = 1'b1;
|
| 323 |
|
|
assign o_axi_rvalid = (i_axi_arvalid)&&(o_axi_arready);
|
| 324 |
|
|
assign o_axi_rid = (i_axi_arid);
|
| 325 |
|
|
assign o_axi_rvalid = (i_axi_arvalid);
|
| 326 |
|
|
assign o_axi_rlast = (i_axi_arvalid);
|
| 327 |
|
|
assign o_axi_rresp = (i_axi_arvalid) ? 2'b11 : 2'b00;
|
| 328 |
|
|
assign o_axi_rdata = 0;
|
| 329 |
|
|
`ifdef FORMAL
|
| 330 |
|
|
assign f_rd_fifo_head = 0;
|
| 331 |
|
|
assign f_rd_fifo_neck = 0;
|
| 332 |
|
|
assign f_rd_fifo_torso = 0;
|
| 333 |
|
|
assign f_rd_fifo_tail = 0;
|
| 334 |
|
|
`endif
|
| 335 |
|
|
end endgenerate
|
| 336 |
8 |
dgisselq |
|
| 337 |
16 |
dgisselq |
generate if (OPT_READONLY)
|
| 338 |
|
|
begin : ARB_RD
|
| 339 |
|
|
assign o_wb_cyc = r_wb_cyc;
|
| 340 |
|
|
assign o_wb_stb = r_wb_stb;
|
| 341 |
|
|
assign o_wb_we = 1'b0;
|
| 342 |
|
|
assign o_wb_addr = r_wb_addr;
|
| 343 |
|
|
assign o_wb_data = 32'h0;
|
| 344 |
|
|
assign o_wb_sel = 0;
|
| 345 |
|
|
assign r_wb_ack = i_wb_ack;
|
| 346 |
|
|
assign r_wb_stall= i_wb_stall;
|
| 347 |
|
|
assign r_wb_ack = i_wb_ack;
|
| 348 |
|
|
assign r_wb_err = i_wb_err;
|
| 349 |
|
|
|
| 350 |
8 |
dgisselq |
`ifdef FORMAL
|
| 351 |
16 |
dgisselq |
fwb_master #(.DW(DW), .AW(AW),
|
| 352 |
|
|
.F_LGDEPTH(LGFIFO),
|
| 353 |
|
|
.F_MAX_STALL(F_MAXSTALL),
|
| 354 |
|
|
.F_MAX_ACK_DELAY(F_MAXDELAY),
|
| 355 |
|
|
.F_OPT_CLK2FFLOGIC(F_OPT_CLK2FFLOGIC))
|
| 356 |
|
|
f_wb(i_clk, !i_axi_reset_n,
|
| 357 |
|
|
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
|
| 358 |
|
|
o_wb_sel,
|
| 359 |
|
|
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
|
| 360 |
|
|
f_wb_nreqs, f_wb_nacks, f_wb_outstanding);
|
| 361 |
|
|
|
| 362 |
|
|
assign f_wb_rd_nreqs = f_wb_nreqs;
|
| 363 |
|
|
assign f_wb_rd_nacks = f_wb_nacks;
|
| 364 |
|
|
assign f_wb_rd_outstanding = f_wb_outstanding;
|
| 365 |
8 |
dgisselq |
`endif
|
| 366 |
16 |
dgisselq |
end else if (OPT_WRITEONLY)
|
| 367 |
|
|
begin : ARB_WR
|
| 368 |
|
|
assign o_wb_cyc = w_wb_cyc;
|
| 369 |
|
|
assign o_wb_stb = w_wb_stb;
|
| 370 |
|
|
assign o_wb_we = 1'b1;
|
| 371 |
|
|
assign o_wb_addr = w_wb_addr;
|
| 372 |
|
|
assign o_wb_data = w_wb_data;
|
| 373 |
|
|
assign o_wb_sel = w_wb_sel;
|
| 374 |
|
|
assign w_wb_ack = i_wb_ack;
|
| 375 |
|
|
assign w_wb_stall= i_wb_stall;
|
| 376 |
|
|
assign w_wb_ack = i_wb_ack;
|
| 377 |
|
|
assign w_wb_err = i_wb_err;
|
| 378 |
8 |
dgisselq |
|
| 379 |
16 |
dgisselq |
`ifdef FORMAL
|
| 380 |
|
|
fwb_master #(.DW(DW), .AW(AW),
|
| 381 |
|
|
.F_LGDEPTH(LGFIFO),
|
| 382 |
|
|
.F_MAX_STALL(F_MAXSTALL),
|
| 383 |
|
|
.F_MAX_ACK_DELAY(F_MAXDELAY))
|
| 384 |
|
|
f_wb(i_clk, !i_axi_reset_n,
|
| 385 |
|
|
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
|
| 386 |
|
|
o_wb_sel,
|
| 387 |
|
|
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
|
| 388 |
|
|
f_wb_nreqs, f_wb_nacks, f_wb_outstanding);
|
| 389 |
|
|
|
| 390 |
|
|
assign f_wb_wr_nreqs = f_wb_nreqs;
|
| 391 |
|
|
assign f_wb_wr_nacks = f_wb_nacks;
|
| 392 |
|
|
assign f_wb_wr_outstanding = f_wb_outstanding;
|
| 393 |
|
|
`endif
|
| 394 |
|
|
end else begin : ARB_WB
|
| 395 |
|
|
wbarbiter #(.DW(DW), .AW(AW),
|
| 396 |
|
|
.F_LGDEPTH(LGFIFO),
|
| 397 |
|
|
.F_MAX_STALL(F_MAXSTALL),
|
| 398 |
|
|
.F_OPT_CLK2FFLOGIC(F_OPT_CLK2FFLOGIC),
|
| 399 |
|
|
.F_MAX_ACK_DELAY(F_MAXDELAY))
|
| 400 |
|
|
readorwrite(i_clk, !i_axi_reset_n,
|
| 401 |
|
|
r_wb_cyc, r_wb_stb, 1'b0, r_wb_addr, w_wb_data, w_wb_sel,
|
| 402 |
|
|
r_wb_ack, r_wb_stall, r_wb_err,
|
| 403 |
|
|
w_wb_cyc, w_wb_stb, 1'b1, w_wb_addr, w_wb_data, w_wb_sel,
|
| 404 |
|
|
w_wb_ack, w_wb_stall, w_wb_err,
|
| 405 |
|
|
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
|
| 406 |
|
|
i_wb_ack, i_wb_stall, i_wb_err
|
| 407 |
|
|
`ifdef FORMAL
|
| 408 |
|
|
,
|
| 409 |
|
|
f_wb_rd_nreqs, f_wb_rd_nacks, f_wb_rd_outstanding,
|
| 410 |
|
|
f_wb_wr_nreqs, f_wb_wr_nacks, f_wb_wr_outstanding,
|
| 411 |
|
|
f_wb_nreqs, f_wb_nacks, f_wb_outstanding
|
| 412 |
|
|
`endif
|
| 413 |
|
|
);
|
| 414 |
|
|
end endgenerate
|
| 415 |
|
|
|
| 416 |
8 |
dgisselq |
assign o_reset = (i_axi_reset_n == 1'b0);
|
| 417 |
|
|
|
| 418 |
|
|
`ifdef FORMAL
|
| 419 |
|
|
|
| 420 |
|
|
`ifdef AXIM2WBSP
|
| 421 |
16 |
dgisselq |
generate if (F_OPT_CLK2FFLOGIC)
|
| 422 |
|
|
begin
|
| 423 |
|
|
reg f_last_clk;
|
| 424 |
8 |
dgisselq |
|
| 425 |
16 |
dgisselq |
initial f_last_clk = 0;
|
| 426 |
|
|
always @($global_clock)
|
| 427 |
|
|
begin
|
| 428 |
|
|
assume(i_clk == f_last_clk);
|
| 429 |
|
|
f_last_clk <= !f_last_clk;
|
| 430 |
|
|
|
| 431 |
|
|
if ((f_past_valid)&&(!$rose(i_clk)))
|
| 432 |
|
|
assume($stable(i_axi_reset_n));
|
| 433 |
|
|
end
|
| 434 |
|
|
end endgenerate
|
| 435 |
8 |
dgisselq |
`else
|
| 436 |
|
|
`endif
|
| 437 |
|
|
|
| 438 |
|
|
reg f_past_valid;
|
| 439 |
|
|
|
| 440 |
|
|
initial f_past_valid = 1'b0;
|
| 441 |
|
|
always @(posedge i_clk)
|
| 442 |
|
|
f_past_valid = 1'b1;
|
| 443 |
|
|
|
| 444 |
16 |
dgisselq |
initial assume(!i_axi_reset_n);
|
| 445 |
|
|
always @(*)
|
| 446 |
|
|
if (!f_past_valid)
|
| 447 |
|
|
assume(!i_axi_reset_n);
|
| 448 |
|
|
|
| 449 |
|
|
generate if (F_OPT_CLK2FFLOGIC)
|
| 450 |
|
|
begin
|
| 451 |
|
|
|
| 452 |
|
|
always @($global_clock)
|
| 453 |
|
|
if ((f_past_valid)&&(!$rose(i_clk)))
|
| 454 |
|
|
assert($stable(i_axi_reset_n));
|
| 455 |
|
|
end endgenerate
|
| 456 |
|
|
|
| 457 |
8 |
dgisselq |
wire [(C_AXI_ID_WIDTH-1):0] f_axi_rd_outstanding,
|
| 458 |
|
|
f_axi_wr_outstanding,
|
| 459 |
|
|
f_axi_awr_outstanding;
|
| 460 |
|
|
wire [((1<<C_AXI_ID_WIDTH)-1):0] f_axi_rd_id_outstanding,
|
| 461 |
|
|
f_axi_awr_id_outstanding,
|
| 462 |
|
|
f_axi_wr_id_outstanding;
|
| 463 |
16 |
dgisselq |
wire [8:0] f_axi_wr_pending,
|
| 464 |
|
|
f_axi_rd_count,
|
| 465 |
|
|
f_axi_wr_count;
|
| 466 |
8 |
dgisselq |
|
| 467 |
16 |
dgisselq |
/*
|
| 468 |
|
|
generate if (!OPT_READONLY)
|
| 469 |
|
|
begin : F_WB_WRITE
|
| 470 |
8 |
dgisselq |
fwb_slave #(.DW(DW), .AW(AW),
|
| 471 |
|
|
.F_MAX_STALL(0),
|
| 472 |
|
|
.F_MAX_ACK_DELAY(0),
|
| 473 |
|
|
.F_LGDEPTH(C_AXI_ID_WIDTH),
|
| 474 |
|
|
.F_OPT_RMW_BUS_OPTION(1),
|
| 475 |
|
|
.F_OPT_DISCONTINUOUS(1))
|
| 476 |
|
|
f_wb_wr(i_clk, !i_axi_reset_n,
|
| 477 |
|
|
w_wb_cyc, w_wb_stb, w_wb_we, w_wb_addr, w_wb_data,
|
| 478 |
|
|
w_wb_sel,
|
| 479 |
|
|
w_wb_ack, w_wb_stall, i_wb_data, w_wb_err,
|
| 480 |
|
|
f_wb_wr_nreqs, f_wb_wr_nacks, f_wb_wr_outstanding);
|
| 481 |
16 |
dgisselq |
end else begin
|
| 482 |
|
|
assign f_wb_wr_nreqs = 0;
|
| 483 |
|
|
assign f_wb_wr_nacks = 0;
|
| 484 |
|
|
assign f_wb_wr_outstanding = 0;
|
| 485 |
|
|
end endgenerate
|
| 486 |
|
|
*/
|
| 487 |
8 |
dgisselq |
|
| 488 |
16 |
dgisselq |
/*
|
| 489 |
|
|
generate if (!OPT_WRITEONLY)
|
| 490 |
|
|
begin : F_WB_READ
|
| 491 |
8 |
dgisselq |
fwb_slave #(.DW(DW), .AW(AW),
|
| 492 |
|
|
.F_MAX_STALL(0),
|
| 493 |
|
|
.F_MAX_ACK_DELAY(0),
|
| 494 |
|
|
.F_LGDEPTH(C_AXI_ID_WIDTH),
|
| 495 |
|
|
.F_OPT_RMW_BUS_OPTION(1),
|
| 496 |
|
|
.F_OPT_DISCONTINUOUS(1))
|
| 497 |
|
|
f_wb_rd(i_clk, !i_axi_reset_n,
|
| 498 |
|
|
r_wb_cyc, r_wb_stb, r_wb_we, r_wb_addr, w_wb_data, w_wb_sel,
|
| 499 |
|
|
r_wb_ack, r_wb_stall, i_wb_data, r_wb_err,
|
| 500 |
|
|
f_wb_rd_nreqs, f_wb_rd_nacks, f_wb_rd_outstanding);
|
| 501 |
16 |
dgisselq |
end else begin
|
| 502 |
|
|
assign f_wb_rd_nreqs = 0;
|
| 503 |
|
|
assign f_wb_rd_nacks = 0;
|
| 504 |
|
|
assign f_wb_rd_outstanding = 0;
|
| 505 |
|
|
end endgenerate
|
| 506 |
|
|
*/
|
| 507 |
8 |
dgisselq |
|
| 508 |
16 |
dgisselq |
/*
|
| 509 |
8 |
dgisselq |
fwb_master #(.DW(DW), .AW(AW),
|
| 510 |
16 |
dgisselq |
.F_MAX_STALL(F_MAXSTALL),
|
| 511 |
|
|
.F_MAX_ACK_DELAY(F_MAXDELAY),
|
| 512 |
8 |
dgisselq |
.F_LGDEPTH(C_AXI_ID_WIDTH))
|
| 513 |
|
|
f_wb(i_clk, !i_axi_reset_n,
|
| 514 |
|
|
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
|
| 515 |
|
|
o_wb_sel,
|
| 516 |
|
|
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
|
| 517 |
|
|
f_wb_nreqs, f_wb_nacks, f_wb_outstanding);
|
| 518 |
16 |
dgisselq |
*/
|
| 519 |
8 |
dgisselq |
|
| 520 |
|
|
faxi_slave #(
|
| 521 |
|
|
.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
|
| 522 |
|
|
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
|
| 523 |
|
|
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
|
| 524 |
|
|
.F_AXI_MAXSTALL(0),
|
| 525 |
16 |
dgisselq |
.F_AXI_MAXDELAY(0),
|
| 526 |
|
|
.F_AXI_MAXBURST(OPT_MAXBURST),
|
| 527 |
|
|
.F_OPT_CLK2FFLOGIC(F_OPT_CLK2FFLOGIC))
|
| 528 |
8 |
dgisselq |
f_axi(.i_clk(i_clk), .i_axi_reset_n(i_axi_reset_n),
|
| 529 |
|
|
// AXI write address channnel
|
| 530 |
|
|
.i_axi_awready(o_axi_awready),
|
| 531 |
|
|
.i_axi_awid( i_axi_awid),
|
| 532 |
|
|
.i_axi_awaddr( i_axi_awaddr),
|
| 533 |
|
|
.i_axi_awlen( i_axi_awlen),
|
| 534 |
|
|
.i_axi_awsize( i_axi_awsize),
|
| 535 |
|
|
.i_axi_awburst(i_axi_awburst),
|
| 536 |
|
|
.i_axi_awlock( i_axi_awlock),
|
| 537 |
|
|
.i_axi_awcache(i_axi_awcache),
|
| 538 |
|
|
.i_axi_awprot( i_axi_awprot),
|
| 539 |
|
|
.i_axi_awqos( i_axi_awqos),
|
| 540 |
|
|
.i_axi_awvalid(i_axi_awvalid),
|
| 541 |
|
|
// AXI write data channel
|
| 542 |
|
|
.i_axi_wready( o_axi_wready),
|
| 543 |
|
|
.i_axi_wdata( i_axi_wdata),
|
| 544 |
|
|
.i_axi_wstrb( i_axi_wstrb),
|
| 545 |
|
|
.i_axi_wlast( i_axi_wlast),
|
| 546 |
|
|
.i_axi_wvalid( i_axi_wvalid),
|
| 547 |
|
|
// AXI write acknowledgement channel
|
| 548 |
16 |
dgisselq |
.i_axi_bid( o_axi_bid),
|
| 549 |
|
|
.i_axi_bresp( o_axi_bresp),
|
| 550 |
|
|
.i_axi_bvalid(o_axi_bvalid),
|
| 551 |
|
|
.i_axi_bready(i_axi_bready),
|
| 552 |
8 |
dgisselq |
// AXI read address channel
|
| 553 |
16 |
dgisselq |
.i_axi_arready(o_axi_arready),
|
| 554 |
|
|
.i_axi_arid( i_axi_arid),
|
| 555 |
|
|
.i_axi_araddr( i_axi_araddr),
|
| 556 |
|
|
.i_axi_arlen( i_axi_arlen),
|
| 557 |
|
|
.i_axi_arsize( i_axi_arsize),
|
| 558 |
|
|
.i_axi_arburst(i_axi_arburst),
|
| 559 |
|
|
.i_axi_arlock( i_axi_arlock),
|
| 560 |
|
|
.i_axi_arcache(i_axi_arcache),
|
| 561 |
|
|
.i_axi_arprot( i_axi_arprot),
|
| 562 |
|
|
.i_axi_arqos( i_axi_arqos),
|
| 563 |
|
|
.i_axi_arvalid(i_axi_arvalid),
|
| 564 |
8 |
dgisselq |
// AXI read data return
|
| 565 |
16 |
dgisselq |
.i_axi_rid( o_axi_rid),
|
| 566 |
|
|
.i_axi_rresp( o_axi_rresp),
|
| 567 |
|
|
.i_axi_rvalid( o_axi_rvalid),
|
| 568 |
|
|
.i_axi_rdata( o_axi_rdata),
|
| 569 |
|
|
.i_axi_rlast( o_axi_rlast),
|
| 570 |
|
|
.i_axi_rready( i_axi_rready),
|
| 571 |
8 |
dgisselq |
// Quantify where we are within a transaction
|
| 572 |
|
|
.f_axi_rd_outstanding( f_axi_rd_outstanding),
|
| 573 |
|
|
.f_axi_wr_outstanding( f_axi_wr_outstanding),
|
| 574 |
|
|
.f_axi_awr_outstanding(f_axi_awr_outstanding),
|
| 575 |
|
|
.f_axi_rd_id_outstanding(f_axi_rd_id_outstanding),
|
| 576 |
|
|
.f_axi_awr_id_outstanding(f_axi_awr_id_outstanding),
|
| 577 |
16 |
dgisselq |
.f_axi_wr_id_outstanding(f_axi_wr_id_outstanding),
|
| 578 |
|
|
.f_axi_wr_pending(f_axi_wr_pending),
|
| 579 |
|
|
.f_axi_rd_count(f_axi_rd_count),
|
| 580 |
|
|
.f_axi_wr_count(f_axi_wr_count));
|
| 581 |
8 |
dgisselq |
|
| 582 |
16 |
dgisselq |
wire f_axi_ard_req, f_axi_awr_req, f_axi_wr_req,
|
| 583 |
|
|
f_axi_rd_ack, f_axi_wr_ack;
|
| 584 |
|
|
|
| 585 |
|
|
assign f_axi_ard_req = (i_axi_arvalid)&&(o_axi_arready);
|
| 586 |
|
|
assign f_axi_awr_req = (i_axi_awvalid)&&(o_axi_awready);
|
| 587 |
|
|
assign f_axi_wr_req = (i_axi_wvalid)&&(o_axi_wready);
|
| 588 |
|
|
assign f_axi_wr_ack = (o_axi_bvalid)&&(i_axi_bready);
|
| 589 |
|
|
assign f_axi_rd_ack = (o_axi_rvalid)&&(i_axi_rready);
|
| 590 |
|
|
|
| 591 |
|
|
wire [(LGFIFO-1):0] f_awr_fifo_axi_used,
|
| 592 |
|
|
f_dwr_fifo_axi_used,
|
| 593 |
|
|
f_rd_fifo_axi_used,
|
| 594 |
|
|
f_wr_fifo_wb_outstanding,
|
| 595 |
|
|
f_rd_fifo_wb_outstanding;
|
| 596 |
|
|
|
| 597 |
|
|
assign f_awr_fifo_axi_used = f_wr_fifo_ahead - f_wr_fifo_tail;
|
| 598 |
|
|
assign f_dwr_fifo_axi_used = f_wr_fifo_dhead - f_wr_fifo_tail;
|
| 599 |
|
|
assign f_rd_fifo_axi_used = f_rd_fifo_head - f_rd_fifo_tail;
|
| 600 |
|
|
assign f_wr_fifo_wb_outstanding = f_wr_fifo_neck - f_wr_fifo_torso;
|
| 601 |
|
|
assign f_rd_fifo_wb_outstanding = f_rd_fifo_neck - f_rd_fifo_torso;
|
| 602 |
|
|
|
| 603 |
|
|
// The number of outstanding requests must always be greater than
|
| 604 |
|
|
// the number of AXI requests creating them--since the AXI requests
|
| 605 |
|
|
// may be burst requests.
|
| 606 |
|
|
//
|
| 607 |
|
|
always @(*)
|
| 608 |
|
|
if (OPT_READONLY)
|
| 609 |
|
|
begin
|
| 610 |
|
|
assert(f_axi_awr_outstanding == 0);
|
| 611 |
|
|
assert(f_axi_wr_outstanding == 0);
|
| 612 |
|
|
assert(f_axi_awr_id_outstanding == 0);
|
| 613 |
|
|
assert(f_axi_wr_id_outstanding == 0);
|
| 614 |
|
|
assert(f_axi_wr_pending == 0);
|
| 615 |
|
|
assert(f_axi_wr_count == 0);
|
| 616 |
|
|
end else begin
|
| 617 |
|
|
assert(f_awr_fifo_axi_used >= f_axi_awr_outstanding);
|
| 618 |
|
|
assert(f_dwr_fifo_axi_used >= f_axi_wr_outstanding);
|
| 619 |
|
|
assert(f_wr_fifo_ahead >= f_axi_awr_outstanding);
|
| 620 |
|
|
end
|
| 621 |
|
|
|
| 622 |
|
|
/*
|
| 623 |
|
|
always @(*)
|
| 624 |
|
|
assert((!w_wb_cyc)
|
| 625 |
|
|
||(f_wr_fifo_wb_outstanding
|
| 626 |
|
|
// -(((w_wb_stall)&&(w_wb_stb))? 1'b1:1'b0)
|
| 627 |
|
|
+(((w_wb_ack)&&(w_wb_err))? 1'b1:1'b0)
|
| 628 |
|
|
== f_wb_wr_outstanding));
|
| 629 |
|
|
*/
|
| 630 |
|
|
|
| 631 |
|
|
wire f_r_wb_req, f_r_wb_ack, f_r_wb_stall;
|
| 632 |
|
|
assign f_r_wb_req = (r_wb_stb)&&(!r_wb_stall);
|
| 633 |
|
|
assign f_r_wb_ack = (r_wb_cyc)&&((r_wb_ack)||(r_wb_err));
|
| 634 |
|
|
assign f_r_wb_stall=(r_wb_stb)&&(r_wb_stall);
|
| 635 |
|
|
|
| 636 |
|
|
/*
|
| 637 |
|
|
always @(*)
|
| 638 |
|
|
if ((i_axi_reset_n)&&(r_wb_cyc))
|
| 639 |
|
|
assert(f_rd_fifo_wb_outstanding
|
| 640 |
|
|
// -((f_r_wb_req)? 1'b1:1'b0)
|
| 641 |
|
|
-((r_wb_stb)? 1'b1:1'b0)
|
| 642 |
|
|
//+(((f_r_wb_ack)&&(!f_r_wb_req))? 1'b1:1'b0)
|
| 643 |
|
|
== f_wb_rd_outstanding);
|
| 644 |
|
|
*/
|
| 645 |
|
|
|
| 646 |
|
|
|
| 647 |
|
|
//
|
| 648 |
|
|
assert property((!OPT_READONLY)||(!OPT_WRITEONLY));
|
| 649 |
|
|
|
| 650 |
|
|
always @(*)
|
| 651 |
|
|
if (OPT_READONLY)
|
| 652 |
|
|
begin
|
| 653 |
|
|
assume(i_axi_awvalid == 0);
|
| 654 |
|
|
assume(i_axi_wvalid == 0);
|
| 655 |
|
|
end
|
| 656 |
|
|
always @(*)
|
| 657 |
|
|
if (OPT_WRITEONLY)
|
| 658 |
|
|
assume(i_axi_arvalid == 0);
|
| 659 |
|
|
|
| 660 |
|
|
always @(*)
|
| 661 |
|
|
if (i_axi_awvalid)
|
| 662 |
|
|
assume(i_axi_awburst[1] == 1'b0);
|
| 663 |
|
|
always @(*)
|
| 664 |
|
|
if (i_axi_arvalid)
|
| 665 |
|
|
assume(i_axi_arburst[1] == 1'b0);
|
| 666 |
|
|
|
| 667 |
|
|
always @(*)
|
| 668 |
|
|
if (F_OPT_BURSTS)
|
| 669 |
|
|
begin
|
| 670 |
|
|
assume((!i_axi_arvalid)||(i_axi_arlen<= OPT_MAXBURST));
|
| 671 |
|
|
assume((!i_axi_awvalid)||(i_axi_awlen<= OPT_MAXBURST));
|
| 672 |
|
|
end else begin
|
| 673 |
|
|
assume((!i_axi_arvalid)||(i_axi_arlen == 0));
|
| 674 |
|
|
assume((!i_axi_awvalid)||(i_axi_awlen == 0));
|
| 675 |
|
|
end
|
| 676 |
|
|
|
| 677 |
8 |
dgisselq |
`endif
|
| 678 |
|
|
endmodule
|
| 679 |
|
|
|
