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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: demoaxi.v
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//
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// Project: Pipelined Wishbone to AXI converter
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//
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// Purpose: Demonstrate an AXI-lite bus design. The goal of this design
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// is to support a completely pipelined AXI-lite transaction
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// which can transfer one data item per clock.
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//
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// Note that the AXI spec requires that there be no combinatorial
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// logic between input ports and output ports. Hence all of the *valid
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// and *ready signals produced here are registered. This forces us into
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// the buffered handshake strategy.
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//
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// Some curious variable meanings below:
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//
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// !axi_arvalid is synonymous with having a request, but stalling because
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// of a current request sitting in axi_rvalid with !axi_rready
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// !axi_awvalid is also synonymous with having an axi address being
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// received, but either the axi_bvalid && !axi_bready, or
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// no write data has been received
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// !axi_wvalid is similar to axi_awvalid.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2018-2019, Gisselquist Technology, LLC
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//
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// This file is part of the pipelined Wishbone to AXI converter project, a
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// project that contains multiple bus bridging designs and formal bus property
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// sets.
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//
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// The bus bridge designs and property sets are free RTL designs: you can
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// redistribute them and/or modify any of them under the terms of the GNU
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// Lesser General Public License as published by the Free Software Foundation,
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// either version 3 of the License, or (at your option) any later version.
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//
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// The bus bridge designs and property sets are distributed in the hope that
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// they will be useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with these designs. (It's in the $(ROOT)/doc directory. Run make
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// with no target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: LGPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/lgpl.html
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype none
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`timescale 1 ns / 1 ps
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module demoaxi
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#(
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// Users to add parameters here
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parameter [0:0] OPT_READ_SIDEEFFECTS = 1,
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// User parameters ends
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// Do not modify the parameters beyond this line
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// Width of S_AXI data bus
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parameter integer C_S_AXI_DATA_WIDTH = 32,
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// Width of S_AXI address bus
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parameter integer C_S_AXI_ADDR_WIDTH = 8
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) (
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// Users to add ports here
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// No user ports (yet) in this design
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// User ports ends
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// Do not modify the ports beyond this line
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// Global Clock Signal
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input wire S_AXI_ACLK,
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// Global Reset Signal. This Signal is Active LOW
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input wire S_AXI_ARESETN,
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// Write address (issued by master, acceped by Slave)
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input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
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// Write channel Protection type. This signal indicates the
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// privilege and security level of the transaction, and whether
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// the transaction is a data access or an instruction access.
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input wire [2 : 0] S_AXI_AWPROT,
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// Write address valid. This signal indicates that the master
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// signaling valid write address and control information.
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input wire S_AXI_AWVALID,
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// Write address ready. This signal indicates that the slave
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// is ready to accept an address and associated control signals.
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output wire S_AXI_AWREADY,
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// Write data (issued by master, acceped by Slave)
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input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
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// Write strobes. This signal indicates which byte lanes hold
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// valid data. There is one write strobe bit for each eight
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// bits of the write data bus.
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input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
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// Write valid. This signal indicates that valid write
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// data and strobes are available.
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input wire S_AXI_WVALID,
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// Write ready. This signal indicates that the slave
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// can accept the write data.
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output wire S_AXI_WREADY,
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// Write response. This signal indicates the status
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// of the write transaction.
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output wire [1 : 0] S_AXI_BRESP,
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// Write response valid. This signal indicates that the channel
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// is signaling a valid write response.
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output wire S_AXI_BVALID,
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// Response ready. This signal indicates that the master
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// can accept a write response.
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input wire S_AXI_BREADY,
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// Read address (issued by master, acceped by Slave)
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input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
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// Protection type. This signal indicates the privilege
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// and security level of the transaction, and whether the
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// transaction is a data access or an instruction access.
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input wire [2 : 0] S_AXI_ARPROT,
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// Read address valid. This signal indicates that the channel
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// is signaling valid read address and control information.
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input wire S_AXI_ARVALID,
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// Read address ready. This signal indicates that the slave is
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// ready to accept an address and associated control signals.
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output wire S_AXI_ARREADY,
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// Read data (issued by slave)
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output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
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// Read response. This signal indicates the status of the
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// read transfer.
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output wire [1 : 0] S_AXI_RRESP,
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// Read valid. This signal indicates that the channel is
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// signaling the required read data.
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output wire S_AXI_RVALID,
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// Read ready. This signal indicates that the master can
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// accept the read data and response information.
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input wire S_AXI_RREADY
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);
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// AXI4LITE signals
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reg axi_awready;
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reg axi_wready;
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reg [1 : 0] axi_bresp;
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reg axi_bvalid;
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reg axi_arready;
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reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
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reg [1 : 0] axi_rresp;
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reg axi_rvalid;
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// Example-specific design signals
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// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
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// ADDR_LSB is used for addressing 32/64 bit registers/memories
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// ADDR_LSB = 2 for 32 bits (n downto 2)
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// ADDR_LSB = 3 for 64 bits (n downto 3)
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localparam integer ADDR_LSB = 2;
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localparam integer AW = C_S_AXI_ADDR_WIDTH-2;
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localparam integer DW = C_S_AXI_DATA_WIDTH;
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//----------------------------------------------
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//-- Signals for user logic register space example
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//------------------------------------------------
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reg [DW-1:0] slv_mem [0:63];
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// I/O Connections assignments
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assign S_AXI_AWREADY = axi_awready;
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assign S_AXI_WREADY = axi_wready;
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assign S_AXI_BRESP = axi_bresp;
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assign S_AXI_BVALID = axi_bvalid;
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assign S_AXI_ARREADY = axi_arready;
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assign S_AXI_RDATA = axi_rdata;
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assign S_AXI_RRESP = axi_rresp;
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assign S_AXI_RVALID = axi_rvalid;
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// Implement axi_*wready generation
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//////////////////////////////////////
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//
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// Read processing
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//
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//
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initial axi_rvalid = 1'b0;
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always @( posedge S_AXI_ACLK )
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if (!S_AXI_ARESETN)
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axi_rvalid <= 0;
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else if (S_AXI_ARVALID)
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axi_rvalid <= 1'b1;
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else if ((S_AXI_RVALID)&&(!S_AXI_RREADY))
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axi_rvalid <= 1'b1;
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else if (!axi_arready)
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axi_rvalid <= 1'b1;
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else
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axi_rvalid <= 1'b0;
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always @(*)
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axi_rresp = 0; // "OKAY" response
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reg [C_S_AXI_ADDR_WIDTH-1 : 0] dly_addr, rd_addr;
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always @(posedge S_AXI_ACLK)
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if (S_AXI_ARREADY)
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dly_addr <= S_AXI_ARADDR;
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always @(*)
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if (!axi_arready)
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rd_addr = dly_addr;
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else
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rd_addr = S_AXI_ARADDR;
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always @(posedge S_AXI_ACLK)
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if (((!S_AXI_RVALID)||(S_AXI_RREADY))
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&&(!OPT_READ_SIDEEFFECTS
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||(!S_AXI_ARREADY || S_AXI_ARVALID)))
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// If the outgoing channel is not stalled (above)
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// then read
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axi_rdata <= slv_mem[rd_addr[AW+ADDR_LSB-1:ADDR_LSB]];
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initial axi_arready = 1'b0;
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always @(posedge S_AXI_ACLK)
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if (!S_AXI_ARESETN)
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axi_arready <= 1'b1;
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else if ((S_AXI_RVALID)&&(!S_AXI_RREADY))
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begin
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// Outgoing channel is stalled
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if (!axi_arready)
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// If something is already in the buffer,
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// axi_arready needs to stay low
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axi_arready <= 1'b0;
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else
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axi_arready <= (!S_AXI_ARVALID);
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end else
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axi_arready <= 1'b1;
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//////////////////////////////////////
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//
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// Write processing
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//
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//
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reg [C_S_AXI_ADDR_WIDTH-1 : 0] pre_waddr, waddr;
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reg [C_S_AXI_DATA_WIDTH-1 : 0] pre_wdata, wdata;
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reg [(C_S_AXI_DATA_WIDTH/8)-1 : 0] pre_wstrb, wstrb;
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//
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// The write address channel ready signal
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//
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initial axi_awready = 1'b1;
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always @(posedge S_AXI_ACLK)
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if (!S_AXI_ARESETN)
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axi_awready <= 1'b1;
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else if ((S_AXI_BVALID)&&(!S_AXI_BREADY))
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begin
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// The output channel is stalled
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if (!axi_awready)
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// If our buffer is full, remain stalled
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axi_awready <= 1'b0;
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else
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// If the buffer is empty, accept one transaction
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// to fill it and then stall
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axi_awready <= (!S_AXI_AWVALID);
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end else if ((!axi_wready)||((S_AXI_WVALID)&&(S_AXI_WREADY)))
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// The output channel is clear, and write data
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// are available
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axi_awready <= 1'b1;
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else
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// If we were ready before, then remain ready unless an
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// address unaccompanied by data shows up
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axi_awready <= ((axi_awready)&&(!S_AXI_AWVALID));
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//
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// The write data channel ready signal
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//
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initial axi_wready = 1'b1;
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always @(posedge S_AXI_ACLK)
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if (!S_AXI_ARESETN)
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axi_wready <= 1'b1;
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else if ((S_AXI_BVALID)&&(!S_AXI_BREADY))
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begin
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// The output channel is stalled
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if (!axi_wready)
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axi_wready <= 1'b0;
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else
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axi_wready <= (!S_AXI_WVALID);
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end else if ((!axi_awready)||((S_AXI_AWVALID)&&(S_AXI_AWREADY)))
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// The output channel is clear, and a write address
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// is available
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axi_wready <= 1'b1;
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else
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// if we were ready before, and there's no new data avaialble
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// to cause us to stall, remain ready
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axi_wready <= (axi_wready)&&(!S_AXI_WVALID);
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// Buffer the address
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always @(posedge S_AXI_ACLK)
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if ((S_AXI_AWREADY)&&(S_AXI_AWVALID))
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pre_waddr <= S_AXI_AWADDR;
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// Buffer the data
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always @(posedge S_AXI_ACLK)
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if ((S_AXI_WREADY)&&(S_AXI_WVALID))
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begin
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pre_wdata <= S_AXI_WDATA;
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pre_wstrb <= S_AXI_WSTRB;
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end
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always @(*)
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if (!axi_awready)
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// Read the write address from our "buffer"
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waddr = pre_waddr;
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else
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waddr = S_AXI_AWADDR;
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always @(*)
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if (!axi_wready)
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begin
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// Read the write data from our "buffer"
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wstrb = pre_wstrb;
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wdata = pre_wdata;
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end else begin
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wstrb = S_AXI_WSTRB;
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wdata = S_AXI_WDATA;
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end
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always @( posedge S_AXI_ACLK )
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|
|
// If the output channel isn't stalled, and
|
| 324 |
|
|
if (((!S_AXI_BVALID)||(S_AXI_BREADY))
|
| 325 |
|
|
// If we have a valid address, and
|
| 326 |
|
|
&&((!axi_awready)||(S_AXI_AWVALID))
|
| 327 |
|
|
// If we have valid data
|
| 328 |
|
|
&&((!axi_wready)||((S_AXI_WVALID))))
|
| 329 |
|
|
begin
|
| 330 |
|
|
if (wstrb[0])
|
| 331 |
|
|
slv_mem[waddr[AW+ADDR_LSB-1:ADDR_LSB]][7:0]
|
| 332 |
|
|
<= wdata[7:0];
|
| 333 |
|
|
if (wstrb[1])
|
| 334 |
|
|
slv_mem[waddr[AW+ADDR_LSB-1:ADDR_LSB]][15:8]
|
| 335 |
|
|
<= wdata[15:8];
|
| 336 |
|
|
if (wstrb[2])
|
| 337 |
|
|
slv_mem[waddr[AW+ADDR_LSB-1:ADDR_LSB]][23:16]
|
| 338 |
|
|
<= wdata[23:16];
|
| 339 |
|
|
if (wstrb[3])
|
| 340 |
|
|
slv_mem[waddr[AW+ADDR_LSB-1:ADDR_LSB]][31:24]
|
| 341 |
|
|
<= wdata[31:24];
|
| 342 |
|
|
end
|
| 343 |
|
|
|
| 344 |
|
|
initial axi_bvalid = 1'b0;
|
| 345 |
|
|
always @( posedge S_AXI_ACLK )
|
| 346 |
|
|
if (!S_AXI_ARESETN)
|
| 347 |
|
|
axi_bvalid <= 1'b0;
|
| 348 |
|
|
//
|
| 349 |
|
|
// The outgoing response channel should indicate a valid write if ...
|
| 350 |
|
|
// 1. We have a valid address, and
|
| 351 |
|
|
else if (((!axi_awready)||(S_AXI_AWVALID))
|
| 352 |
|
|
// 2. We had valid data
|
| 353 |
|
|
&&((!axi_wready)||((S_AXI_WVALID))))
|
| 354 |
|
|
// It doesn't matter here if we are stalled or not
|
| 355 |
|
|
// We can keep setting ready as often as we want
|
| 356 |
|
|
axi_bvalid <= 1'b1;
|
| 357 |
|
|
else if (S_AXI_BREADY)
|
| 358 |
|
|
axi_bvalid <= 1'b0;
|
| 359 |
|
|
|
| 360 |
|
|
always @(*)
|
| 361 |
|
|
axi_bresp = 2'b0; // "OKAY" response
|
| 362 |
|
|
|
| 363 |
|
|
// Make Verilator happy
|
| 364 |
|
|
// Verilator lint_off UNUSED
|
| 365 |
|
|
wire [5*ADDR_LSB+5:0] unused;
|
| 366 |
|
|
assign unused = { S_AXI_AWPROT, S_AXI_ARPROT,
|
| 367 |
|
|
S_AXI_AWADDR[ADDR_LSB-1:0],
|
| 368 |
|
|
dly_addr[ADDR_LSB-1:0],
|
| 369 |
|
|
rd_addr[ADDR_LSB-1:0],
|
| 370 |
|
|
waddr[ADDR_LSB-1:0],
|
| 371 |
|
|
S_AXI_ARADDR[ADDR_LSB-1:0] };
|
| 372 |
|
|
// Verilator lint_on UNUSED
|
| 373 |
|
|
|
| 374 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 375 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 376 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 377 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 378 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 379 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 380 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 381 |
|
|
`ifdef FORMAL
|
| 382 |
|
|
localparam F_LGDEPTH = 4;
|
| 383 |
|
|
|
| 384 |
|
|
wire [(F_LGDEPTH-1):0] f_axi_awr_outstanding,
|
| 385 |
|
|
f_axi_wr_outstanding,
|
| 386 |
|
|
f_axi_rd_outstanding;
|
| 387 |
|
|
|
| 388 |
|
|
faxil_slave #(// .C_AXI_DATA_WIDTH(C_S_AXI_DATA_WIDTH),
|
| 389 |
|
|
.C_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH),
|
| 390 |
|
|
// .F_OPT_NO_READS(1'b0),
|
| 391 |
|
|
// .F_OPT_NO_WRITES(1'b0),
|
| 392 |
|
|
.F_LGDEPTH(F_LGDEPTH))
|
| 393 |
|
|
properties (
|
| 394 |
|
|
.i_clk(S_AXI_ACLK),
|
| 395 |
|
|
.i_axi_reset_n(S_AXI_ARESETN),
|
| 396 |
|
|
//
|
| 397 |
|
|
.i_axi_awaddr(S_AXI_AWADDR),
|
| 398 |
|
|
.i_axi_awcache(4'h0),
|
| 399 |
|
|
.i_axi_awprot(S_AXI_AWPROT),
|
| 400 |
|
|
.i_axi_awvalid(S_AXI_AWVALID),
|
| 401 |
|
|
.i_axi_awready(S_AXI_AWREADY),
|
| 402 |
|
|
//
|
| 403 |
|
|
.i_axi_wdata(S_AXI_WDATA),
|
| 404 |
|
|
.i_axi_wstrb(S_AXI_WSTRB),
|
| 405 |
|
|
.i_axi_wvalid(S_AXI_WVALID),
|
| 406 |
|
|
.i_axi_wready(S_AXI_WREADY),
|
| 407 |
|
|
//
|
| 408 |
|
|
.i_axi_bresp(S_AXI_BRESP),
|
| 409 |
|
|
.i_axi_bvalid(S_AXI_BVALID),
|
| 410 |
|
|
.i_axi_bready(S_AXI_BREADY),
|
| 411 |
|
|
//
|
| 412 |
|
|
.i_axi_araddr(S_AXI_ARADDR),
|
| 413 |
|
|
.i_axi_arprot(S_AXI_ARPROT),
|
| 414 |
|
|
.i_axi_arcache(4'h0),
|
| 415 |
|
|
.i_axi_arvalid(S_AXI_ARVALID),
|
| 416 |
|
|
.i_axi_arready(S_AXI_ARREADY),
|
| 417 |
|
|
//
|
| 418 |
|
|
.i_axi_rdata(S_AXI_RDATA),
|
| 419 |
|
|
.i_axi_rresp(S_AXI_RRESP),
|
| 420 |
|
|
.i_axi_rvalid(S_AXI_RVALID),
|
| 421 |
|
|
.i_axi_rready(S_AXI_RREADY),
|
| 422 |
|
|
//
|
| 423 |
|
|
.f_axi_rd_outstanding(f_axi_rd_outstanding),
|
| 424 |
|
|
.f_axi_wr_outstanding(f_axi_wr_outstanding),
|
| 425 |
|
|
.f_axi_awr_outstanding(f_axi_awr_outstanding));
|
| 426 |
|
|
|
| 427 |
|
|
reg f_past_valid;
|
| 428 |
|
|
initial f_past_valid = 1'b0;
|
| 429 |
|
|
always @(posedge S_AXI_ACLK)
|
| 430 |
|
|
f_past_valid <= 1'b1;
|
| 431 |
|
|
|
| 432 |
|
|
///////
|
| 433 |
|
|
//
|
| 434 |
|
|
// Properties necessary to pass induction
|
| 435 |
|
|
always @(*)
|
| 436 |
|
|
if (S_AXI_ARESETN)
|
| 437 |
|
|
begin
|
| 438 |
|
|
if (!S_AXI_RVALID)
|
| 439 |
|
|
assert(f_axi_rd_outstanding == 0);
|
| 440 |
|
|
else if (!S_AXI_ARREADY)
|
| 441 |
|
|
assert((f_axi_rd_outstanding == 2)||(f_axi_rd_outstanding == 1));
|
| 442 |
|
|
else
|
| 443 |
|
|
assert(f_axi_rd_outstanding == 1);
|
| 444 |
|
|
end
|
| 445 |
|
|
|
| 446 |
|
|
always @(*)
|
| 447 |
|
|
if (S_AXI_ARESETN)
|
| 448 |
|
|
begin
|
| 449 |
|
|
if (axi_bvalid)
|
| 450 |
|
|
begin
|
| 451 |
|
|
assert(f_axi_awr_outstanding == 1+(axi_awready ? 0:1));
|
| 452 |
|
|
assert(f_axi_wr_outstanding == 1+(axi_wready ? 0:1));
|
| 453 |
|
|
end else begin
|
| 454 |
|
|
assert(f_axi_awr_outstanding == (axi_awready ? 0:1));
|
| 455 |
|
|
assert(f_axi_wr_outstanding == (axi_wready ? 0:1));
|
| 456 |
|
|
end
|
| 457 |
|
|
end
|
| 458 |
|
|
|
| 459 |
|
|
|
| 460 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 461 |
|
|
//
|
| 462 |
|
|
// Cover properties
|
| 463 |
|
|
//
|
| 464 |
|
|
// In addition to making sure the design returns a value, any value,
|
| 465 |
|
|
// let's cover returning three values on adjacent clocks--just to prove
|
| 466 |
|
|
// we can.
|
| 467 |
|
|
//
|
| 468 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 469 |
|
|
//
|
| 470 |
|
|
//
|
| 471 |
|
|
always @( posedge S_AXI_ACLK )
|
| 472 |
|
|
if ((f_past_valid)&&(S_AXI_ARESETN))
|
| 473 |
|
|
cover(($past((S_AXI_BVALID && S_AXI_BREADY)))
|
| 474 |
|
|
&&($past((S_AXI_BVALID && S_AXI_BREADY),2))
|
| 475 |
|
|
&&(S_AXI_BVALID && S_AXI_BREADY));
|
| 476 |
|
|
|
| 477 |
|
|
always @( posedge S_AXI_ACLK )
|
| 478 |
|
|
if ((f_past_valid)&&(S_AXI_ARESETN))
|
| 479 |
|
|
cover(($past((S_AXI_RVALID && S_AXI_RREADY)))
|
| 480 |
|
|
&&($past((S_AXI_RVALID && S_AXI_RREADY),2))
|
| 481 |
|
|
&&(S_AXI_RVALID && S_AXI_RREADY));
|
| 482 |
|
|
|
| 483 |
|
|
// Let's go just one further, and verify we can do three returns in a
|
| 484 |
|
|
// row. Why? It might just be possible that one value was waiting
|
| 485 |
|
|
// already, and so we haven't yet tested that two requests could be
|
| 486 |
|
|
// made in a row.
|
| 487 |
|
|
always @( posedge S_AXI_ACLK )
|
| 488 |
|
|
if ((f_past_valid)&&(S_AXI_ARESETN))
|
| 489 |
|
|
cover(($past((S_AXI_BVALID && S_AXI_BREADY)))
|
| 490 |
|
|
&&($past((S_AXI_BVALID && S_AXI_BREADY),2))
|
| 491 |
|
|
&&($past((S_AXI_BVALID && S_AXI_BREADY),3))
|
| 492 |
|
|
&&(S_AXI_BVALID && S_AXI_BREADY));
|
| 493 |
|
|
|
| 494 |
|
|
always @( posedge S_AXI_ACLK )
|
| 495 |
|
|
if ((f_past_valid)&&(S_AXI_ARESETN))
|
| 496 |
|
|
cover(($past((S_AXI_RVALID && S_AXI_RREADY)))
|
| 497 |
|
|
&&($past((S_AXI_RVALID && S_AXI_RREADY),2))
|
| 498 |
|
|
&&($past((S_AXI_RVALID && S_AXI_RREADY),3))
|
| 499 |
|
|
&&(S_AXI_RVALID && S_AXI_RREADY));
|
| 500 |
|
|
|
| 501 |
|
|
//
|
| 502 |
|
|
// Let's create a sophisticated cover statement designed to show off
|
| 503 |
|
|
// how our core can handle stalls and non-valids, synchronizing
|
| 504 |
|
|
// across multiple scenarios
|
| 505 |
|
|
reg [22:0] fw_wrdemo_pipe, fr_wrdemo_pipe;
|
| 506 |
|
|
always @(*)
|
| 507 |
|
|
if (!S_AXI_ARESETN)
|
| 508 |
|
|
fw_wrdemo_pipe = 0;
|
| 509 |
|
|
else begin
|
| 510 |
|
|
fw_wrdemo_pipe[0] = (S_AXI_AWVALID)
|
| 511 |
|
|
&&(S_AXI_WVALID)
|
| 512 |
|
|
&&(S_AXI_BREADY);
|
| 513 |
|
|
fw_wrdemo_pipe[1] = fr_wrdemo_pipe[0]
|
| 514 |
|
|
&&(!S_AXI_AWVALID)
|
| 515 |
|
|
&&(!S_AXI_WVALID)
|
| 516 |
|
|
&&(S_AXI_BREADY);
|
| 517 |
|
|
fw_wrdemo_pipe[2] = fr_wrdemo_pipe[1]
|
| 518 |
|
|
&&(!S_AXI_AWVALID)
|
| 519 |
|
|
&&(!S_AXI_WVALID)
|
| 520 |
|
|
&&(S_AXI_BREADY);
|
| 521 |
|
|
//
|
| 522 |
|
|
//
|
| 523 |
|
|
fw_wrdemo_pipe[3] = fr_wrdemo_pipe[2]
|
| 524 |
|
|
&&(S_AXI_AWVALID)
|
| 525 |
|
|
&&(S_AXI_WVALID)
|
| 526 |
|
|
&&(S_AXI_BREADY);
|
| 527 |
|
|
fw_wrdemo_pipe[4] = fr_wrdemo_pipe[3]
|
| 528 |
|
|
&&(S_AXI_AWVALID)
|
| 529 |
|
|
&&(S_AXI_WVALID)
|
| 530 |
|
|
&&(S_AXI_BREADY);
|
| 531 |
|
|
fw_wrdemo_pipe[5] = fr_wrdemo_pipe[4]
|
| 532 |
|
|
&&(!S_AXI_AWVALID)
|
| 533 |
|
|
&&(S_AXI_WVALID)
|
| 534 |
|
|
&&(S_AXI_BREADY);
|
| 535 |
|
|
fw_wrdemo_pipe[6] = fr_wrdemo_pipe[5]
|
| 536 |
|
|
&&(S_AXI_AWVALID)
|
| 537 |
|
|
&&( S_AXI_WVALID)
|
| 538 |
|
|
&&( S_AXI_BREADY);
|
| 539 |
|
|
fw_wrdemo_pipe[7] = fr_wrdemo_pipe[6]
|
| 540 |
|
|
&&(!S_AXI_AWVALID)
|
| 541 |
|
|
&&(S_AXI_WVALID)
|
| 542 |
|
|
&&( S_AXI_BREADY);
|
| 543 |
|
|
fw_wrdemo_pipe[8] = fr_wrdemo_pipe[7]
|
| 544 |
|
|
&&(S_AXI_AWVALID)
|
| 545 |
|
|
&&(S_AXI_WVALID)
|
| 546 |
|
|
&&(S_AXI_BREADY);
|
| 547 |
|
|
fw_wrdemo_pipe[9] = fr_wrdemo_pipe[8]
|
| 548 |
|
|
// &&(S_AXI_AWVALID)
|
| 549 |
|
|
// &&(!S_AXI_WVALID)
|
| 550 |
|
|
&&(S_AXI_BREADY);
|
| 551 |
|
|
fw_wrdemo_pipe[10] = fr_wrdemo_pipe[9]
|
| 552 |
|
|
// &&(S_AXI_AWVALID)
|
| 553 |
|
|
// &&(S_AXI_WVALID)
|
| 554 |
|
|
// &&(S_AXI_BREADY);
|
| 555 |
|
|
&&(S_AXI_BREADY);
|
| 556 |
|
|
fw_wrdemo_pipe[11] = fr_wrdemo_pipe[10]
|
| 557 |
|
|
&&(S_AXI_AWVALID)
|
| 558 |
|
|
&&(S_AXI_WVALID)
|
| 559 |
|
|
&&(!S_AXI_BREADY);
|
| 560 |
|
|
fw_wrdemo_pipe[12] = fr_wrdemo_pipe[11]
|
| 561 |
|
|
&&(!S_AXI_AWVALID)
|
| 562 |
|
|
&&(!S_AXI_WVALID)
|
| 563 |
|
|
&&(S_AXI_BREADY);
|
| 564 |
|
|
fw_wrdemo_pipe[13] = fr_wrdemo_pipe[12]
|
| 565 |
|
|
&&(!S_AXI_AWVALID)
|
| 566 |
|
|
&&(!S_AXI_WVALID)
|
| 567 |
|
|
&&(S_AXI_BREADY);
|
| 568 |
|
|
fw_wrdemo_pipe[14] = fr_wrdemo_pipe[13]
|
| 569 |
|
|
&&(!S_AXI_AWVALID)
|
| 570 |
|
|
&&(!S_AXI_WVALID)
|
| 571 |
|
|
&&(f_axi_awr_outstanding == 0)
|
| 572 |
|
|
&&(f_axi_wr_outstanding == 0)
|
| 573 |
|
|
&&(S_AXI_BREADY);
|
| 574 |
|
|
//
|
| 575 |
|
|
//
|
| 576 |
|
|
//
|
| 577 |
|
|
fw_wrdemo_pipe[15] = fr_wrdemo_pipe[14]
|
| 578 |
|
|
&&(S_AXI_AWVALID)
|
| 579 |
|
|
&&(S_AXI_WVALID)
|
| 580 |
|
|
&&(S_AXI_BREADY);
|
| 581 |
|
|
fw_wrdemo_pipe[16] = fr_wrdemo_pipe[15]
|
| 582 |
|
|
&&(S_AXI_AWVALID)
|
| 583 |
|
|
&&(S_AXI_WVALID)
|
| 584 |
|
|
&&(S_AXI_BREADY);
|
| 585 |
|
|
fw_wrdemo_pipe[17] = fr_wrdemo_pipe[16]
|
| 586 |
|
|
&&(S_AXI_AWVALID)
|
| 587 |
|
|
&&(S_AXI_WVALID)
|
| 588 |
|
|
&&(S_AXI_BREADY);
|
| 589 |
|
|
fw_wrdemo_pipe[18] = fr_wrdemo_pipe[17]
|
| 590 |
|
|
&&(S_AXI_AWVALID)
|
| 591 |
|
|
&&(S_AXI_WVALID)
|
| 592 |
|
|
&&(!S_AXI_BREADY);
|
| 593 |
|
|
fw_wrdemo_pipe[19] = fr_wrdemo_pipe[18]
|
| 594 |
|
|
&&(S_AXI_AWVALID)
|
| 595 |
|
|
&&(S_AXI_WVALID)
|
| 596 |
|
|
&&(S_AXI_BREADY);
|
| 597 |
|
|
fw_wrdemo_pipe[20] = fr_wrdemo_pipe[19]
|
| 598 |
|
|
&&(S_AXI_AWVALID)
|
| 599 |
|
|
&&(S_AXI_WVALID)
|
| 600 |
|
|
&&(S_AXI_BREADY);
|
| 601 |
|
|
fw_wrdemo_pipe[21] = fr_wrdemo_pipe[20]
|
| 602 |
|
|
&&(!S_AXI_AWVALID)
|
| 603 |
|
|
&&(!S_AXI_WVALID)
|
| 604 |
|
|
&&(S_AXI_BREADY);
|
| 605 |
|
|
fw_wrdemo_pipe[22] = fr_wrdemo_pipe[21]
|
| 606 |
|
|
&&(!S_AXI_AWVALID)
|
| 607 |
|
|
&&(!S_AXI_WVALID)
|
| 608 |
|
|
&&(S_AXI_BREADY);
|
| 609 |
|
|
end
|
| 610 |
|
|
|
| 611 |
|
|
always @(posedge S_AXI_ACLK)
|
| 612 |
|
|
fr_wrdemo_pipe <= fw_wrdemo_pipe;
|
| 613 |
|
|
|
| 614 |
|
|
always @(*)
|
| 615 |
|
|
if (S_AXI_ARESETN)
|
| 616 |
|
|
begin
|
| 617 |
|
|
cover(fw_wrdemo_pipe[0]);
|
| 618 |
|
|
cover(fw_wrdemo_pipe[1]);
|
| 619 |
|
|
cover(fw_wrdemo_pipe[2]);
|
| 620 |
|
|
cover(fw_wrdemo_pipe[3]);
|
| 621 |
|
|
cover(fw_wrdemo_pipe[4]);
|
| 622 |
|
|
cover(fw_wrdemo_pipe[5]);
|
| 623 |
|
|
cover(fw_wrdemo_pipe[6]);
|
| 624 |
|
|
cover(fw_wrdemo_pipe[7]); //
|
| 625 |
|
|
cover(fw_wrdemo_pipe[8]);
|
| 626 |
|
|
cover(fw_wrdemo_pipe[9]);
|
| 627 |
|
|
cover(fw_wrdemo_pipe[10]);
|
| 628 |
|
|
cover(fw_wrdemo_pipe[11]);
|
| 629 |
|
|
cover(fw_wrdemo_pipe[12]);
|
| 630 |
|
|
cover(fw_wrdemo_pipe[13]);
|
| 631 |
|
|
cover(fw_wrdemo_pipe[14]);
|
| 632 |
|
|
cover(fw_wrdemo_pipe[15]);
|
| 633 |
|
|
cover(fw_wrdemo_pipe[16]);
|
| 634 |
|
|
cover(fw_wrdemo_pipe[17]);
|
| 635 |
|
|
cover(fw_wrdemo_pipe[18]);
|
| 636 |
|
|
cover(fw_wrdemo_pipe[19]);
|
| 637 |
|
|
cover(fw_wrdemo_pipe[20]);
|
| 638 |
|
|
cover(fw_wrdemo_pipe[21]);
|
| 639 |
|
|
cover(fw_wrdemo_pipe[22]);
|
| 640 |
|
|
end
|
| 641 |
|
|
|
| 642 |
|
|
//
|
| 643 |
|
|
// Now let's repeat, but for a read demo
|
| 644 |
|
|
reg [10:0] fw_rddemo_pipe, fr_rddemo_pipe;
|
| 645 |
|
|
always @(*)
|
| 646 |
|
|
if (!S_AXI_ARESETN)
|
| 647 |
|
|
fw_rddemo_pipe = 0;
|
| 648 |
|
|
else begin
|
| 649 |
|
|
fw_rddemo_pipe[0] = (S_AXI_ARVALID)
|
| 650 |
|
|
&&(S_AXI_RREADY);
|
| 651 |
|
|
fw_rddemo_pipe[1] = fr_rddemo_pipe[0]
|
| 652 |
|
|
&&(!S_AXI_ARVALID)
|
| 653 |
|
|
&&(S_AXI_RREADY);
|
| 654 |
|
|
fw_rddemo_pipe[2] = fr_rddemo_pipe[1]
|
| 655 |
|
|
&&(!S_AXI_ARVALID)
|
| 656 |
|
|
&&(S_AXI_RREADY);
|
| 657 |
|
|
//
|
| 658 |
|
|
//
|
| 659 |
|
|
fw_rddemo_pipe[3] = fr_rddemo_pipe[2]
|
| 660 |
|
|
&&(S_AXI_ARVALID)
|
| 661 |
|
|
&&(S_AXI_RREADY);
|
| 662 |
|
|
fw_rddemo_pipe[4] = fr_rddemo_pipe[3]
|
| 663 |
|
|
&&(S_AXI_ARVALID)
|
| 664 |
|
|
&&(S_AXI_RREADY);
|
| 665 |
|
|
fw_rddemo_pipe[5] = fr_rddemo_pipe[4]
|
| 666 |
|
|
&&(S_AXI_ARVALID)
|
| 667 |
|
|
&&(S_AXI_RREADY);
|
| 668 |
|
|
fw_rddemo_pipe[6] = fr_rddemo_pipe[5]
|
| 669 |
|
|
&&(S_AXI_ARVALID)
|
| 670 |
|
|
&&(!S_AXI_RREADY);
|
| 671 |
|
|
fw_rddemo_pipe[7] = fr_rddemo_pipe[6]
|
| 672 |
|
|
&&(S_AXI_ARVALID)
|
| 673 |
|
|
&&(S_AXI_RREADY);
|
| 674 |
|
|
fw_rddemo_pipe[8] = fr_rddemo_pipe[7]
|
| 675 |
|
|
&&(S_AXI_ARVALID)
|
| 676 |
|
|
&&(S_AXI_RREADY);
|
| 677 |
|
|
fw_rddemo_pipe[9] = fr_rddemo_pipe[8]
|
| 678 |
|
|
&&(!S_AXI_ARVALID)
|
| 679 |
|
|
&&(S_AXI_RREADY);
|
| 680 |
|
|
fw_rddemo_pipe[10] = fr_rddemo_pipe[9]
|
| 681 |
|
|
&&(f_axi_rd_outstanding == 0);
|
| 682 |
|
|
end
|
| 683 |
|
|
|
| 684 |
|
|
initial fr_rddemo_pipe = 0;
|
| 685 |
|
|
always @(posedge S_AXI_ACLK)
|
| 686 |
|
|
fr_rddemo_pipe <= fw_rddemo_pipe;
|
| 687 |
|
|
|
| 688 |
|
|
always @(*)
|
| 689 |
|
|
begin
|
| 690 |
|
|
cover(fw_rddemo_pipe[0]);
|
| 691 |
|
|
cover(fw_rddemo_pipe[1]);
|
| 692 |
|
|
cover(fw_rddemo_pipe[2]);
|
| 693 |
|
|
cover(fw_rddemo_pipe[3]);
|
| 694 |
|
|
cover(fw_rddemo_pipe[4]);
|
| 695 |
|
|
cover(fw_rddemo_pipe[5]);
|
| 696 |
|
|
cover(fw_rddemo_pipe[6]);
|
| 697 |
|
|
cover(fw_rddemo_pipe[7]);
|
| 698 |
|
|
cover(fw_rddemo_pipe[8]);
|
| 699 |
|
|
cover(fw_rddemo_pipe[9]);
|
| 700 |
|
|
cover(fw_rddemo_pipe[10]);
|
| 701 |
|
|
end
|
| 702 |
|
|
`endif
|
| 703 |
|
|
endmodule
|
