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////////////////////////////////////////////////////////////////////////////////
//
// Filename:    wbm2axisp.v (Wishbone master to AXI slave, pipelined)
//
// Project:     Pipelined Wishbone to AXI converter
//
// Purpose:     The B4 Wishbone SPEC allows transactions at a speed as fast as
//              one per clock.  The AXI bus allows transactions at a speed of
//      one read and one write transaction per clock.  These capabilities work
//      by allowing requests to take place prior to responses, such that the
//      requests might go out at once per clock and take several clocks, and
//      the responses may start coming back several clocks later.  In other
//      words, both protocols allow multiple transactions to be "in flight" at
//      the same time.  Current wishbone to AXI converters, however, handle only
//      one transaction at a time: initiating the transaction, and then waiting
//      for the transaction to complete before initiating the next.
//
//      The purpose of this core is to maintain the speed of both busses, while
//      transiting from the Wishbone (as master) to the AXI bus (as slave) and
//      back again.
//
//      Since the AXI bus allows transactions to be reordered, whereas the
//      wishbone does not, this core can be configured to reorder return
//      transactions as well.
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype        none
//
module wbm2axisp #(
        parameter C_AXI_ID_WIDTH        =   3, // The AXI id width used for R&W
                                             // This is an int between 1-16
        parameter C_AXI_DATA_WIDTH      = 128,// Width of the AXI R&W data
        parameter C_AXI_ADDR_WIDTH      =  28,  // AXI Address width (log wordsize)
        parameter DW                    =  32,  // Wishbone data width
        parameter AW                    =  26,  // Wishbone address width (log wordsize)
        parameter [0:0] STRICT_ORDER      = 1     // Reorder, or not? 0 -> Reorder
        ) (
        input   wire                    i_clk,  // System clock
        // input wire                   i_reset,// Wishbone reset signal--unused
 
// AXI write address channel signals
        input   wire                    i_axi_awready, // Slave is ready to accept
        output  reg     [C_AXI_ID_WIDTH-1:0]     o_axi_awid,     // Write ID
        output  reg     [C_AXI_ADDR_WIDTH-1:0]   o_axi_awaddr,   // Write address
        output  wire    [7:0]            o_axi_awlen,    // Write Burst Length
        output  wire    [2:0]            o_axi_awsize,   // Write Burst size
        output  wire    [1:0]            o_axi_awburst,  // Write Burst type
        output  wire    [0:0]             o_axi_awlock,   // Write lock type
        output  wire    [3:0]            o_axi_awcache,  // Write Cache type
        output  wire    [2:0]            o_axi_awprot,   // Write Protection type
        output  wire    [3:0]            o_axi_awqos,    // Write Quality of Svc
        output  reg                     o_axi_awvalid,  // Write address valid
 
// AXI write data channel signals
        input   wire                    i_axi_wready,  // Write data ready
        output  reg     [C_AXI_DATA_WIDTH-1:0]   o_axi_wdata,    // Write data
        output  reg     [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb,    // Write strobes
        output  wire                    o_axi_wlast,    // Last write transaction   
        output  reg                     o_axi_wvalid,   // Write valid
 
// AXI write response channel signals
        input wire [C_AXI_ID_WIDTH-1:0]  i_axi_bid,      // Response ID
        input   wire [1:0]               i_axi_bresp,    // Write response
        input   wire                    i_axi_bvalid,  // Write reponse valid
        output  wire                    o_axi_bready,  // Response ready
 
// AXI read address channel signals
        input   wire                    i_axi_arready,  // Read address ready
        output  wire    [C_AXI_ID_WIDTH-1:0]     o_axi_arid,     // Read ID
        output  wire    [C_AXI_ADDR_WIDTH-1:0]   o_axi_araddr,   // Read address
        output  wire    [7:0]            o_axi_arlen,    // Read Burst Length
        output  wire    [2:0]            o_axi_arsize,   // Read Burst size
        output  wire    [1:0]            o_axi_arburst,  // Read Burst type
        output  wire    [0:0]             o_axi_arlock,   // Read lock type
        output  wire    [3:0]            o_axi_arcache,  // Read Cache type
        output  wire    [2:0]            o_axi_arprot,   // Read Protection type
        output  wire    [3:0]            o_axi_arqos,    // Read Protection type
        output  reg                     o_axi_arvalid,  // Read address valid
 
// AXI read data channel signals   
        input wire [C_AXI_ID_WIDTH-1:0]  i_axi_rid,     // Response ID
        input   wire    [1:0]            i_axi_rresp,   // Read response
        input   wire                    i_axi_rvalid,  // Read reponse valid
        input wire [C_AXI_DATA_WIDTH-1:0] i_axi_rdata,    // Read data
        input   wire                    i_axi_rlast,    // Read last
        output  wire                    o_axi_rready,  // Read Response ready
 
        // We'll share the clock and the reset
        input   wire                    i_wb_cyc,
        input   wire                    i_wb_stb,
        input   wire                    i_wb_we,
        input   wire    [(AW-1):0]       i_wb_addr,
        input   wire    [(DW-1):0]       i_wb_data,
        input   wire    [(DW/8-1):0]     i_wb_sel,
        output  reg                     o_wb_ack,
        output  wire                    o_wb_stall,
        output  reg     [(DW-1):0]       o_wb_data,
        output  reg                     o_wb_err
);
 
//*****************************************************************************
// Parameter declarations
//*****************************************************************************
 
        localparam      LG_AXI_DW       = ( C_AXI_DATA_WIDTH ==   8) ? 3
                                        : ((C_AXI_DATA_WIDTH ==  16) ? 4
                                        : ((C_AXI_DATA_WIDTH ==  32) ? 5
                                        : ((C_AXI_DATA_WIDTH ==  64) ? 6
                                        : ((C_AXI_DATA_WIDTH == 128) ? 7
                                        : 8))));
 
        localparam      LG_WB_DW        = ( DW ==   8) ? 3
                                        : ((DW ==  16) ? 4
                                        : ((DW ==  32) ? 5
                                        : ((DW ==  64) ? 6
                                        : ((DW == 128) ? 7
                                        : 8))));
        localparam      LGFIFOLN = C_AXI_ID_WIDTH;
        localparam      FIFOLN = (1<<LGFIFOLN);
 
 
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
 
// Things we're not changing ...
        assign o_axi_awlen   = 8'h0;    // Burst length is one
        assign o_axi_awsize  = 3'b101;  // maximum bytes per burst is 32
        assign o_axi_awburst = 2'b01;   // Incrementing address (ignored)
        assign o_axi_arburst = 2'b01;   // Incrementing address (ignored)
        assign o_axi_awlock  = 1'b0;    // Normal signaling
        assign o_axi_arlock  = 1'b0;    // Normal signaling
        assign o_axi_awcache = 4'h2;    // Normal: no cache, no buffer
        assign o_axi_arcache = 4'h2;    // Normal: no cache, no buffer
        assign o_axi_awprot  = 3'b010;  // Unpriviledged, unsecure, data access
        assign o_axi_arprot  = 3'b010;  // Unpriviledged, unsecure, data access
        assign o_axi_awqos   = 4'h0;    // Lowest quality of service (unused)
        assign o_axi_arqos   = 4'h0;    // Lowest quality of service (unused)
 
        reg     wb_mid_cycle, wb_mid_abort;
        wire    wb_abort;
 
// Command logic
// Transaction ID logic
        wire    [(LGFIFOLN-1):0] fifo_head;
        reg     [(C_AXI_ID_WIDTH-1):0]   transaction_id;
 
        initial transaction_id = 0;
        always @(posedge i_clk)
                if ((i_wb_stb)&&(!o_wb_stall))
                        transaction_id <= transaction_id + 1'b1;
 
        assign  fifo_head = transaction_id;
 
        wire    [(DW/8-1):0]                     no_sel;
        wire    [(LG_AXI_DW-4):0]        axi_bottom_addr;
        assign  no_sel = 0;
        assign  axi_bottom_addr = 0;
 
 
// Write address logic
 
        initial o_axi_awvalid = 0;
        always @(posedge i_clk)
                o_axi_awvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)
                        ||(o_axi_awvalid)&&(!i_axi_awready);
 
        generate
 
        initial o_axi_awid = -1;
        always @(posedge i_clk)
                if ((i_wb_stb)&&(!o_wb_stall))
                        o_axi_awid <= transaction_id;
 
        if (C_AXI_DATA_WIDTH == DW)
        begin
                always @(posedge i_clk)
                        if ((i_wb_stb)&&(!o_wb_stall)) // 26 bit address becomes 28 bit ...
                                o_axi_awaddr <= { i_wb_addr[AW-1:0], axi_bottom_addr };
        end else if (C_AXI_DATA_WIDTH / DW == 2)
        begin
 
                always @(posedge i_clk)
                        if ((i_wb_stb)&&(!o_wb_stall)) // 26 bit address becomes 28 bit ...
                                o_axi_awaddr <= { i_wb_addr[AW-1:1], axi_bottom_addr };
 
        end else if (C_AXI_DATA_WIDTH / DW == 4)
        begin
                always @(posedge i_clk)
                if ((i_wb_stb)&&(!o_wb_stall)) // 26 bit address becomes 28 bit ...
                        o_axi_awaddr <= { i_wb_addr[AW-1:2], axi_bottom_addr };
        end endgenerate
 
 
// Read address logic
        assign  o_axi_arid   = o_axi_awid;
        assign  o_axi_araddr = o_axi_awaddr;
        assign  o_axi_arlen  = o_axi_awlen;
        assign  o_axi_arsize = 3'b101;  // maximum bytes per burst is 32
        initial o_axi_arvalid = 1'b0;
        always @(posedge i_clk)
                o_axi_arvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)
                        ||(o_axi_arvalid)&&(!i_axi_arready);
 
// Write data logic
        generate
        if (C_AXI_DATA_WIDTH == DW)
        begin
 
                always @(posedge i_clk)
                        if ((i_wb_stb)&&(!o_wb_stall))
                                o_axi_wdata <= i_wb_data;
 
                always @(posedge i_clk)
                        if ((i_wb_stb)&&(!o_wb_stall))
                                o_axi_wstrb<= i_wb_sel;
 
        end else if (C_AXI_DATA_WIDTH/2 == DW)
        begin
 
                always @(posedge i_clk)
                        if ((i_wb_stb)&&(!o_wb_stall))
                                o_axi_wdata <= { i_wb_data, i_wb_data };
 
                always @(posedge i_clk)
                        if ((i_wb_stb)&&(!o_wb_stall))
                        case(i_wb_addr[0])
                        1'b0:o_axi_wstrb<={  no_sel,i_wb_sel };
                        1'b1:o_axi_wstrb<={i_wb_sel,  no_sel };
                        endcase
 
        end else if (C_AXI_DATA_WIDTH/4 == DW)
        begin
 
                always @(posedge i_clk)
                        if ((i_wb_stb)&&(!o_wb_stall))
                                o_axi_wdata <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
 
                always @(posedge i_clk)
                        if ((i_wb_stb)&&(!o_wb_stall))
                        case(i_wb_addr[1:0])
                        2'b00:o_axi_wstrb<={   no_sel,   no_sel,   no_sel, i_wb_sel };
                        2'b01:o_axi_wstrb<={   no_sel,   no_sel, i_wb_sel,   no_sel };
                        2'b10:o_axi_wstrb<={   no_sel, i_wb_sel,   no_sel,   no_sel };
                        2'b11:o_axi_wstrb<={ i_wb_sel,   no_sel,   no_sel,   no_sel };
                        endcase
 
        end endgenerate
 
        assign  o_axi_wlast = 1'b1;
        initial o_axi_wvalid = 0;
        always @(posedge i_clk)
                o_axi_wvalid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))
                        ||(o_axi_wvalid)&&(!i_axi_wready);
 
        // Read data channel / response logic
        assign  o_axi_rready = 1'b1;
        assign  o_axi_bready = 1'b1;
 
        wire    [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;
        assign  n_fifo_head = fifo_head+1'b1;
        assign  nn_fifo_head = { fifo_head[(LGFIFOLN-1):1]+1'b1, fifo_head[0] };
 
 
        wire    w_fifo_full;
        reg     [(LGFIFOLN-1):0] fifo_tail;
 
        generate
        if (C_AXI_DATA_WIDTH == DW)
        begin
                if (STRICT_ORDER == 0)
                begin
                        reg     [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
 
                        always @(posedge i_clk)
                                if ((o_axi_rready)&&(i_axi_rvalid))
                                        reorder_fifo_data[i_axi_rid] <= i_axi_rdata;
                        always @(posedge i_clk)
                                o_wb_data <= reorder_fifo_data[fifo_tail];
                end else begin
                        reg     [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data;
 
                        always @(posedge i_clk)
                                reorder_fifo_data <= i_axi_rdata;
                        always @(posedge i_clk)
                                o_wb_data <= reorder_fifo_data;
                end
        end else if (C_AXI_DATA_WIDTH / DW == 2)
        begin
                reg             reorder_fifo_addr [0:(FIFOLN-1)];
 
                reg             low_addr;
                always @(posedge i_clk)
                        if ((i_wb_stb)&&(!o_wb_stall))
                                low_addr <= i_wb_addr[0];
                always @(posedge i_clk)
                        if ((o_axi_arvalid)&&(i_axi_arready))
                                reorder_fifo_addr[o_axi_arid] <= low_addr;
 
                if (STRICT_ORDER == 0)
                begin
                        reg     [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
 
                        always @(posedge i_clk)
                                if ((o_axi_rready)&&(i_axi_rvalid))
                                        reorder_fifo_data[i_axi_rid] <= i_axi_rdata;
                        always @(posedge i_clk)
                                reorder_fifo_data[i_axi_rid] <= i_axi_rdata;
                        always @(posedge i_clk)
                        case(reorder_fifo_addr[fifo_tail])
                        1'b0: o_wb_data <=reorder_fifo_data[fifo_tail][(  DW-1):    0 ];
                        1'b1: o_wb_data <=reorder_fifo_data[fifo_tail][(2*DW-1):(  DW)];
                        endcase
                end else begin
                        reg     [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data;
 
                        always @(posedge i_clk)
                                reorder_fifo_data <= i_axi_rdata;
                        always @(posedge i_clk)
                        case(reorder_fifo_addr[fifo_tail])
                        1'b0: o_wb_data <=reorder_fifo_data[(  DW-1):    0 ];
                        1'b1: o_wb_data <=reorder_fifo_data[(2*DW-1):(  DW)];
                        endcase
                end
        end else if (C_AXI_DATA_WIDTH / DW == 4)
        begin
                reg     [1:0]    reorder_fifo_addr [0:(FIFOLN-1)];
 
 
                reg     [1:0]    low_addr;
                always @(posedge i_clk)
                        if ((i_wb_stb)&&(!o_wb_stall))
                                low_addr <= i_wb_addr[1:0];
                always @(posedge i_clk)
                        if ((o_axi_arvalid)&&(i_axi_arready))
                                reorder_fifo_addr[o_axi_arid] <= low_addr;
 
                if (STRICT_ORDER == 0)
                begin
                        reg     [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
 
                        always @(posedge i_clk)
                                if ((o_axi_rready)&&(i_axi_rvalid))
                                        reorder_fifo_data[i_axi_rid] <= i_axi_rdata;
                        always @(posedge i_clk)
                        case(reorder_fifo_addr[fifo_tail][1:0])
                        2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][(  DW-1):    0 ];
                        2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][(2*DW-1):(  DW)];
                        2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][(3*DW-1):(2*DW)];
                        2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][(4*DW-1):(3*DW)];
                        endcase
                end else begin
                        reg     [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data;
 
                        always @(posedge i_clk)
                                reorder_fifo_data <= i_axi_rdata;
                        always @(posedge i_clk)
                        case(reorder_fifo_addr[fifo_tail][1:0])
                        2'b00: o_wb_data <=reorder_fifo_data[(  DW-1): 0];
                        2'b01: o_wb_data <=reorder_fifo_data[(2*DW-1):(  DW)];
                        2'b10: o_wb_data <=reorder_fifo_data[(3*DW-1):(2*DW)];
                        2'b11: o_wb_data <=reorder_fifo_data[(4*DW-1):(3*DW)];
                        endcase
                end
        end
 
        endgenerate
 
        // verilator lint_off UNUSED
        wire    axi_rd_ack, axi_wr_ack, axi_ard_req, axi_awr_req, axi_wr_req,
                axi_rd_err, axi_wr_err;
        // verilator lint_on  UNUSED
 
        //
        assign  axi_ard_req = (o_axi_arvalid)&&(i_axi_arready);
        assign  axi_awr_req = (o_axi_awvalid)&&(i_axi_awready);
        assign  axi_wr_req  = (o_axi_wvalid )&&(i_axi_wready);
        //
        assign  axi_rd_ack = (i_axi_rvalid)&&(o_axi_rready);
        assign  axi_wr_ack = (i_axi_bvalid)&&(o_axi_bready);
        assign  axi_rd_err = (axi_rd_ack)&&(i_axi_rresp[1]);
        assign  axi_wr_err = (axi_wr_ack)&&(i_axi_bresp[1]);
 
        //
        // We're going to need a FIFO on the return to make certain that we can
        // select the right bits from the return value, in the case where
        // DW != the axi data width.
        //
        // If we aren't using a strict order, this FIFO is can be used as a
        // reorder buffer as well, to place our out of order bus responses
        // back into order.  Responses on the wishbone, however, are *always*
        // done in order.
        generate
        if (STRICT_ORDER == 0)
        begin
                // Reorder FIFO
                //
                // FIFO reorder buffer
                reg     [(FIFOLN-1):0]   reorder_fifo_valid;
                reg     [(FIFOLN-1):0]   reorder_fifo_err;
 
                initial reorder_fifo_valid = 0;
                initial reorder_fifo_err = 0;
 
 
                initial fifo_tail = 0;
                initial o_wb_ack  = 0;
                initial o_wb_err  = 0;
                always @(posedge i_clk)
                begin
                        if (axi_rd_ack)
                        begin
                                reorder_fifo_valid[i_axi_rid] <= 1'b1;
                                reorder_fifo_err[i_axi_rid] <= axi_rd_err;
                        end
                        if (axi_wr_ack)
                        begin
                                reorder_fifo_valid[i_axi_bid] <= 1'b1;
                                reorder_fifo_err[i_axi_bid] <= axi_wr_err;
                        end
 
                        if (reorder_fifo_valid[fifo_tail])
                        begin
                                o_wb_ack <= (!wb_abort)&&(!reorder_fifo_err[fifo_tail]);
                                o_wb_err <= (!wb_abort)&&( reorder_fifo_err[fifo_tail]);
                                fifo_tail <= fifo_tail + 1'b1;
                                reorder_fifo_valid[fifo_tail] <= 1'b0;
                                reorder_fifo_err[fifo_tail]   <= 1'b0;
                        end else begin
                                o_wb_ack <= 1'b0;
                                o_wb_err <= 1'b0;
                        end
 
                        if (!i_wb_cyc)
                        begin
                                // reorder_fifo_valid <= 0;
                                // reorder_fifo_err   <= 0;
                                o_wb_err <= 1'b0;
                                o_wb_ack <= 1'b0;
                        end
                end
 
                reg     r_fifo_full;
                initial r_fifo_full = 0;
                always @(posedge i_clk)
                begin
                        if ((i_wb_stb)&&(!o_wb_stall)
                                        &&(reorder_fifo_valid[fifo_tail]))
                                r_fifo_full <= (fifo_tail==n_fifo_head);
                        else if ((i_wb_stb)&&(!o_wb_stall))
                                r_fifo_full <= (fifo_tail==nn_fifo_head);
                        else if (reorder_fifo_valid[fifo_tail])
                                r_fifo_full <= 1'b0;
                        else
                                r_fifo_full <= (fifo_tail==n_fifo_head);
                end
                assign w_fifo_full = r_fifo_full;
        end else begin
                //
                // Strict ordering
                //
                reg     reorder_fifo_valid;
                reg     reorder_fifo_err;
 
                initial reorder_fifo_valid = 1'b0;
                initial reorder_fifo_err   = 1'b0;
                always @(posedge i_clk)
                        if (axi_rd_ack)
                        begin
                                reorder_fifo_valid <= 1'b1;
                                reorder_fifo_err   <= axi_rd_err;
                        end else if (axi_wr_ack)
                        begin
                                reorder_fifo_valid <= 1'b1;
                                reorder_fifo_err   <= axi_wr_err;
                        end else begin
                                reorder_fifo_valid <= 1'b0;
                                reorder_fifo_err   <= 1'b0;
                        end
 
                initial fifo_tail = 0;
                always @(posedge i_clk)
                        if (reorder_fifo_valid)
                                fifo_tail <= fifo_tail + 1'b1;
 
                initial o_wb_ack  = 0;
                always @(posedge i_clk)
                        o_wb_ack <= (reorder_fifo_valid)&&(i_wb_cyc)&&(!wb_abort);
 
                initial o_wb_err  = 0;
                always @(posedge i_clk)
                        o_wb_err <= (reorder_fifo_err)&&(i_wb_cyc)&&(!wb_abort);
 
                reg     r_fifo_full;
                initial r_fifo_full = 0;
                always @(posedge i_clk)
                begin
                        if ((i_wb_stb)&&(!o_wb_stall)
                                        &&(reorder_fifo_valid))
                                r_fifo_full <= (fifo_tail==n_fifo_head);
                        else if ((i_wb_stb)&&(!o_wb_stall))
                                r_fifo_full <= (fifo_tail==nn_fifo_head);
                        else if (reorder_fifo_valid)
                                r_fifo_full <= 1'b0;
                        else
                                r_fifo_full <= (fifo_tail==n_fifo_head);
                end
 
                assign w_fifo_full = r_fifo_full;
 
                // verilator lint_off UNUSED
                wire    [2*C_AXI_ID_WIDTH-1:0]   strict_unused;
                assign  strict_unused = { i_axi_bid, i_axi_rid };
                // verilator lint_on  UNUSED
        end endgenerate
 
        //
        // Wishbone abort logic
        //
 
        // Are we mid-cycle?
        initial wb_mid_cycle = 0;
        always @(posedge i_clk)
                if ((fifo_head != fifo_tail)
                                ||(o_axi_arvalid)||(o_axi_awvalid)
                                ||(o_axi_wvalid)
                                ||(i_wb_cyc)&&(i_wb_stb)&&(!o_wb_stall))
                        wb_mid_cycle <= 1'b1;
                else
                        wb_mid_cycle <= 1'b0;
 
        always @(posedge i_clk)
                if (wb_mid_cycle)
                        wb_mid_abort <= (wb_mid_abort)||(!i_wb_cyc);
                else
                        wb_mid_abort <= 1'b0;
 
        assign  wb_abort = ((wb_mid_cycle)&&(!i_wb_cyc))||(wb_mid_abort);
 
        // Now, the difficult signal ... the stall signal
        // Let's build for a single cycle input ... and only stall if something
        // outgoing is valid and nothing is ready.
        assign  o_wb_stall = (i_wb_cyc)&&(
                                (w_fifo_full)||(wb_mid_abort)
                                ||((o_axi_awvalid)&&(!i_axi_awready))
                                ||((o_axi_wvalid )&&(!i_axi_wready ))
                                ||((o_axi_arvalid)&&(!i_axi_arready)));
 
 
        // Make Verilator happy
        // verilator lint_off UNUSED
        wire    [2:0]    unused;
        assign  unused = { i_axi_bresp[0], i_axi_rresp[0], i_axi_rlast };
        // verilator lint_on  UNUSED
 
/////////////////////////////////////////////////////////////////////////
//
//
//
// Formal methods section
//
// These are only relevant when *proving* that this translator works
//
//
//
/////////////////////////////////////////////////////////////////////////
//
// This section has been removed from this release.
//
endmodule

Line No.	Rev	Author	Line
1	2	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3	8	dgisselq	`// Filename: wbm2axisp.v (Wishbone master to AXI slave, pipelined)`
4	2	dgisselq	`//`
5			`// Project: Pipelined Wishbone to AXI converter`
6			`//`
7			`// Purpose: The B4 Wishbone SPEC allows transactions at a speed as fast as`
8			`// one per clock. The AXI bus allows transactions at a speed of`
9			`// one read and one write transaction per clock. These capabilities work`
10			`// by allowing requests to take place prior to responses, such that the`
11			`// requests might go out at once per clock and take several clocks, and`
12			`// the responses may start coming back several clocks later. In other`
13			`// words, both protocols allow multiple transactions to be "in flight" at`
14			`// the same time. Current wishbone to AXI converters, however, handle only`
15			`// one transaction at a time: initiating the transaction, and then waiting`
16			`// for the transaction to complete before initiating the next.`
17			`//`
18			`// The purpose of this core is to maintain the speed of both busses, while`
19			`// transiting from the Wishbone (as master) to the AXI bus (as slave) and`
20			`// back again.`
21			`//`
22	8	dgisselq	`// Since the AXI bus allows transactions to be reordered, whereas the`
23	2	dgisselq	`// wishbone does not, this core can be configured to reorder return`
24			`// transactions as well.`
25			`//`
26			`// Creator: Dan Gisselquist, Ph.D.`
27			`// Gisselquist Technology, LLC`
28			`//`
29			`////////////////////////////////////////////////////////////////////////////////`
30			`//`
31	3	dgisselq	`// Copyright (C) 2016, Gisselquist Technology, LLC`
32	2	dgisselq	`//`
33			`// This program is free software (firmware): you can redistribute it and/or`
34			`// modify it under the terms of the GNU General Public License as published`
35			`// by the Free Software Foundation, either version 3 of the License, or (at`
36			`// your option) any later version.`
37			`//`
38			`// This program is distributed in the hope that it will be useful, but WITHOUT`
39			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
40			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
41			`// for more details.`
42			`//`
43			`// You should have received a copy of the GNU General Public License along`
44			`// with this program. (It's in the $(ROOT)/doc directory, run make with no`
45			`// target there if the PDF file isn't present.) If not, see`
46			`// <http://www.gnu.org/licenses/> for a copy.`
47			`//`
48			`// License: GPL, v3, as defined and found on www.gnu.org,`
49			`// http://www.gnu.org/licenses/gpl.html`
50			`//`
51			`//`
52			`////////////////////////////////////////////////////////////////////////////////`
53			`//`
54			`//`
55	8	dgisselq	`default_nettype none
56			`//`
57	2	dgisselq	`module wbm2axisp #(`
58	13	dgisselq	`parameter C_AXI_ID_WIDTH = 3, // The AXI id width used for R&W`
59	2	dgisselq	`// This is an int between 1-16`
60	13	dgisselq	`parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data`
61			`parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width (log wordsize)`
62			`parameter DW = 32, // Wishbone data width`
63			`parameter AW = 26, // Wishbone address width (log wordsize)`
64	8	dgisselq	`parameter [0:0] STRICT_ORDER = 1 // Reorder, or not? 0 -> Reorder`
65	2	dgisselq	`) (`
66	13	dgisselq	`input wire i_clk, // System clock`
67			`// input wire i_reset,// Wishbone reset signal--unused`
68	2	dgisselq
69			`// AXI write address channel signals`
70	13	dgisselq	`input wire i_axi_awready, // Slave is ready to accept`
71	6	dgisselq	`output reg [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID`
72			`output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr, // Write address`
73	5	dgisselq	`output wire [7:0] o_axi_awlen, // Write Burst Length`
74			`output wire [2:0] o_axi_awsize, // Write Burst size`
75			`output wire [1:0] o_axi_awburst, // Write Burst type`
76	6	dgisselq	`output wire [0:0] o_axi_awlock, // Write lock type`
77	5	dgisselq	`output wire [3:0] o_axi_awcache, // Write Cache type`
78			`output wire [2:0] o_axi_awprot, // Write Protection type`
79			`output wire [3:0] o_axi_awqos, // Write Quality of Svc`
80			`output reg o_axi_awvalid, // Write address valid`
81	8	dgisselq
82	2	dgisselq	`// AXI write data channel signals`
83	13	dgisselq	`input wire i_axi_wready, // Write data ready`
84	5	dgisselq	`output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata, // Write data`
85			`output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb, // Write strobes`
86	13	dgisselq	`output wire o_axi_wlast, // Last write transaction`
87	5	dgisselq	`output reg o_axi_wvalid, // Write valid`
88	8	dgisselq
89	2	dgisselq	`// AXI write response channel signals`
90	13	dgisselq	`input wire [C_AXI_ID_WIDTH-1:0] i_axi_bid, // Response ID`
91			`input wire [1:0] i_axi_bresp, // Write response`
92			`input wire i_axi_bvalid, // Write reponse valid`
93	5	dgisselq	`output wire o_axi_bready, // Response ready`
94	8	dgisselq
95	2	dgisselq	`// AXI read address channel signals`
96	13	dgisselq	`input wire i_axi_arready, // Read address ready`
97	5	dgisselq	`output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID`
98	6	dgisselq	`output wire [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr, // Read address`
99	5	dgisselq	`output wire [7:0] o_axi_arlen, // Read Burst Length`
100			`output wire [2:0] o_axi_arsize, // Read Burst size`
101			`output wire [1:0] o_axi_arburst, // Read Burst type`
102	6	dgisselq	`output wire [0:0] o_axi_arlock, // Read lock type`
103	5	dgisselq	`output wire [3:0] o_axi_arcache, // Read Cache type`
104			`output wire [2:0] o_axi_arprot, // Read Protection type`
105			`output wire [3:0] o_axi_arqos, // Read Protection type`
106			`output reg o_axi_arvalid, // Read address valid`
107	8	dgisselq
108	13	dgisselq	`// AXI read data channel signals`
109			`input wire [C_AXI_ID_WIDTH-1:0] i_axi_rid, // Response ID`
110			`input wire [1:0] i_axi_rresp, // Read response`
111			`input wire i_axi_rvalid, // Read reponse valid`
112			`input wire [C_AXI_DATA_WIDTH-1:0] i_axi_rdata, // Read data`
113			`input wire i_axi_rlast, // Read last`
114	5	dgisselq	`output wire o_axi_rready, // Read Response ready`
115	2	dgisselq
116			`// We'll share the clock and the reset`
117	13	dgisselq	`input wire i_wb_cyc,`
118			`input wire i_wb_stb,`
119			`input wire i_wb_we,`
120			`input wire [(AW-1):0] i_wb_addr,`
121			`input wire [(DW-1):0] i_wb_data,`
122			`input wire [(DW/8-1):0] i_wb_sel,`
123	3	dgisselq	`output reg o_wb_ack,`
124			`output wire o_wb_stall,`
125	6	dgisselq	`output reg [(DW-1):0] o_wb_data,`
126	3	dgisselq	`output reg o_wb_err`
127	2	dgisselq	`);`
128
129			`//*****************************************************************************`
130			`// Parameter declarations`
131			`//*****************************************************************************`
132
133	8	dgisselq	`localparam LG_AXI_DW = ( C_AXI_DATA_WIDTH == 8) ? 3`
134			`: ((C_AXI_DATA_WIDTH == 16) ? 4`
135			`: ((C_AXI_DATA_WIDTH == 32) ? 5`
136			`: ((C_AXI_DATA_WIDTH == 64) ? 6`
137			`: ((C_AXI_DATA_WIDTH == 128) ? 7`
138			`: 8))));`
139	2	dgisselq
140	8	dgisselq	`localparam LG_WB_DW = ( DW == 8) ? 3`
141			`: ((DW == 16) ? 4`
142			`: ((DW == 32) ? 5`
143			`: ((DW == 64) ? 6`
144			`: ((DW == 128) ? 7`
145			`: 8))));`
146			`localparam LGFIFOLN = C_AXI_ID_WIDTH;`
147			`localparam FIFOLN = (1<<LGFIFOLN);`
148
149
150	2	dgisselq	`//*****************************************************************************`
151			`// Internal register and wire declarations`
152			`//*****************************************************************************`
153
154			`// Things we're not changing ...`
155	8	dgisselq	`assign o_axi_awlen = 8'h0; // Burst length is one`
156			`assign o_axi_awsize = 3'b101; // maximum bytes per burst is 32`
157	5	dgisselq	`assign o_axi_awburst = 2'b01; // Incrementing address (ignored)`
158			`assign o_axi_arburst = 2'b01; // Incrementing address (ignored)`
159	6	dgisselq	`assign o_axi_awlock = 1'b0; // Normal signaling`
160			`assign o_axi_arlock = 1'b0; // Normal signaling`
161	5	dgisselq	`assign o_axi_awcache = 4'h2; // Normal: no cache, no buffer`
162			`assign o_axi_arcache = 4'h2; // Normal: no cache, no buffer`
163	6	dgisselq	`assign o_axi_awprot = 3'b010; // Unpriviledged, unsecure, data access`
164			`assign o_axi_arprot = 3'b010; // Unpriviledged, unsecure, data access`
165	8	dgisselq	`assign o_axi_awqos = 4'h0; // Lowest quality of service (unused)`
166			`assign o_axi_arqos = 4'h0; // Lowest quality of service (unused)`
167	2	dgisselq
168	13	dgisselq	`reg wb_mid_cycle, wb_mid_abort;`
169			`wire wb_abort;`
170
171	2	dgisselq	`// Command logic`
172	8	dgisselq	`// Transaction ID logic`
173			`wire [(LGFIFOLN-1):0] fifo_head;`
174			`reg [(C_AXI_ID_WIDTH-1):0] transaction_id;`
175
176			`initial transaction_id = 0;`
177			`always @(posedge i_clk)`
178			`if ((i_wb_stb)&&(!o_wb_stall))`
179			`transaction_id <= transaction_id + 1'b1;`
180
181			`assign fifo_head = transaction_id;`
182
183			`wire [(DW/8-1):0] no_sel;`
184			`wire [(LG_AXI_DW-4):0] axi_bottom_addr;`
185			`assign no_sel = 0;`
186			`assign axi_bottom_addr = 0;`
187
188
189	2	dgisselq	`// Write address logic`
190
191	8	dgisselq	`initial o_axi_awvalid = 0;`
192	2	dgisselq	`always @(posedge i_clk)`
193	5	dgisselq	`o_axi_awvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)`
194	8	dgisselq	`\|\|(o_axi_awvalid)&&(!i_axi_awready);`
195	2	dgisselq
196	6	dgisselq	`generate`
197	8	dgisselq
198			`initial o_axi_awid = -1;`
199			`always @(posedge i_clk)`
200			`if ((i_wb_stb)&&(!o_wb_stall))`
201			`o_axi_awid <= transaction_id;`
202
203			`if (C_AXI_DATA_WIDTH == DW)`
204	6	dgisselq	`begin`
205			`always @(posedge i_clk)`
206	8	dgisselq	`if ((i_wb_stb)&&(!o_wb_stall)) // 26 bit address becomes 28 bit ...`
207			`o_axi_awaddr <= { i_wb_addr[AW-1:0], axi_bottom_addr };`
208			`end else if (C_AXI_DATA_WIDTH / DW == 2)`
209	6	dgisselq	`begin`
210	8	dgisselq
211	6	dgisselq	`always @(posedge i_clk)`
212	8	dgisselq	`if ((i_wb_stb)&&(!o_wb_stall)) // 26 bit address becomes 28 bit ...`
213			`o_axi_awaddr <= { i_wb_addr[AW-1:1], axi_bottom_addr };`
214
215			`end else if (C_AXI_DATA_WIDTH / DW == 4)`
216			`begin`
217			`always @(posedge i_clk)`
218	13	dgisselq	`if ((i_wb_stb)&&(!o_wb_stall)) // 26 bit address becomes 28 bit ...`
219			`o_axi_awaddr <= { i_wb_addr[AW-1:2], axi_bottom_addr };`
220	6	dgisselq	`end endgenerate`
221
222	2	dgisselq
223			`// Read address logic`
224	8	dgisselq	`assign o_axi_arid = o_axi_awid;`
225	5	dgisselq	`assign o_axi_araddr = o_axi_awaddr;`
226			`assign o_axi_arlen = o_axi_awlen;`
227			`assign o_axi_arsize = 3'b101; // maximum bytes per burst is 32`
228	8	dgisselq	`initial o_axi_arvalid = 1'b0;`
229	2	dgisselq	`always @(posedge i_clk)`
230	5	dgisselq	`o_axi_arvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)`
231	8	dgisselq	`\|\|(o_axi_arvalid)&&(!i_axi_arready);`
232	2	dgisselq
233			`// Write data logic`
234	4	dgisselq	`generate`
235	8	dgisselq	`if (C_AXI_DATA_WIDTH == DW)`
236	4	dgisselq	`begin`
237	8	dgisselq
238	4	dgisselq	`always @(posedge i_clk)`
239	8	dgisselq	`if ((i_wb_stb)&&(!o_wb_stall))`
240			`o_axi_wdata <= i_wb_data;`
241
242	4	dgisselq	`always @(posedge i_clk)`
243	8	dgisselq	`if ((i_wb_stb)&&(!o_wb_stall))`
244			`o_axi_wstrb<= i_wb_sel;`
245
246			`end else if (C_AXI_DATA_WIDTH/2 == DW)`
247			`begin`
248
249			`always @(posedge i_clk)`
250			`if ((i_wb_stb)&&(!o_wb_stall))`
251			`o_axi_wdata <= { i_wb_data, i_wb_data };`
252
253			`always @(posedge i_clk)`
254			`if ((i_wb_stb)&&(!o_wb_stall))`
255			`case(i_wb_addr[0])`
256			`1'b0:o_axi_wstrb<={ no_sel,i_wb_sel };`
257			`1'b1:o_axi_wstrb<={i_wb_sel, no_sel };`
258	4	dgisselq	`endcase`
259	8	dgisselq
260			`end else if (C_AXI_DATA_WIDTH/4 == DW)`
261	4	dgisselq	`begin`
262	8	dgisselq
263	4	dgisselq	`always @(posedge i_clk)`
264	8	dgisselq	`if ((i_wb_stb)&&(!o_wb_stall))`
265			`o_axi_wdata <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };`
266
267	4	dgisselq	`always @(posedge i_clk)`
268	8	dgisselq	`if ((i_wb_stb)&&(!o_wb_stall))`
269			`case(i_wb_addr[1:0])`
270			`2'b00:o_axi_wstrb<={ no_sel, no_sel, no_sel, i_wb_sel };`
271			`2'b01:o_axi_wstrb<={ no_sel, no_sel, i_wb_sel, no_sel };`
272			`2'b10:o_axi_wstrb<={ no_sel, i_wb_sel, no_sel, no_sel };`
273			`2'b11:o_axi_wstrb<={ i_wb_sel, no_sel, no_sel, no_sel };`
274			`endcase`
275
276	4	dgisselq	`end endgenerate`
277
278	5	dgisselq	`assign o_axi_wlast = 1'b1;`
279	8	dgisselq	`initial o_axi_wvalid = 0;`
280	2	dgisselq	`always @(posedge i_clk)`
281	5	dgisselq	`o_axi_wvalid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))`
282	8	dgisselq	`\|\|(o_axi_wvalid)&&(!i_axi_wready);`
283	2	dgisselq
284	8	dgisselq	`// Read data channel / response logic`
285	5	dgisselq	`assign o_axi_rready = 1'b1;`
286			`assign o_axi_bready = 1'b1;`
287	2	dgisselq
288	8	dgisselq	`wire [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;`
289			`assign n_fifo_head = fifo_head+1'b1;`
290			`assign nn_fifo_head = { fifo_head[(LGFIFOLN-1):1]+1'b1, fifo_head[0] };`
291
292
293	2	dgisselq	`wire w_fifo_full;`
294	8	dgisselq	`reg [(LGFIFOLN-1):0] fifo_tail;`
295
296	2	dgisselq	`generate`
297	8	dgisselq	`if (C_AXI_DATA_WIDTH == DW)`
298	2	dgisselq	`begin`
299	8	dgisselq	`if (STRICT_ORDER == 0)`
300			`begin`
301			`reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];`
302	3	dgisselq
303	8	dgisselq	`always @(posedge i_clk)`
304			`if ((o_axi_rready)&&(i_axi_rvalid))`
305			`reorder_fifo_data[i_axi_rid] <= i_axi_rdata;`
306			`always @(posedge i_clk)`
307			`o_wb_data <= reorder_fifo_data[fifo_tail];`
308			`end else begin`
309			`reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data;`
310	6	dgisselq
311	8	dgisselq	`always @(posedge i_clk)`
312			`reorder_fifo_data <= i_axi_rdata;`
313			`always @(posedge i_clk)`
314			`o_wb_data <= reorder_fifo_data;`
315			`end`
316			`end else if (C_AXI_DATA_WIDTH / DW == 2)`
317			`begin`
318			`reg reorder_fifo_addr [0:(FIFOLN-1)];`
319
320			`reg low_addr;`
321			`always @(posedge i_clk)`
322			`if ((i_wb_stb)&&(!o_wb_stall))`
323			`low_addr <= i_wb_addr[0];`
324			`always @(posedge i_clk)`
325			`if ((o_axi_arvalid)&&(i_axi_arready))`
326			`reorder_fifo_addr[o_axi_arid] <= low_addr;`
327
328			`if (STRICT_ORDER == 0)`
329	4	dgisselq	`begin`
330	8	dgisselq	`reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];`
331	3	dgisselq
332	8	dgisselq	`always @(posedge i_clk)`
333			`if ((o_axi_rready)&&(i_axi_rvalid))`
334			`reorder_fifo_data[i_axi_rid] <= i_axi_rdata;`
335			`always @(posedge i_clk)`
336			`reorder_fifo_data[i_axi_rid] <= i_axi_rdata;`
337			`always @(posedge i_clk)`
338			`case(reorder_fifo_addr[fifo_tail])`
339			`1'b0: o_wb_data <=reorder_fifo_data[fifo_tail][( DW-1): 0 ];`
340			`1'b1: o_wb_data <=reorder_fifo_data[fifo_tail][(2*DW-1):( DW)];`
341			`endcase`
342			`end else begin`
343			`reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data;`
344	3	dgisselq
345	4	dgisselq	`always @(posedge i_clk)`
346	8	dgisselq	`reorder_fifo_data <= i_axi_rdata;`
347	4	dgisselq	`always @(posedge i_clk)`
348	8	dgisselq	`case(reorder_fifo_addr[fifo_tail])`
349			`1'b0: o_wb_data <=reorder_fifo_data[( DW-1): 0 ];`
350			`1'b1: o_wb_data <=reorder_fifo_data[(2*DW-1):( DW)];`
351			`endcase`
352			`end`
353			`end else if (C_AXI_DATA_WIDTH / DW == 4)`
354			`begin`
355			`reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];`
356	3	dgisselq
357	8	dgisselq
358			`reg [1:0] low_addr;`
359			`always @(posedge i_clk)`
360			`if ((i_wb_stb)&&(!o_wb_stall))`
361			`low_addr <= i_wb_addr[1:0];`
362			`always @(posedge i_clk)`
363			`if ((o_axi_arvalid)&&(i_axi_arready))`
364			`reorder_fifo_addr[o_axi_arid] <= low_addr;`
365
366			`if (STRICT_ORDER == 0)`
367			`begin`
368			`reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];`
369
370	4	dgisselq	`always @(posedge i_clk)`
371	8	dgisselq	`if ((o_axi_rready)&&(i_axi_rvalid))`
372			`reorder_fifo_data[i_axi_rid] <= i_axi_rdata;`
373			`always @(posedge i_clk)`
374	6	dgisselq	`case(reorder_fifo_addr[fifo_tail][1:0])`
375	8	dgisselq	`2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][( DW-1): 0 ];`
376			`2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][(2*DW-1):( DW)];`
377			`2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][(3DW-1):(2DW)];`
378			`2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][(4DW-1):(3DW)];`
379	4	dgisselq	`endcase`
380	8	dgisselq	`end else begin`
381			`reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data;`
382	4	dgisselq
383			`always @(posedge i_clk)`
384	8	dgisselq	`reorder_fifo_data <= i_axi_rdata;`
385			`always @(posedge i_clk)`
386			`case(reorder_fifo_addr[fifo_tail][1:0])`
387			`2'b00: o_wb_data <=reorder_fifo_data[( DW-1): 0];`
388			`2'b01: o_wb_data <=reorder_fifo_data[(2*DW-1):( DW)];`
389			`2'b10: o_wb_data <=reorder_fifo_data[(3DW-1):(2DW)];`
390			`2'b11: o_wb_data <=reorder_fifo_data[(4DW-1):(3DW)];`
391			`endcase`
392	4	dgisselq	`end`
393	8	dgisselq	`end`
394	4	dgisselq
395	8	dgisselq	`endgenerate`
396	4	dgisselq
397	13	dgisselq	`// verilator lint_off UNUSED`
398	8	dgisselq	`wire axi_rd_ack, axi_wr_ack, axi_ard_req, axi_awr_req, axi_wr_req,`
399			`axi_rd_err, axi_wr_err;`
400	13	dgisselq	`// verilator lint_on UNUSED`
401
402	8	dgisselq	`//`
403			`assign axi_ard_req = (o_axi_arvalid)&&(i_axi_arready);`
404			`assign axi_awr_req = (o_axi_awvalid)&&(i_axi_awready);`
405			`assign axi_wr_req = (o_axi_wvalid )&&(i_axi_wready);`
406			`//`
407			`assign axi_rd_ack = (i_axi_rvalid)&&(o_axi_rready);`
408			`assign axi_wr_ack = (i_axi_bvalid)&&(o_axi_bready);`
409			`assign axi_rd_err = (axi_rd_ack)&&(i_axi_rresp[1]);`
410			`assign axi_wr_err = (axi_wr_ack)&&(i_axi_bresp[1]);`
411	2	dgisselq
412	8	dgisselq	`//`
413			`// We're going to need a FIFO on the return to make certain that we can`
414			`// select the right bits from the return value, in the case where`
415			`// DW != the axi data width.`
416			`//`
417			`// If we aren't using a strict order, this FIFO is can be used as a`
418			`// reorder buffer as well, to place our out of order bus responses`
419			`// back into order. Responses on the wishbone, however, are always`
420			`// done in order.`
421			`generate`
422			`if (STRICT_ORDER == 0)`
423			`begin`
424			`// Reorder FIFO`
425			`//`
426			`// FIFO reorder buffer`
427			`reg [(FIFOLN-1):0] reorder_fifo_valid;`
428			`reg [(FIFOLN-1):0] reorder_fifo_err;`
429	2	dgisselq
430	8	dgisselq	`initial reorder_fifo_valid = 0;`
431			`initial reorder_fifo_err = 0;`
432
433
434			`initial fifo_tail = 0;`
435			`initial o_wb_ack = 0;`
436			`initial o_wb_err = 0;`
437	2	dgisselq	`always @(posedge i_clk)`
438			`begin`
439	8	dgisselq	`if (axi_rd_ack)`
440	2	dgisselq	`begin`
441	5	dgisselq	`reorder_fifo_valid[i_axi_rid] <= 1'b1;`
442	8	dgisselq	`reorder_fifo_err[i_axi_rid] <= axi_rd_err;`
443	2	dgisselq	`end`
444	8	dgisselq	`if (axi_wr_ack)`
445	2	dgisselq	`begin`
446	5	dgisselq	`reorder_fifo_valid[i_axi_bid] <= 1'b1;`
447	8	dgisselq	`reorder_fifo_err[i_axi_bid] <= axi_wr_err;`
448	2	dgisselq	`end`
449
450			`if (reorder_fifo_valid[fifo_tail])`
451			`begin`
452	8	dgisselq	`o_wb_ack <= (!wb_abort)&&(!reorder_fifo_err[fifo_tail]);`
453			`o_wb_err <= (!wb_abort)&&( reorder_fifo_err[fifo_tail]);`
454			`fifo_tail <= fifo_tail + 1'b1;`
455	2	dgisselq	`reorder_fifo_valid[fifo_tail] <= 1'b0;`
456			`reorder_fifo_err[fifo_tail] <= 1'b0;`
457			`end else begin`
458			`o_wb_ack <= 1'b0;`
459			`o_wb_err <= 1'b0;`
460			`end`
461
462			`if (!i_wb_cyc)`
463			`begin`
464	8	dgisselq	`// reorder_fifo_valid <= 0;`
465			`// reorder_fifo_err <= 0;`
466	2	dgisselq	`o_wb_err <= 1'b0;`
467			`o_wb_ack <= 1'b0;`
468			`end`
469			`end`
470
471	3	dgisselq	`reg r_fifo_full;`
472	8	dgisselq	`initial r_fifo_full = 0;`
473	2	dgisselq	`always @(posedge i_clk)`
474			`begin`
475	8	dgisselq	`if ((i_wb_stb)&&(!o_wb_stall)`
476	2	dgisselq	`&&(reorder_fifo_valid[fifo_tail]))`
477			`r_fifo_full <= (fifo_tail==n_fifo_head);`
478	8	dgisselq	`else if ((i_wb_stb)&&(!o_wb_stall))`
479	2	dgisselq	`r_fifo_full <= (fifo_tail==nn_fifo_head);`
480			`else if (reorder_fifo_valid[fifo_tail])`
481			`r_fifo_full <= 1'b0;`
482			`else`
483			`r_fifo_full <= (fifo_tail==n_fifo_head);`
484			`end`
485			`assign w_fifo_full = r_fifo_full;`
486			`end else begin`
487	6	dgisselq	`//`
488	8	dgisselq	`// Strict ordering`
489	6	dgisselq	`//`
490	8	dgisselq	`reg reorder_fifo_valid;`
491			`reg reorder_fifo_err;`
492
493			`initial reorder_fifo_valid = 1'b0;`
494			`initial reorder_fifo_err = 1'b0;`
495	2	dgisselq	`always @(posedge i_clk)`
496	8	dgisselq	`if (axi_rd_ack)`
497			`begin`
498			`reorder_fifo_valid <= 1'b1;`
499			`reorder_fifo_err <= axi_rd_err;`
500			`end else if (axi_wr_ack)`

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