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////////////////////////////////////////////////////////////////////////////////
//
// Filename:    wbm2axisp.v
//
// Project:     Pipelined Wishbone to AXI converter
//
// Purpose:     The B4 Wishbone SPEC allows transactions at a speed as fast as
//              one per clock.  The AXI bus allows transactions at a speed of
//      one read and one write transaction per clock.  These capabilities work
//      by allowing requests to take place prior to responses, such that the
//      requests might go out at once per clock and take several clocks, and
//      the responses may start coming back several clocks later.  In other
//      words, both protocols allow multiple transactions to be "in flight" at
//      the same time.  Current wishbone to AXI converters, however, handle only
//      one transaction at a time: initiating the transaction, and then waiting
//      for the transaction to complete before initiating the next.
//
//      The purpose of this core is to maintain the speed of both busses, while
//      transiting from the Wishbone (as master) to the AXI bus (as slave) and
//      back again.
//
//      Since the AXI bus allows transactions to be reordered, whereas the 
//      wishbone does not, this core can be configured to reorder return
//      transactions as well.
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module wbm2axisp #(
        parameter C_AXI_ID_WIDTH        = 6, // The AXI id width used for R&W
                                             // This is an int between 1-16
        parameter C_AXI_DATA_WIDTH      = 128,// Width of the AXI R&W data
        parameter AW                    = 28,   // Wishbone address width
        parameter DW                    = 32,   // Wishbone data width
        parameter STRICT_ORDER          = 0      // Reorder, or not? 0 -> Reorder
        ) (
        input                           i_clk,  // System clock
        input                           i_reset,// Wishbone reset signal
 
// AXI write address channel signals
        input                           i_axi_wready, // Slave is ready to accept
        output  wire    [C_AXI_ID_WIDTH-1:0]     o_axi_wid,      // Write ID
        output  reg     [AW-1:0] o_axi_waddr,    // Write address
        output  wire    [7:0]            o_axi_wlen,     // Write Burst Length
        output  wire    [2:0]            o_axi_wsize,    // Write Burst size
        output  wire    [1:0]            o_axi_wburst,   // Write Burst type
        output  wire    [1:0]            o_axi_wlock,    // Write lock type
        output  wire    [3:0]            o_axi_wcache,   // Write Cache type
        output  wire    [2:0]            o_axi_wprot,    // Write Protection type
        output  reg                     o_axi_wvalid,   // Write address valid
 
// AXI write data channel signals
        input                           i_axi_wd_wready,  // Write data ready
        output  wire    [C_AXI_ID_WIDTH-1:0]     o_axi_wd_wid,   // Write ID tag
        output  reg     [C_AXI_DATA_WIDTH-1:0]   o_axi_wd_data,  // Write data
        output  reg     [C_AXI_DATA_WIDTH/8-1:0] o_axi_wd_strb,  // Write strobes
        output  wire                    o_axi_wd_last,  // Last write transaction   
        output  reg                     o_axi_wd_valid, // Write valid
 
// AXI write response channel signals
        input   [C_AXI_ID_WIDTH-1:0]     i_axi_wd_bid,   // Response ID
        input   [1:0]                    i_axi_wd_bresp, // Write response
        input                           i_axi_wd_bvalid,  // Write reponse valid
        output  wire                    o_axi_wd_bready,  // Response ready
 
// AXI read address channel signals
        input                           i_axi_rready,   // Read address ready
        output  wire    [C_AXI_ID_WIDTH-1:0]     o_axi_rid,      // Read ID
        output  wire    [AW-1:0] o_axi_raddr,    // Read address
        output  wire    [7:0]            o_axi_rlen,     // Read Burst Length
        output  wire    [2:0]            o_axi_rsize,    // Read Burst size
        output  wire    [1:0]            o_axi_rburst,   // Read Burst type
        output  wire    [1:0]            o_axi_rlock,    // Read lock type
        output  wire    [3:0]            o_axi_rcache,   // Read Cache type
        output  wire    [2:0]            o_axi_rprot,    // Read Protection type
        output  reg                     o_axi_rvalid,   // Read address valid
 
// AXI read data channel signals   
        input   [C_AXI_ID_WIDTH-1:0]     i_axi_rd_bid,     // Response ID
        input   [1:0]                    i_axi_rd_rresp,   // Read response
        input                           i_axi_rd_rvalid,  // Read reponse valid
        input   [C_AXI_DATA_WIDTH-1:0]           i_axi_rd_data,    // Read data
        input                           i_axi_rd_last,    // Read last
        output  wire                    o_axi_rd_rready,  // Read Response ready
 
        // We'll share the clock and the reset
        input                           i_wb_cyc,
        input                           i_wb_stb,
        input                           i_wb_we,
        input           [AW-1:0] i_wb_addr,
        input           [DW-1:0] i_wb_data,
        input           [3:0]            i_wb_sel,
        output  reg                     o_wb_ack,
        output  wire                    o_wb_stall,
        output  reg     [DW-1:0] o_wb_data,
        output  reg                     o_wb_err
);
 
//*****************************************************************************
// Parameter declarations
//*****************************************************************************
 
        localparam      CTL_SIG_WIDTH   = 3;    // Control signal width
        localparam      RD_STS_WIDTH    = 16;   // Read status signal width
        localparam      WR_STS_WIDTH    = 16;   // Write status signal width
 
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
 
        wire                                    cmd_en;
        wire    [2:0]                            cmd;
        wire    [7:0]                            blen;
        wire    [31:0]                           addr;
        wire    [CTL_SIG_WIDTH-1:0]              ctl;
        wire                                    cmd_ack;
 
// User interface write ports
        wire                                    wrdata_vld;
        wire    [C_AXI_DATA_WIDTH-1:0]           wrdata;
        wire    [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld;
        wire                                    wrdata_cmptd;
        wire                                    wrdata_rdy;
        wire                                    wrdata_sts_vld;
        wire    [WR_STS_WIDTH-1:0]              wrdata_sts;
 
// User interface read ports
        wire                                    rddata_rdy;
        wire                                    rddata_vld;
        wire    [C_AXI_DATA_WIDTH-1:0]           rddata;
        wire    [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld;
        wire                                    rddata_cmptd;
        wire    [RD_STS_WIDTH-1:0]               rddata_sts;
        reg                                     cmptd_one_wr;
        reg                                     cmptd_one_rd;
 
 
// Things we're not changing ...
        assign o_axi_wlen = 8'h0;       // Burst length is one
        assign o_axi_wsize = 3'b101;    // maximum bytes per burst is 32
        assign o_axi_wburst = 2'b01;    // Incrementing address (ignored)
        assign o_axi_rburst = 2'b01;    // Incrementing address (ignored)
        assign o_axi_wlock  = 2'b00;    // Normal signaling
        assign o_axi_rlock  = 2'b00;    // Normal signaling
        assign o_axi_wcache = 4'h2;     // Normal: no cache, no buffer
        assign o_axi_rcache = 4'h2;     // Normal: no cache, no buffer
        assign o_axi_wprot  = 3'h010;   // Unpriviledged, unsecure, data access
        assign o_axi_rprot  = 3'h010;   // Unpriviledged, unsecure, data access
 
// Command logic
        assign  o_wb_stall = (i_wb_we)&&(~i_axi_wready)
                        ||(~i_wb_we)&&(!i_axi_rready);
// Write address logic
 
        always @(posedge i_clk)
                o_axi_wvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)
                                ||(o_wb_stall)&&(o_axi_wvalid)&&(!i_axi_wready);
        always @(posedge i_clk)
                if (!o_wb_stall)
                        o_axi_waddr <= { i_wb_addr[AW-1:2], 2'b00 }; // 28 bits
 
        reg     [5:0]    transaction_id;
        always @(posedge i_clk)
                if (!i_wb_cyc)
                        transaction_id <= 6'h00;
                else if ((i_wb_stb)&&(~o_wb_stall))
                        transaction_id <= transaction_id + 6'h01;
        assign  o_axi_wid = transaction_id;
 
// Read address logic
        assign  o_axi_rid = transaction_id;
        assign  o_axi_raddr = o_axi_waddr;
        assign  o_axi_rlen  = o_axi_wlen;
        assign  o_axi_rsize = 3'b101;   // maximum bytes per burst is 32
        always @(posedge i_clk)
                o_axi_rvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)
                        ||(o_wb_stall)&&(o_axi_rvalid)&&(!i_axi_rready);
 
 
// Write data logic
        assign  o_axi_wd_wid = transaction_id;
        always @(posedge i_clk)
                if (!o_wb_stall)
                        o_axi_wd_data <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
        always @(posedge i_clk)
                if (!o_wb_stall)
                case(i_wb_addr[1:0])
                2'b00:o_axi_wd_strb<={     4'h0,     4'h0,     4'h0, i_wb_sel };
                2'b01:o_axi_wd_strb<={     4'h0,     4'h0, i_wb_sel,     4'h0 };
                2'b10:o_axi_wd_strb<={     4'h0, i_wb_sel,     4'h0,     4'h0 };
                2'b11:o_axi_wd_strb<={ i_wb_sel,     4'h0,     4'h0,     4'h0 };
                endcase
        assign  o_axi_wd_last = 1'b1;
        always @(posedge i_clk)
                o_axi_wd_valid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))
                        ||(o_wb_stall)&&(o_axi_wd_valid)&&(!i_axi_wd_wready);
 
// Read data channel / response logic
        assign  o_axi_rd_rready = 1'b1;
        assign  o_axi_wd_bready = 1'b1;
 
        wire    w_fifo_full;
        generate
        if (STRICT_ORDER == 0)
        begin
                // Reorder FIFO
                //
                localparam      LGFIFOLN = C_AXI_ID_WIDTH;
                localparam      FIFOLN = (1<<LGFIFOLN);
                // FIFO reorder buffer
                reg     [(LGFIFOLN-1):0] fifo_tail;
                reg     [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
                reg     [(FIFOLN-1):0]   reorder_fifo_valid;
                reg     [(FIFOLN-1):0]   reorder_fifo_err;
                reg     [1:0]            reorder_fifo_addr [0:(FIFOLN-1)];
 
 
                reg     [1:0]    low_addr;
                always @(posedge i_clk)
                        if ((i_wb_stb)&&(!o_wb_stall))
                                low_addr <= i_wb_addr[1:0];
                always @(posedge i_clk)
                        if ((o_axi_rvalid)&&(i_axi_rready))
                                reorder_fifo_addr[o_axi_rid] <= low_addr;
 
 
                wire    [(LGFIFOLN-1):0] fifo_head;
                assign  fifo_head = transaction_id;
 
                // Let's do some math to figure out where the FIFO head will
                // point to next, but let's also insist that it be LGFIFOLN
                // bits in size as well.  This'll be part of the fifo_full
                // calculation below.
                wire    [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;
                assign  n_fifo_head = fifo_head+1'b1;
 
                always @(posedge i_clk)
                begin
                        if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
                                reorder_fifo_data[i_axi_rd_bid]<= i_axi_rd_data;
                        if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
                        begin
                                reorder_fifo_valid[i_axi_rd_bid] <= 1'b1;
                                reorder_fifo_err[i_axi_rd_bid] <= i_axi_rd_rresp[1];
                        end
                        if ((i_axi_wd_bvalid)&&(o_axi_wd_bready))
                        begin
                                reorder_fifo_valid[i_axi_wd_bid] <= 1'b1;
                                reorder_fifo_err[i_axi_wd_bid] <= i_axi_wd_bresp[1];
                        end
 
                        case(reorder_fifo_addr[1:0])
                        2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
                        2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
                        2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
                        2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];
                        endcase
 
                        if (reorder_fifo_valid[fifo_tail])
                        begin
                                o_wb_ack <= 1'b1;
                                o_wb_err <= reorder_fifo_err[fifo_tail];
                                fifo_tail <= fifo_tail + 6'h1;
                                reorder_fifo_valid[fifo_tail] <= 1'b0;
                                reorder_fifo_err[fifo_tail]   <= 1'b0;
                        end else begin
                                o_wb_ack <= 1'b0;
                                o_wb_err <= 1'b0;
                        end
 
                        if (!i_wb_cyc)
                        begin
                                reorder_fifo_valid <= {(FIFOLN){1'b0}};
                                reorder_fifo_err   <= {(FIFOLN){1'b0}};
                                fifo_tail <= 6'h0;
                                o_wb_err <= 1'b0;
                                o_wb_ack <= 1'b0;
                        end
                end
 
                reg     r_fifo_full;
                always @(posedge i_clk)
                begin
                        if (!i_wb_cyc)
                                r_fifo_full <= 1'b0;
                        else if ((i_wb_stb)&&(~o_wb_stall)
                                        &&(reorder_fifo_valid[fifo_tail]))
                                r_fifo_full <= (fifo_tail==n_fifo_head);
                        else if ((i_wb_stb)&&(~o_wb_stall))
                                r_fifo_full <= (fifo_tail==nn_fifo_head);
                        else if (reorder_fifo_valid[fifo_tail])
                                r_fifo_full <= 1'b0;
                        else
                                r_fifo_full <= (fifo_tail==n_fifo_head);
                end
                assign w_fifo_full = r_fifo_full;
        end else begin
                assign w_fifo_full = 1'b0;
                always @(posedge i_clk)
                        o_wb_data <= i_axi_rd_data;
                always @(posedge i_clk)
                        o_wb_ack <= ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
                                  ||((i_axi_wd_bvalid)&&(o_axi_wd_bready));
                always @(posedge i_clk)
                        o_wb_err <= (!i_wb_cyc)&&((o_wb_err)
                                ||((i_axi_rd_rvalid)&&(i_axi_rd_rresp[1]))
                                ||((i_axi_wd_bvalid)&&(i_axi_wd_bresp[1])));
        end endgenerate
 
 
        // Now, the difficult signal ... the stall signal
        // Let's build for a single cycle input ... and only stall if something
        // outgoing is valid and nothing is ready.
        assign  o_wb_stall = (i_wb_cyc)&&(
                                (w_fifo_full)
                                ||((o_axi_wvalid)&&(!i_axi_wready))
                                ||((o_axi_wd_valid)&&(!i_axi_wd_wready))
                                ||((o_axi_rvalid)&&(!i_axi_rready)));
endmodule

Line No.	Rev	Author	Line
1	2	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: wbm2axisp.v`
4			`//`
5			`// Project: Pipelined Wishbone to AXI converter`
6			`//`
7			`// Purpose: The B4 Wishbone SPEC allows transactions at a speed as fast as`
8			`// one per clock. The AXI bus allows transactions at a speed of`
9			`// one read and one write transaction per clock. These capabilities work`
10			`// by allowing requests to take place prior to responses, such that the`
11			`// requests might go out at once per clock and take several clocks, and`
12			`// the responses may start coming back several clocks later. In other`
13			`// words, both protocols allow multiple transactions to be "in flight" at`
14			`// the same time. Current wishbone to AXI converters, however, handle only`
15			`// one transaction at a time: initiating the transaction, and then waiting`
16			`// for the transaction to complete before initiating the next.`
17			`//`
18			`// The purpose of this core is to maintain the speed of both busses, while`
19			`// transiting from the Wishbone (as master) to the AXI bus (as slave) and`
20			`// back again.`
21			`//`
22			`// Since the AXI bus allows transactions to be reordered, whereas the`
23			`// wishbone does not, this core can be configured to reorder return`
24			`// transactions as well.`
25			`//`
26			`// Creator: Dan Gisselquist, Ph.D.`
27			`// Gisselquist Technology, LLC`
28			`//`
29			`////////////////////////////////////////////////////////////////////////////////`
30			`//`
31	3	dgisselq	`// Copyright (C) 2016, Gisselquist Technology, LLC`
32	2	dgisselq	`//`
33			`// This program is free software (firmware): you can redistribute it and/or`
34			`// modify it under the terms of the GNU General Public License as published`
35			`// by the Free Software Foundation, either version 3 of the License, or (at`
36			`// your option) any later version.`
37			`//`
38			`// This program is distributed in the hope that it will be useful, but WITHOUT`
39			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
40			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
41			`// for more details.`
42			`//`
43			`// You should have received a copy of the GNU General Public License along`
44			`// with this program. (It's in the $(ROOT)/doc directory, run make with no`
45			`// target there if the PDF file isn't present.) If not, see`
46			`// <http://www.gnu.org/licenses/> for a copy.`
47			`//`
48			`// License: GPL, v3, as defined and found on www.gnu.org,`
49			`// http://www.gnu.org/licenses/gpl.html`
50			`//`
51			`//`
52			`////////////////////////////////////////////////////////////////////////////////`
53			`//`
54			`//`
55			`module wbm2axisp #(`
56			`parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W`
57			`// This is an int between 1-16`
58			`parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data`
59			`parameter AW = 28, // Wishbone address width`
60	3	dgisselq	`parameter DW = 32, // Wishbone data width`
61			`parameter STRICT_ORDER = 0 // Reorder, or not? 0 -> Reorder`
62	2	dgisselq	`) (`
63			`input i_clk, // System clock`
64			`input i_reset,// Wishbone reset signal`
65
66			`// AXI write address channel signals`
67			`input i_axi_wready, // Slave is ready to accept`
68			`output wire [C_AXI_ID_WIDTH-1:0] o_axi_wid, // Write ID`
69			`output reg [AW-1:0] o_axi_waddr, // Write address`
70			`output wire [7:0] o_axi_wlen, // Write Burst Length`
71			`output wire [2:0] o_axi_wsize, // Write Burst size`
72			`output wire [1:0] o_axi_wburst, // Write Burst type`
73			`output wire [1:0] o_axi_wlock, // Write lock type`
74			`output wire [3:0] o_axi_wcache, // Write Cache type`
75			`output wire [2:0] o_axi_wprot, // Write Protection type`
76			`output reg o_axi_wvalid, // Write address valid`
77
78			`// AXI write data channel signals`
79			`input i_axi_wd_wready, // Write data ready`
80			`output wire [C_AXI_ID_WIDTH-1:0] o_axi_wd_wid, // Write ID tag`
81	3	dgisselq	`output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wd_data, // Write data`
82			`output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wd_strb, // Write strobes`
83	2	dgisselq	`output wire o_axi_wd_last, // Last write transaction`
84			`output reg o_axi_wd_valid, // Write valid`
85
86			`// AXI write response channel signals`
87			`input [C_AXI_ID_WIDTH-1:0] i_axi_wd_bid, // Response ID`
88			`input [1:0] i_axi_wd_bresp, // Write response`
89			`input i_axi_wd_bvalid, // Write reponse valid`
90			`output wire o_axi_wd_bready, // Response ready`
91
92			`// AXI read address channel signals`
93			`input i_axi_rready, // Read address ready`
94			`output wire [C_AXI_ID_WIDTH-1:0] o_axi_rid, // Read ID`
95			`output wire [AW-1:0] o_axi_raddr, // Read address`
96			`output wire [7:0] o_axi_rlen, // Read Burst Length`
97			`output wire [2:0] o_axi_rsize, // Read Burst size`
98			`output wire [1:0] o_axi_rburst, // Read Burst type`
99			`output wire [1:0] o_axi_rlock, // Read lock type`
100			`output wire [3:0] o_axi_rcache, // Read Cache type`
101			`output wire [2:0] o_axi_rprot, // Read Protection type`
102			`output reg o_axi_rvalid, // Read address valid`
103
104			`// AXI read data channel signals`
105			`input [C_AXI_ID_WIDTH-1:0] i_axi_rd_bid, // Response ID`
106			`input [1:0] i_axi_rd_rresp, // Read response`
107			`input i_axi_rd_rvalid, // Read reponse valid`
108	3	dgisselq	`input [C_AXI_DATA_WIDTH-1:0] i_axi_rd_data, // Read data`
109	2	dgisselq	`input i_axi_rd_last, // Read last`
110			`output wire o_axi_rd_rready, // Read Response ready`
111
112			`// We'll share the clock and the reset`
113	3	dgisselq	`input i_wb_cyc,`
114			`input i_wb_stb,`
115			`input i_wb_we,`
116			`input [AW-1:0] i_wb_addr,`
117			`input [DW-1:0] i_wb_data,`
118			`input [3:0] i_wb_sel,`
119			`output reg o_wb_ack,`
120			`output wire o_wb_stall,`
121			`output reg [DW-1:0] o_wb_data,`
122			`output reg o_wb_err`
123	2	dgisselq	`);`
124
125			`//*****************************************************************************`
126			`// Parameter declarations`
127			`//*****************************************************************************`
128
129			`localparam CTL_SIG_WIDTH = 3; // Control signal width`
130			`localparam RD_STS_WIDTH = 16; // Read status signal width`
131			`localparam WR_STS_WIDTH = 16; // Write status signal width`
132
133			`//*****************************************************************************`
134			`// Internal register and wire declarations`
135			`//*****************************************************************************`
136
137			`wire cmd_en;`
138			`wire [2:0] cmd;`
139			`wire [7:0] blen;`
140			`wire [31:0] addr;`
141			`wire [CTL_SIG_WIDTH-1:0] ctl;`
142			`wire cmd_ack;`
143
144			`// User interface write ports`
145			`wire wrdata_vld;`
146			`wire [C_AXI_DATA_WIDTH-1:0] wrdata;`
147			`wire [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld;`
148			`wire wrdata_cmptd;`
149			`wire wrdata_rdy;`
150			`wire wrdata_sts_vld;`
151			`wire [WR_STS_WIDTH-1:0] wrdata_sts;`
152
153			`// User interface read ports`
154			`wire rddata_rdy;`
155			`wire rddata_vld;`
156			`wire [C_AXI_DATA_WIDTH-1:0] rddata;`
157			`wire [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld;`
158			`wire rddata_cmptd;`
159			`wire [RD_STS_WIDTH-1:0] rddata_sts;`
160			`reg cmptd_one_wr;`
161			`reg cmptd_one_rd;`
162
163
164			`// Things we're not changing ...`
165			`assign o_axi_wlen = 8'h0; // Burst length is one`
166			`assign o_axi_wsize = 3'b101; // maximum bytes per burst is 32`
167			`assign o_axi_wburst = 2'b01; // Incrementing address (ignored)`
168			`assign o_axi_rburst = 2'b01; // Incrementing address (ignored)`
169			`assign o_axi_wlock = 2'b00; // Normal signaling`
170			`assign o_axi_rlock = 2'b00; // Normal signaling`
171			`assign o_axi_wcache = 4'h2; // Normal: no cache, no buffer`
172			`assign o_axi_rcache = 4'h2; // Normal: no cache, no buffer`
173			`assign o_axi_wprot = 3'h010; // Unpriviledged, unsecure, data access`
174			`assign o_axi_rprot = 3'h010; // Unpriviledged, unsecure, data access`
175
176			`// Command logic`
177			`assign o_wb_stall = (i_wb_we)&&(~i_axi_wready)`
178			`\|\|(~i_wb_we)&&(!i_axi_rready);`
179			`// Write address logic`
180
181			`always @(posedge i_clk)`
182			`o_axi_wvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)`
183			`\|\|(o_wb_stall)&&(o_axi_wvalid)&&(!i_axi_wready);`
184			`always @(posedge i_clk)`
185			`if (!o_wb_stall)`
186			`o_axi_waddr <= { i_wb_addr[AW-1:2], 2'b00 }; // 28 bits`
187
188			`reg [5:0] transaction_id;`
189			`always @(posedge i_clk)`
190			`if (!i_wb_cyc)`
191			`transaction_id <= 6'h00;`
192			`else if ((i_wb_stb)&&(~o_wb_stall))`
193			`transaction_id <= transaction_id + 6'h01;`
194			`assign o_axi_wid = transaction_id;`
195
196			`// Read address logic`
197			`assign o_axi_rid = transaction_id;`
198			`assign o_axi_raddr = o_axi_waddr;`
199			`assign o_axi_rlen = o_axi_wlen;`
200			`assign o_axi_rsize = 3'b101; // maximum bytes per burst is 32`
201			`always @(posedge i_clk)`
202			`o_axi_rvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)`
203			`\|\|(o_wb_stall)&&(o_axi_rvalid)&&(!i_axi_rready);`
204
205
206			`// Write data logic`
207			`assign o_axi_wd_wid = transaction_id;`
208			`always @(posedge i_clk)`
209			`if (!o_wb_stall)`
210	3	dgisselq	`o_axi_wd_data <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };`
211	2	dgisselq	`always @(posedge i_clk)`
212			`if (!o_wb_stall)`
213			`case(i_wb_addr[1:0])`
214			`2'b00:o_axi_wd_strb<={ 4'h0, 4'h0, 4'h0, i_wb_sel };`
215			`2'b01:o_axi_wd_strb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 };`
216			`2'b10:o_axi_wd_strb<={ 4'h0, i_wb_sel, 4'h0, 4'h0 };`
217			`2'b11:o_axi_wd_strb<={ i_wb_sel, 4'h0, 4'h0, 4'h0 };`
218			`endcase`
219			`assign o_axi_wd_last = 1'b1;`
220			`always @(posedge i_clk)`
221			`o_axi_wd_valid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))`
222			`\|\|(o_wb_stall)&&(o_axi_wd_valid)&&(!i_axi_wd_wready);`
223
224			`// Read data channel / response logic`
225			`assign o_axi_rd_rready = 1'b1;`
226			`assign o_axi_wd_bready = 1'b1;`
227
228			`wire w_fifo_full;`
229			`generate`
230			`if (STRICT_ORDER == 0)`
231			`begin`
232			`// Reorder FIFO`
233			`//`
234			`localparam LGFIFOLN = C_AXI_ID_WIDTH;`
235			`localparam FIFOLN = (1<<LGFIFOLN);`
236			`// FIFO reorder buffer`
237	3	dgisselq	`reg [(LGFIFOLN-1):0] fifo_tail;`
238			`reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];`
239			`reg [(FIFOLN-1):0] reorder_fifo_valid;`
240			`reg [(FIFOLN-1):0] reorder_fifo_err;`
241			`reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];`
242
243
244			`reg [1:0] low_addr;`
245			`always @(posedge i_clk)`
246			`if ((i_wb_stb)&&(!o_wb_stall))`
247			`low_addr <= i_wb_addr[1:0];`
248			`always @(posedge i_clk)`
249			`if ((o_axi_rvalid)&&(i_axi_rready))`
250			`reorder_fifo_addr[o_axi_rid] <= low_addr;`
251
252
253			`wire [(LGFIFOLN-1):0] fifo_head;`
254	2	dgisselq	`assign fifo_head = transaction_id;`
255
256			`// Let's do some math to figure out where the FIFO head will`
257			`// point to next, but let's also insist that it be LGFIFOLN`
258			`// bits in size as well. This'll be part of the fifo_full`
259			`// calculation below.`
260			`wire [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;`
261			`assign n_fifo_head = fifo_head+1'b1;`
262
263			`always @(posedge i_clk)`
264			`begin`
265			`if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))`
266			`reorder_fifo_data[i_axi_rd_bid]<= i_axi_rd_data;`
267			`if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))`
268			`begin`
269			`reorder_fifo_valid[i_axi_rd_bid] <= 1'b1;`
270	3	dgisselq	`reorder_fifo_err[i_axi_rd_bid] <= i_axi_rd_rresp[1];`
271	2	dgisselq	`end`
272			`if ((i_axi_wd_bvalid)&&(o_axi_wd_bready))`
273			`begin`
274	3	dgisselq	`reorder_fifo_valid[i_axi_wd_bid] <= 1'b1;`
275			`reorder_fifo_err[i_axi_wd_bid] <= i_axi_wd_bresp[1];`
276	2	dgisselq	`end`
277
278	3	dgisselq	`case(reorder_fifo_addr[1:0])`
279			`2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];`
280			`2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];`
281			`2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];`
282			`2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];`
283			`endcase`
284
285	2	dgisselq	`if (reorder_fifo_valid[fifo_tail])`
286			`begin`
287			`o_wb_ack <= 1'b1;`
288			`o_wb_err <= reorder_fifo_err[fifo_tail];`
289			`fifo_tail <= fifo_tail + 6'h1;`
290			`reorder_fifo_valid[fifo_tail] <= 1'b0;`
291			`reorder_fifo_err[fifo_tail] <= 1'b0;`
292			`end else begin`
293			`o_wb_ack <= 1'b0;`
294			`o_wb_err <= 1'b0;`
295			`end`
296
297			`if (!i_wb_cyc)`
298			`begin`
299			`reorder_fifo_valid <= {(FIFOLN){1'b0}};`
300			`reorder_fifo_err <= {(FIFOLN){1'b0}};`
301			`fifo_tail <= 6'h0;`
302			`o_wb_err <= 1'b0;`
303			`o_wb_ack <= 1'b0;`
304			`end`
305			`end`
306
307	3	dgisselq	`reg r_fifo_full;`
308	2	dgisselq	`always @(posedge i_clk)`
309			`begin`
310			`if (!i_wb_cyc)`
311			`r_fifo_full <= 1'b0;`
312			`else if ((i_wb_stb)&&(~o_wb_stall)`
313			`&&(reorder_fifo_valid[fifo_tail]))`
314			`r_fifo_full <= (fifo_tail==n_fifo_head);`
315			`else if ((i_wb_stb)&&(~o_wb_stall))`
316			`r_fifo_full <= (fifo_tail==nn_fifo_head);`
317			`else if (reorder_fifo_valid[fifo_tail])`
318			`r_fifo_full <= 1'b0;`
319			`else`
320			`r_fifo_full <= (fifo_tail==n_fifo_head);`
321			`end`
322			`assign w_fifo_full = r_fifo_full;`
323			`end else begin`
324	3	dgisselq	`assign w_fifo_full = 1'b0;`
325	2	dgisselq	`always @(posedge i_clk)`
326			`o_wb_data <= i_axi_rd_data;`
327			`always @(posedge i_clk)`
328			`o_wb_ack <= ((i_axi_rd_rvalid)&&(o_axi_rd_rready))`
329			`\|\|((i_axi_wd_bvalid)&&(o_axi_wd_bready));`
330			`always @(posedge i_clk)`
331			`o_wb_err <= (!i_wb_cyc)&&((o_wb_err)`
332	3	dgisselq	`\|\|((i_axi_rd_rvalid)&&(i_axi_rd_rresp[1]))`
333	2	dgisselq	`\|\|((i_axi_wd_bvalid)&&(i_axi_wd_bresp[1])));`
334	3	dgisselq	`end endgenerate`
335	2	dgisselq
336
337			`// Now, the difficult signal ... the stall signal`
338			`// Let's build for a single cycle input ... and only stall if something`
339			`// outgoing is valid and nothing is ready.`
340			`assign o_wb_stall = (i_wb_cyc)&&(`
341			`(w_fifo_full)`
342			`\|\|((o_axi_wvalid)&&(!i_axi_wready))`
343	3	dgisselq	`\|\|((o_axi_wd_valid)&&(!i_axi_wd_wready))`
344	2	dgisselq	`\|\|((o_axi_rvalid)&&(!i_axi_rready)));`
345			`endmodule`

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