URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

Subversion Repositories wb2axip

[/] [wb2axip/] [trunk/] [rtl/] [wbm2axisp.v] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log


////////////////////////////////////////////////////////////////////////////////
//
// Filename:    wbm2axisp.v
//
// Project:     Pipelined Wishbone to AXI converter
//
// Purpose:     The B4 Wishbone SPEC allows transactions at a speed as fast as
//              one per clock.  The AXI bus allows transactions at a speed of
//      one read and one write transaction per clock.  These capabilities work
//      by allowing requests to take place prior to responses, such that the
//      requests might go out at once per clock and take several clocks, and
//      the responses may start coming back several clocks later.  In other
//      words, both protocols allow multiple transactions to be "in flight" at
//      the same time.  Current wishbone to AXI converters, however, handle only
//      one transaction at a time: initiating the transaction, and then waiting
//      for the transaction to complete before initiating the next.
//
//      The purpose of this core is to maintain the speed of both busses, while
//      transiting from the Wishbone (as master) to the AXI bus (as slave) and
//      back again.
//
//      Since the AXI bus allows transactions to be reordered, whereas the 
//      wishbone does not, this core can be configured to reorder return
//      transactions as well.
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module wbm2axisp #(
        parameter C_AXI_ID_WIDTH        = 6, // The AXI id width used for R&W
                                             // This is an int between 1-16
        parameter C_AXI_DATA_WIDTH      = 128,// Width of the AXI R&W data
        parameter AW                    = 28,   // Wishbone address width
        parameter DW                    = 128,  // Wishbone data width
        parameter STRICT_ORDER          = 0      // Reorder, or not? 0 -> Reorder
        ) (
        input                           i_clk,  // System clock
        input                           i_reset,// Wishbone reset signal
 
// AXI write address channel signals
        input                           i_axi_awready, // Slave is ready to accept
        output  wire    [C_AXI_ID_WIDTH-1:0]     o_axi_awid,     // Write ID
        output  reg     [AW-1:0] o_axi_awaddr,   // Write address
        output  wire    [7:0]            o_axi_awlen,    // Write Burst Length
        output  wire    [2:0]            o_axi_awsize,   // Write Burst size
        output  wire    [1:0]            o_axi_awburst,  // Write Burst type
        output  wire    [1:0]            o_axi_awlock,   // Write lock type
        output  wire    [3:0]            o_axi_awcache,  // Write Cache type
        output  wire    [2:0]            o_axi_awprot,   // Write Protection type
        output  wire    [3:0]            o_axi_awqos,    // Write Quality of Svc
        output  reg                     o_axi_awvalid,  // Write address valid
 
// AXI write data channel signals
        input                           i_axi_wready,  // Write data ready
        output  reg     [C_AXI_DATA_WIDTH-1:0]   o_axi_wdata,    // Write data
        output  reg     [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb,    // Write strobes
        output  wire                    o_axi_wlast,    // Last write transaction   
        output  reg                     o_axi_wvalid,   // Write valid
 
// AXI write response channel signals
        input   [C_AXI_ID_WIDTH-1:0]     i_axi_bid,      // Response ID
        input   [1:0]                    i_axi_bresp,    // Write response
        input                           i_axi_bvalid,  // Write reponse valid
        output  wire                    o_axi_bready,  // Response ready
 
// AXI read address channel signals
        input                           i_axi_arready,  // Read address ready
        output  wire    [C_AXI_ID_WIDTH-1:0]     o_axi_arid,     // Read ID
        output  wire    [AW-1:0] o_axi_araddr,   // Read address
        output  wire    [7:0]            o_axi_arlen,    // Read Burst Length
        output  wire    [2:0]            o_axi_arsize,   // Read Burst size
        output  wire    [1:0]            o_axi_arburst,  // Read Burst type
        output  wire    [1:0]            o_axi_arlock,   // Read lock type
        output  wire    [3:0]            o_axi_arcache,  // Read Cache type
        output  wire    [2:0]            o_axi_arprot,   // Read Protection type
        output  wire    [3:0]            o_axi_arqos,    // Read Protection type
        output  reg                     o_axi_arvalid,  // Read address valid
 
// AXI read data channel signals   
        input   [C_AXI_ID_WIDTH-1:0]     i_axi_rid,     // Response ID
        input   [1:0]                    i_axi_rresp,   // Read response
        input                           i_axi_rvalid,  // Read reponse valid
        input   [C_AXI_DATA_WIDTH-1:0]   i_axi_rdata,    // Read data
        input                           i_axi_rlast,    // Read last
        output  wire                    o_axi_rready,  // Read Response ready
 
        // We'll share the clock and the reset
        input                           i_wb_cyc,
        input                           i_wb_stb,
        input                           i_wb_we,
        input           [AW-1:0] i_wb_addr,
        input           [DW-1:0] i_wb_data,
        input           [(DW/8-1):0]     i_wb_sel,
        output  reg                     o_wb_ack,
        output  wire                    o_wb_stall,
        output  reg     [DW-1:0] o_wb_data,
        output  reg                     o_wb_err
);
 
//*****************************************************************************
// Parameter declarations
//*****************************************************************************
 
        localparam      CTL_SIG_WIDTH   = 3;    // Control signal width
        localparam      RD_STS_WIDTH    = 16;   // Read status signal width
        localparam      WR_STS_WIDTH    = 16;   // Write status signal width
 
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
 
        wire                                    cmd_en;
        wire    [2:0]                            cmd;
        wire    [7:0]                            blen;
        wire    [31:0]                           addr;
        wire    [CTL_SIG_WIDTH-1:0]              ctl;
        wire                                    cmd_ack;
 
// User interface write ports
        wire                                    wrdata_vld;
        wire    [C_AXI_DATA_WIDTH-1:0]           wrdata;
        wire    [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld;
        wire                                    wrdata_cmptd;
        wire                                    wrdata_rdy;
        wire                                    wrdata_sts_vld;
        wire    [WR_STS_WIDTH-1:0]              wrdata_sts;
 
// User interface read ports
        wire                                    rddata_rdy;
        wire                                    rddata_vld;
        wire    [C_AXI_DATA_WIDTH-1:0]           rddata;
        wire    [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld;
        wire                                    rddata_cmptd;
        wire    [RD_STS_WIDTH-1:0]               rddata_sts;
        reg                                     cmptd_one_wr;
        reg                                     cmptd_one_rd;
 
 
// Things we're not changing ...
        assign o_axi_awlen = 8'h0;      // Burst length is one
        assign o_axi_awsize = 3'b101;   // maximum bytes per burst is 32
        assign o_axi_awburst = 2'b01;   // Incrementing address (ignored)
        assign o_axi_arburst = 2'b01;   // Incrementing address (ignored)
        assign o_axi_awlock  = 2'b00;   // Normal signaling
        assign o_axi_arlock  = 2'b00;   // Normal signaling
        assign o_axi_awcache = 4'h2;    // Normal: no cache, no buffer
        assign o_axi_arcache = 4'h2;    // Normal: no cache, no buffer
        assign o_axi_awprot  = 3'h010;  // Unpriviledged, unsecure, data access
        assign o_axi_arprot  = 3'h010;  // Unpriviledged, unsecure, data access
        assign o_axi_awqos  = 4'h0;     // Lowest quality of service (unused)
        assign o_axi_arqos  = 4'h0;     // Lowest quality of service (unused)
 
// Command logic
// Write address logic
 
        always @(posedge i_clk)
                o_axi_awvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)
                        ||(o_wb_stall)&&(o_axi_awvalid)&&(!i_axi_awready);
        always @(posedge i_clk)
                if (!o_wb_stall)
                        o_axi_awaddr <= { i_wb_addr[AW-1:2], 2'b00 }; // 28 bits
 
        reg     [5:0]    transaction_id;
        always @(posedge i_clk)
                if (!i_wb_cyc)
                        transaction_id <= 6'h00;
                else if ((i_wb_stb)&&(~o_wb_stall))
                        transaction_id <= transaction_id + 6'h01;
        assign  o_axi_awid = transaction_id;
 
// Read address logic
        assign  o_axi_arid = transaction_id;
        assign  o_axi_araddr = o_axi_awaddr;
        assign  o_axi_arlen  = o_axi_awlen;
        assign  o_axi_arsize = 3'b101;  // maximum bytes per burst is 32
        always @(posedge i_clk)
                o_axi_arvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)
                        ||(o_wb_stall)&&(o_axi_arvalid)&&(!i_axi_arready);
 
 
// Write data logic
        generate
        if (DW == 32)
        begin
                always @(posedge i_clk)
                        if (!o_wb_stall)
                                o_axi_wdata <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
                always @(posedge i_clk)
                        if (!o_wb_stall)
                        case(i_wb_addr[1:0])
                        2'b00:o_axi_wstrb<={     4'h0,     4'h0,     4'h0, i_wb_sel };
                        2'b01:o_axi_wstrb<={     4'h0,     4'h0, i_wb_sel,     4'h0 };
                        2'b10:o_axi_wstrb<={     4'h0, i_wb_sel,     4'h0,     4'h0 };
                        2'b11:o_axi_wstrb<={ i_wb_sel,     4'h0,     4'h0,     4'h0 };
                        endcase
        end else if (DW == 128)
        begin
                always @(posedge i_clk)
                        if (!o_wb_stall)
                                o_axi_wdata <= i_wb_data;
                always @(posedge i_clk)
                        if (!o_wb_stall)
                                o_axi_wstrb <= i_wb_sel;
        end endgenerate
 
        assign  o_axi_wlast = 1'b1;
        always @(posedge i_clk)
                o_axi_wvalid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))
                        ||(o_wb_stall)&&(o_axi_wvalid)&&(!i_axi_wready);
 
// Read data channel / response logic
        assign  o_axi_rready = 1'b1;
        assign  o_axi_bready = 1'b1;
 
        wire    w_fifo_full;
        generate
        if (STRICT_ORDER == 0)
        begin
                // Reorder FIFO
                //
                localparam      LGFIFOLN = C_AXI_ID_WIDTH;
                localparam      FIFOLN = (1<<LGFIFOLN);
                // FIFO reorder buffer
                reg     [(LGFIFOLN-1):0] fifo_tail;
                reg     [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
                reg     [(FIFOLN-1):0]   reorder_fifo_valid;
                reg     [(FIFOLN-1):0]   reorder_fifo_err;
 
                if (DW == 32)
                begin
                        reg     [1:0]    reorder_fifo_addr [0:(FIFOLN-1)];
 
 
                        reg     [1:0]    low_addr;
                        always @(posedge i_clk)
                                if ((i_wb_stb)&&(!o_wb_stall))
                                        low_addr <= i_wb_addr[1:0];
                        always @(posedge i_clk)
                                if ((o_axi_arvalid)&&(i_axi_arready))
                                        reorder_fifo_addr[o_axi_arid] <= low_addr;
 
                        always @(posedge i_clk)
                        case(reorder_fifo_addr[1:0])
                        2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
                        2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
                        2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
                        2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];
                        endcase
 
                end else if (DW == 128)
                begin
                        always @(posedge i_clk)
                                o_wb_data <= reorder_fifo_data[fifo_tail];
                end
 
 
                wire    [(LGFIFOLN-1):0] fifo_head;
                assign  fifo_head = transaction_id;
 
                // Let's do some math to figure out where the FIFO head will
                // point to next, but let's also insist that it be LGFIFOLN
                // bits in size as well.  This'll be part of the fifo_full
                // calculation below.
                wire    [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;
                assign  n_fifo_head = fifo_head+1'b1;
 
                always @(posedge i_clk)
                begin
                        if ((i_axi_rvalid)&&(o_axi_rready))
                                reorder_fifo_data[i_axi_rid]<= i_axi_rdata;
                        if ((i_axi_rvalid)&&(o_axi_rready))
                        begin
                                reorder_fifo_valid[i_axi_rid] <= 1'b1;
                                reorder_fifo_err[i_axi_rid] <= i_axi_rresp[1];
                        end
                        if ((i_axi_bvalid)&&(o_axi_bready))
                        begin
                                reorder_fifo_valid[i_axi_bid] <= 1'b1;
                                reorder_fifo_err[i_axi_bid] <= i_axi_bresp[1];
                        end
 
                        if (reorder_fifo_valid[fifo_tail])
                        begin
                                o_wb_ack <= 1'b1;
                                o_wb_err <= reorder_fifo_err[fifo_tail];
                                fifo_tail <= fifo_tail + 6'h1;
                                reorder_fifo_valid[fifo_tail] <= 1'b0;
                                reorder_fifo_err[fifo_tail]   <= 1'b0;
                        end else begin
                                o_wb_ack <= 1'b0;
                                o_wb_err <= 1'b0;
                        end
 
                        if (!i_wb_cyc)
                        begin
                                reorder_fifo_valid <= {(FIFOLN){1'b0}};
                                reorder_fifo_err   <= {(FIFOLN){1'b0}};
                                fifo_tail <= 6'h0;
                                o_wb_err <= 1'b0;
                                o_wb_ack <= 1'b0;
                        end
                end
 
                reg     r_fifo_full;
                always @(posedge i_clk)
                begin
                        if (!i_wb_cyc)
                                r_fifo_full <= 1'b0;
                        else if ((i_wb_stb)&&(~o_wb_stall)
                                        &&(reorder_fifo_valid[fifo_tail]))
                                r_fifo_full <= (fifo_tail==n_fifo_head);
                        else if ((i_wb_stb)&&(~o_wb_stall))
                                r_fifo_full <= (fifo_tail==nn_fifo_head);
                        else if (reorder_fifo_valid[fifo_tail])
                                r_fifo_full <= 1'b0;
                        else
                                r_fifo_full <= (fifo_tail==n_fifo_head);
                end
                assign w_fifo_full = r_fifo_full;
        end else begin
                assign w_fifo_full = 1'b0;
                always @(posedge i_clk)
                        o_wb_data <= i_axi_rdata;
                always @(posedge i_clk)
                        o_wb_ack <= ((i_axi_rvalid)&&(o_axi_rready))
                                  ||((i_axi_bvalid)&&(o_axi_bready));
                always @(posedge i_clk)
                        o_wb_err <= (!i_wb_cyc)&&((o_wb_err)
                                ||((i_axi_rvalid)&&(i_axi_rresp[1]))
                                ||((i_axi_bvalid)&&(i_axi_bresp[1])));
        end endgenerate
 
 
        // Now, the difficult signal ... the stall signal
        // Let's build for a single cycle input ... and only stall if something
        // outgoing is valid and nothing is ready.
        assign  o_wb_stall = (i_wb_cyc)&&(
                                (w_fifo_full)
                                ||((o_axi_awvalid)&&(!i_axi_awready))
                                ||((o_axi_wvalid )&&(!i_axi_wready ))
                                ||((o_axi_arvalid)&&(!i_axi_arready)));
endmodule
 

Line No.	Rev	Author	Line
1	2	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: wbm2axisp.v`
4			`//`
5			`// Project: Pipelined Wishbone to AXI converter`
6			`//`
7			`// Purpose: The B4 Wishbone SPEC allows transactions at a speed as fast as`
8			`// one per clock. The AXI bus allows transactions at a speed of`
9			`// one read and one write transaction per clock. These capabilities work`
10			`// by allowing requests to take place prior to responses, such that the`
11			`// requests might go out at once per clock and take several clocks, and`
12			`// the responses may start coming back several clocks later. In other`
13			`// words, both protocols allow multiple transactions to be "in flight" at`
14			`// the same time. Current wishbone to AXI converters, however, handle only`
15			`// one transaction at a time: initiating the transaction, and then waiting`
16			`// for the transaction to complete before initiating the next.`
17			`//`
18			`// The purpose of this core is to maintain the speed of both busses, while`
19			`// transiting from the Wishbone (as master) to the AXI bus (as slave) and`
20			`// back again.`
21			`//`
22			`// Since the AXI bus allows transactions to be reordered, whereas the`
23			`// wishbone does not, this core can be configured to reorder return`
24			`// transactions as well.`
25			`//`
26			`// Creator: Dan Gisselquist, Ph.D.`
27			`// Gisselquist Technology, LLC`
28			`//`
29			`////////////////////////////////////////////////////////////////////////////////`
30			`//`
31	3	dgisselq	`// Copyright (C) 2016, Gisselquist Technology, LLC`
32	2	dgisselq	`//`
33			`// This program is free software (firmware): you can redistribute it and/or`
34			`// modify it under the terms of the GNU General Public License as published`
35			`// by the Free Software Foundation, either version 3 of the License, or (at`
36			`// your option) any later version.`
37			`//`
38			`// This program is distributed in the hope that it will be useful, but WITHOUT`
39			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
40			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
41			`// for more details.`
42			`//`
43			`// You should have received a copy of the GNU General Public License along`
44			`// with this program. (It's in the $(ROOT)/doc directory, run make with no`
45			`// target there if the PDF file isn't present.) If not, see`
46			`// <http://www.gnu.org/licenses/> for a copy.`
47			`//`
48			`// License: GPL, v3, as defined and found on www.gnu.org,`
49			`// http://www.gnu.org/licenses/gpl.html`
50			`//`
51			`//`
52			`////////////////////////////////////////////////////////////////////////////////`
53			`//`
54			`//`
55			`module wbm2axisp #(`
56			`parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W`
57			`// This is an int between 1-16`
58			`parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data`
59			`parameter AW = 28, // Wishbone address width`
60	4	dgisselq	`parameter DW = 128, // Wishbone data width`
61	3	dgisselq	`parameter STRICT_ORDER = 0 // Reorder, or not? 0 -> Reorder`
62	2	dgisselq	`) (`
63			`input i_clk, // System clock`
64			`input i_reset,// Wishbone reset signal`
65
66			`// AXI write address channel signals`
67	5	dgisselq	`input i_axi_awready, // Slave is ready to accept`
68			`output wire [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID`
69			`output reg [AW-1:0] o_axi_awaddr, // Write address`
70			`output wire [7:0] o_axi_awlen, // Write Burst Length`
71			`output wire [2:0] o_axi_awsize, // Write Burst size`
72			`output wire [1:0] o_axi_awburst, // Write Burst type`
73			`output wire [1:0] o_axi_awlock, // Write lock type`
74			`output wire [3:0] o_axi_awcache, // Write Cache type`
75			`output wire [2:0] o_axi_awprot, // Write Protection type`
76			`output wire [3:0] o_axi_awqos, // Write Quality of Svc`
77			`output reg o_axi_awvalid, // Write address valid`
78	2	dgisselq
79			`// AXI write data channel signals`
80	5	dgisselq	`input i_axi_wready, // Write data ready`
81			`output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata, // Write data`
82			`output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb, // Write strobes`
83			`output wire o_axi_wlast, // Last write transaction`
84			`output reg o_axi_wvalid, // Write valid`
85	2	dgisselq
86			`// AXI write response channel signals`
87	5	dgisselq	`input [C_AXI_ID_WIDTH-1:0] i_axi_bid, // Response ID`
88			`input [1:0] i_axi_bresp, // Write response`
89			`input i_axi_bvalid, // Write reponse valid`
90			`output wire o_axi_bready, // Response ready`
91	2	dgisselq
92			`// AXI read address channel signals`
93	5	dgisselq	`input i_axi_arready, // Read address ready`
94			`output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID`
95			`output wire [AW-1:0] o_axi_araddr, // Read address`
96			`output wire [7:0] o_axi_arlen, // Read Burst Length`
97			`output wire [2:0] o_axi_arsize, // Read Burst size`
98			`output wire [1:0] o_axi_arburst, // Read Burst type`
99			`output wire [1:0] o_axi_arlock, // Read lock type`
100			`output wire [3:0] o_axi_arcache, // Read Cache type`
101			`output wire [2:0] o_axi_arprot, // Read Protection type`
102			`output wire [3:0] o_axi_arqos, // Read Protection type`
103			`output reg o_axi_arvalid, // Read address valid`
104	2	dgisselq
105			`// AXI read data channel signals`
106	5	dgisselq	`input [C_AXI_ID_WIDTH-1:0] i_axi_rid, // Response ID`
107			`input [1:0] i_axi_rresp, // Read response`
108			`input i_axi_rvalid, // Read reponse valid`
109			`input [C_AXI_DATA_WIDTH-1:0] i_axi_rdata, // Read data`
110			`input i_axi_rlast, // Read last`
111			`output wire o_axi_rready, // Read Response ready`
112	2	dgisselq
113			`// We'll share the clock and the reset`
114	3	dgisselq	`input i_wb_cyc,`
115			`input i_wb_stb,`
116			`input i_wb_we,`
117			`input [AW-1:0] i_wb_addr,`
118			`input [DW-1:0] i_wb_data,`
119	4	dgisselq	`input [(DW/8-1):0] i_wb_sel,`
120	3	dgisselq	`output reg o_wb_ack,`
121			`output wire o_wb_stall,`
122			`output reg [DW-1:0] o_wb_data,`
123			`output reg o_wb_err`
124	2	dgisselq	`);`
125
126			`//*****************************************************************************`
127			`// Parameter declarations`
128			`//*****************************************************************************`
129
130			`localparam CTL_SIG_WIDTH = 3; // Control signal width`
131			`localparam RD_STS_WIDTH = 16; // Read status signal width`
132			`localparam WR_STS_WIDTH = 16; // Write status signal width`
133
134			`//*****************************************************************************`
135			`// Internal register and wire declarations`
136			`//*****************************************************************************`
137
138			`wire cmd_en;`
139			`wire [2:0] cmd;`
140			`wire [7:0] blen;`
141			`wire [31:0] addr;`
142			`wire [CTL_SIG_WIDTH-1:0] ctl;`
143			`wire cmd_ack;`
144
145			`// User interface write ports`
146			`wire wrdata_vld;`
147			`wire [C_AXI_DATA_WIDTH-1:0] wrdata;`
148			`wire [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld;`
149			`wire wrdata_cmptd;`
150			`wire wrdata_rdy;`
151			`wire wrdata_sts_vld;`
152			`wire [WR_STS_WIDTH-1:0] wrdata_sts;`
153
154			`// User interface read ports`
155			`wire rddata_rdy;`
156			`wire rddata_vld;`
157			`wire [C_AXI_DATA_WIDTH-1:0] rddata;`
158			`wire [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld;`
159			`wire rddata_cmptd;`
160			`wire [RD_STS_WIDTH-1:0] rddata_sts;`
161			`reg cmptd_one_wr;`
162			`reg cmptd_one_rd;`
163
164
165			`// Things we're not changing ...`
166	5	dgisselq	`assign o_axi_awlen = 8'h0; // Burst length is one`
167			`assign o_axi_awsize = 3'b101; // maximum bytes per burst is 32`
168			`assign o_axi_awburst = 2'b01; // Incrementing address (ignored)`
169			`assign o_axi_arburst = 2'b01; // Incrementing address (ignored)`
170			`assign o_axi_awlock = 2'b00; // Normal signaling`
171			`assign o_axi_arlock = 2'b00; // Normal signaling`
172			`assign o_axi_awcache = 4'h2; // Normal: no cache, no buffer`
173			`assign o_axi_arcache = 4'h2; // Normal: no cache, no buffer`
174			`assign o_axi_awprot = 3'h010; // Unpriviledged, unsecure, data access`
175			`assign o_axi_arprot = 3'h010; // Unpriviledged, unsecure, data access`
176			`assign o_axi_awqos = 4'h0; // Lowest quality of service (unused)`
177			`assign o_axi_arqos = 4'h0; // Lowest quality of service (unused)`
178	2	dgisselq
179			`// Command logic`
180			`// Write address logic`
181
182			`always @(posedge i_clk)`
183	5	dgisselq	`o_axi_awvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)`
184			`\|\|(o_wb_stall)&&(o_axi_awvalid)&&(!i_axi_awready);`
185	2	dgisselq	`always @(posedge i_clk)`
186			`if (!o_wb_stall)`
187	5	dgisselq	`o_axi_awaddr <= { i_wb_addr[AW-1:2], 2'b00 }; // 28 bits`
188	2	dgisselq
189			`reg [5:0] transaction_id;`
190			`always @(posedge i_clk)`
191			`if (!i_wb_cyc)`
192			`transaction_id <= 6'h00;`
193			`else if ((i_wb_stb)&&(~o_wb_stall))`
194			`transaction_id <= transaction_id + 6'h01;`
195	5	dgisselq	`assign o_axi_awid = transaction_id;`
196	2	dgisselq
197			`// Read address logic`
198	5	dgisselq	`assign o_axi_arid = transaction_id;`
199			`assign o_axi_araddr = o_axi_awaddr;`
200			`assign o_axi_arlen = o_axi_awlen;`
201			`assign o_axi_arsize = 3'b101; // maximum bytes per burst is 32`
202	2	dgisselq	`always @(posedge i_clk)`
203	5	dgisselq	`o_axi_arvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)`
204			`\|\|(o_wb_stall)&&(o_axi_arvalid)&&(!i_axi_arready);`
205	2	dgisselq
206
207			`// Write data logic`
208	4	dgisselq	`generate`
209			`if (DW == 32)`
210			`begin`
211			`always @(posedge i_clk)`
212			`if (!o_wb_stall)`
213	5	dgisselq	`o_axi_wdata <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };`
214	4	dgisselq	`always @(posedge i_clk)`
215			`if (!o_wb_stall)`
216			`case(i_wb_addr[1:0])`
217	5	dgisselq	`2'b00:o_axi_wstrb<={ 4'h0, 4'h0, 4'h0, i_wb_sel };`
218			`2'b01:o_axi_wstrb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 };`
219			`2'b10:o_axi_wstrb<={ 4'h0, i_wb_sel, 4'h0, 4'h0 };`
220			`2'b11:o_axi_wstrb<={ i_wb_sel, 4'h0, 4'h0, 4'h0 };`
221	4	dgisselq	`endcase`
222			`end else if (DW == 128)`
223			`begin`
224			`always @(posedge i_clk)`
225			`if (!o_wb_stall)`
226	5	dgisselq	`o_axi_wdata <= i_wb_data;`
227	4	dgisselq	`always @(posedge i_clk)`
228			`if (!o_wb_stall)`
229	5	dgisselq	`o_axi_wstrb <= i_wb_sel;`
230	4	dgisselq	`end endgenerate`
231
232	5	dgisselq	`assign o_axi_wlast = 1'b1;`
233	2	dgisselq	`always @(posedge i_clk)`
234	5	dgisselq	`o_axi_wvalid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))`
235			`\|\|(o_wb_stall)&&(o_axi_wvalid)&&(!i_axi_wready);`
236	2	dgisselq
237			`// Read data channel / response logic`
238	5	dgisselq	`assign o_axi_rready = 1'b1;`
239			`assign o_axi_bready = 1'b1;`
240	2	dgisselq
241			`wire w_fifo_full;`
242			`generate`
243			`if (STRICT_ORDER == 0)`
244			`begin`
245			`// Reorder FIFO`
246			`//`
247			`localparam LGFIFOLN = C_AXI_ID_WIDTH;`
248			`localparam FIFOLN = (1<<LGFIFOLN);`
249			`// FIFO reorder buffer`
250	3	dgisselq	`reg [(LGFIFOLN-1):0] fifo_tail;`
251			`reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];`
252			`reg [(FIFOLN-1):0] reorder_fifo_valid;`
253			`reg [(FIFOLN-1):0] reorder_fifo_err;`
254
255	4	dgisselq	`if (DW == 32)`
256			`begin`
257			`reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];`
258	3	dgisselq
259
260	4	dgisselq	`reg [1:0] low_addr;`
261			`always @(posedge i_clk)`
262			`if ((i_wb_stb)&&(!o_wb_stall))`
263			`low_addr <= i_wb_addr[1:0];`
264			`always @(posedge i_clk)`
265	5	dgisselq	`if ((o_axi_arvalid)&&(i_axi_arready))`
266			`reorder_fifo_addr[o_axi_arid] <= low_addr;`
267	3	dgisselq
268	4	dgisselq	`always @(posedge i_clk)`
269			`case(reorder_fifo_addr[1:0])`
270			`2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];`
271			`2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];`
272			`2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];`
273			`2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];`
274			`endcase`
275
276			`end else if (DW == 128)`
277			`begin`
278			`always @(posedge i_clk)`
279			`o_wb_data <= reorder_fifo_data[fifo_tail];`
280			`end`
281
282
283	3	dgisselq	`wire [(LGFIFOLN-1):0] fifo_head;`
284	2	dgisselq	`assign fifo_head = transaction_id;`
285
286			`// Let's do some math to figure out where the FIFO head will`
287			`// point to next, but let's also insist that it be LGFIFOLN`
288			`// bits in size as well. This'll be part of the fifo_full`
289			`// calculation below.`
290			`wire [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;`
291			`assign n_fifo_head = fifo_head+1'b1;`
292
293			`always @(posedge i_clk)`
294			`begin`
295	5	dgisselq	`if ((i_axi_rvalid)&&(o_axi_rready))`
296			`reorder_fifo_data[i_axi_rid]<= i_axi_rdata;`
297			`if ((i_axi_rvalid)&&(o_axi_rready))`
298	2	dgisselq	`begin`
299	5	dgisselq	`reorder_fifo_valid[i_axi_rid] <= 1'b1;`
300			`reorder_fifo_err[i_axi_rid] <= i_axi_rresp[1];`
301	2	dgisselq	`end`
302	5	dgisselq	`if ((i_axi_bvalid)&&(o_axi_bready))`
303	2	dgisselq	`begin`
304	5	dgisselq	`reorder_fifo_valid[i_axi_bid] <= 1'b1;`
305			`reorder_fifo_err[i_axi_bid] <= i_axi_bresp[1];`
306	2	dgisselq	`end`
307
308			`if (reorder_fifo_valid[fifo_tail])`
309			`begin`
310			`o_wb_ack <= 1'b1;`
311			`o_wb_err <= reorder_fifo_err[fifo_tail];`
312			`fifo_tail <= fifo_tail + 6'h1;`
313			`reorder_fifo_valid[fifo_tail] <= 1'b0;`
314			`reorder_fifo_err[fifo_tail] <= 1'b0;`
315			`end else begin`
316			`o_wb_ack <= 1'b0;`
317			`o_wb_err <= 1'b0;`
318			`end`
319
320			`if (!i_wb_cyc)`
321			`begin`
322			`reorder_fifo_valid <= {(FIFOLN){1'b0}};`
323			`reorder_fifo_err <= {(FIFOLN){1'b0}};`
324			`fifo_tail <= 6'h0;`
325			`o_wb_err <= 1'b0;`
326			`o_wb_ack <= 1'b0;`
327			`end`
328			`end`
329
330	3	dgisselq	`reg r_fifo_full;`
331	2	dgisselq	`always @(posedge i_clk)`
332			`begin`
333			`if (!i_wb_cyc)`
334			`r_fifo_full <= 1'b0;`
335			`else if ((i_wb_stb)&&(~o_wb_stall)`
336			`&&(reorder_fifo_valid[fifo_tail]))`
337			`r_fifo_full <= (fifo_tail==n_fifo_head);`
338			`else if ((i_wb_stb)&&(~o_wb_stall))`
339			`r_fifo_full <= (fifo_tail==nn_fifo_head);`
340			`else if (reorder_fifo_valid[fifo_tail])`
341			`r_fifo_full <= 1'b0;`
342			`else`
343			`r_fifo_full <= (fifo_tail==n_fifo_head);`
344			`end`
345			`assign w_fifo_full = r_fifo_full;`
346			`end else begin`
347	3	dgisselq	`assign w_fifo_full = 1'b0;`
348	2	dgisselq	`always @(posedge i_clk)`
349	5	dgisselq	`o_wb_data <= i_axi_rdata;`
350	2	dgisselq	`always @(posedge i_clk)`
351	5	dgisselq	`o_wb_ack <= ((i_axi_rvalid)&&(o_axi_rready))`
352			`\|\|((i_axi_bvalid)&&(o_axi_bready));`
353	2	dgisselq	`always @(posedge i_clk)`
354			`o_wb_err <= (!i_wb_cyc)&&((o_wb_err)`
355	5	dgisselq	`\|\|((i_axi_rvalid)&&(i_axi_rresp[1]))`
356			`\|\|((i_axi_bvalid)&&(i_axi_bresp[1])));`
357	3	dgisselq	`end endgenerate`
358	2	dgisselq
359
360			`// Now, the difficult signal ... the stall signal`
361			`// Let's build for a single cycle input ... and only stall if something`
362			`// outgoing is valid and nothing is ready.`
363			`assign o_wb_stall = (i_wb_cyc)&&(`
364			`(w_fifo_full)`
365	5	dgisselq	`\|\|((o_axi_awvalid)&&(!i_axi_awready))`
366			`\|\|((o_axi_wvalid )&&(!i_axi_wready ))`
367			`\|\|((o_axi_arvalid)&&(!i_axi_arready)));`
368	2	dgisselq	`endmodule`
369	5	dgisselq

Browse

Tools

Subversion Repositories wb2axip

[/] [wb2axip/] [trunk/] [rtl/] [wbm2axisp.v] - Blame information for rev 5