Subversion Repositories wb4pb

INST DCM_SP_INST CLK_FEEDBACK = NONE;

INST DCM_SP_INST CLKDV_DIVIDE = 2.0;

INST DCM_SP_INST CLKFX_DIVIDE = 8;

INST DCM_SP_INST CLKFX_MULTIPLY = 25;

INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE;

INST DCM_SP_INST CLKIN_PERIOD = 62.500;

INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;

INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;

INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;

INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;

INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;

INST DCM_SP_INST FACTORY_JF = C080;

INST DCM_SP_INST PHASE_SHIFT = 0;

INST DCM_SP_INST STARTUP_WAIT = FALSE;

NET CLK_16MHZ TNM_NET = CLK_16MHZ;

TIMESPEC TS_CLK_16MHZ = PERIOD CLK_16MHZ 62.50 ns;

NET CLK_16MHZ           LOC = C10   | IOSTANDARD = LVCMOS33               ;

NET FPGA_RESET          LOC = H4    | IOSTANDARD = LVCMOS33               ;

NET LED1                LOC = D14   | IOSTANDARD = LVCMOS33               ;

NET UART_RXD            LOC = B3    | IOSTANDARD = LVCMOS33               ;

NET UART_TXD            LOC = A3    | IOSTANDARD = LVCMOS33               ;