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-- This sourcecode is released under BSD license.

-- Please see http://www.opensource.org/licenses/bsd-license.php for details!

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--

-- Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>

-- All rights reserved.

--

-- Redistribution and use in source and binary forms, with or without 

-- modification, are permitted provided that the following conditions are met:

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--  * Redistributions of source code must retain the above copyright notice, 

--    this list of conditions and the following disclaimer.

--  * Redistributions in binary form must reproduce the above copyright notice,

--    this list of conditions and the following disclaimer in the documentation

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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 

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-- filename: picoblaze_wb_uart_tb.vhd

-- description: testbench for picoblaze_wb_uart example

-- todo4user: modify stimulus as needed

-- version: 0.0.0

-- changelog: - 0.0.0, initial release

--            - ...

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library ieee;

use ieee.std_logic_1164.all;

entity picoblaze_wb_uart_tb is

end picoblaze_wb_uart_tb;

architecture behavioral of picoblaze_wb_uart_tb is

  component picoblaze_wb_uart is

    port

    (

      p_rst_n_i : in std_logic;

      p_clk_i : in std_logic;

      p_uart_rx_si_i : in std_logic;

      p_uart_tx_so_o : out std_logic

    );

  end component;

  signal rst_n : std_logic := '0';

  signal clk : std_logic := '1';

  signal uart_rx_si : std_logic := '0';

  signal uart_tx_so : std_logic := '0';

  constant PERIOD : time := 20 ns;

begin

  -- system signal generation

  rst_n <= '1' after PERIOD*2;

  clk <= not clk after PERIOD/2;

  -- simple serial loopback

  uart_rx_si <= uart_tx_so;

  -- design under test instance

  dut : picoblaze_wb_uart

    port map

    (

      p_rst_n_i => rst_n,

      p_clk_i => clk,

      p_uart_rx_si_i => uart_rx_si,

      p_uart_tx_so_o => uart_tx_so

    );

end behavioral;