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Subversion Repositories wb_async_mem_bridge

[/] [wb_async_mem_bridge/] [trunk/] [src/] [wb_async_mem_sm.v] - Blame information for rev 6

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// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module
  wb_async_mem_sm
  #(
    parameter DW = 32,
    parameter AW = 32
  )
  (
    input   [(DW-1):0]  wb_data_i,
    input   [(AW-1):0]  wb_addr_i,
    output              wb_we_o,
    output              wb_cyc_o,
    output              wb_stb_o,
    input               wb_ack_i,
    input               wb_err_i,
    input               wb_rty_i,
 
    input   [(DW-1):0]  mem_d,
    input   [(AW-1):0]  mem_a,
    input               mem_oe_n,
    input   [3:0]       mem_bls_n,
    input               mem_we_n,
    input               mem_cs_n,
 
    input               mem_we_n_fall,
    input               mem_oe_n_fall,
 
    output  [5:0]       dbg_state,
 
    input               wb_clk_i,
    input               wb_rst_i
  );
 
 
  // --------------------------------------------------------------------
  //  wires
  wire address_change;
 
 
  // --------------------------------------------------------------------
  //  state machine
 
  localparam   STATE_IDLE     = 6'b000001;
  localparam   STATE_WE       = 6'b000010;
  localparam   STATE_OE       = 6'b000100;
  localparam   STATE_DONE     = 6'b001000;
  localparam   STATE_ERROR    = 6'b010000;
  localparam   STATE_GLITCH   = 6'b100000;
 
  reg [5:0] state;
  reg [5:0] next_state;
 
  always @(posedge wb_clk_i or posedge wb_rst_i)
    if(wb_rst_i)
      state <= STATE_IDLE;
    else
      state <= next_state;
 
  always @(*)
    case( state )
      STATE_IDLE:       if( (mem_oe_n & mem_we_n) | mem_cs_n )
                          next_state = STATE_IDLE;
                        else
                          if( ~mem_oe_n & ~mem_we_n )
                            next_state = STATE_ERROR;
                          else
                            if( ~mem_we_n )
                              next_state = STATE_WE;
                            else
                              next_state = STATE_OE;
 
      STATE_WE:         if( mem_we_n | mem_cs_n )
                          next_state = STATE_ERROR;
                        else
                          if( wb_ack_i )
                            next_state = STATE_DONE;
                          else
                            next_state = STATE_WE;
 
      STATE_OE:         if( mem_oe_n | mem_cs_n | address_change )
                          next_state = STATE_ERROR;
                        else
                          if( wb_ack_i )
                            next_state = STATE_DONE;
                          else
                            next_state = STATE_OE;
 
      STATE_DONE:       if( mem_cs_n )
                          next_state = STATE_IDLE;
                        else
                          if( mem_we_n_fall )
                            next_state = STATE_WE;
                          else if( mem_oe_n_fall )
                            next_state = STATE_OE;
                          else
                            next_state = STATE_DONE;
 
      STATE_ERROR:      next_state = STATE_IDLE;
 
      STATE_GLITCH:     next_state = STATE_IDLE;
 
      default:          next_state = STATE_GLITCH;
    endcase
 
 
// --------------------------------------------------------------------
//  wb_addr_i flop
  reg [(AW-1):0] wb_addr_i_r;
  assign address_change = (wb_addr_i != wb_addr_i_r);
 
  always @(posedge wb_clk_i)
    if( (state != STATE_DONE) | (state != STATE_OE) )
      wb_addr_i_r <= wb_addr_i;
 
 
// --------------------------------------------------------------------
//  outputs
  assign wb_cyc_o = (state == STATE_WE) | (state == STATE_OE);
  assign wb_stb_o = (state == STATE_WE) | (state == STATE_OE);
  assign wb_we_o  = (state == STATE_WE);
 
  assign dbg_state = state;
 
endmodule
 

Line No.	Rev	Author	Line
1	6	qaztronic	`// --------------------------------------------------------------------`
2			`//`
3			`// --------------------------------------------------------------------`
4
5			`include "timescale.v"
6
7
8			`module`
9			`wb_async_mem_sm`
10			`#(`
11			`parameter DW = 32,`
12			`parameter AW = 32`
13			`)`
14			`(`
15			`input [(DW-1):0] wb_data_i,`
16			`input [(AW-1):0] wb_addr_i,`
17			`output wb_we_o,`
18			`output wb_cyc_o,`
19			`output wb_stb_o,`
20			`input wb_ack_i,`
21			`input wb_err_i,`
22			`input wb_rty_i,`
23
24			`input [(DW-1):0] mem_d,`
25			`input [(AW-1):0] mem_a,`
26			`input mem_oe_n,`
27			`input [3:0] mem_bls_n,`
28			`input mem_we_n,`
29			`input mem_cs_n,`
30
31			`input mem_we_n_fall,`
32			`input mem_oe_n_fall,`
33
34			`output [5:0] dbg_state,`
35
36			`input wb_clk_i,`
37			`input wb_rst_i`
38			`);`
39
40
41			`// --------------------------------------------------------------------`
42			`// wires`
43			`wire address_change;`
44
45
46			`// --------------------------------------------------------------------`
47			`// state machine`
48
49			`localparam STATE_IDLE = 6'b000001;`
50			`localparam STATE_WE = 6'b000010;`
51			`localparam STATE_OE = 6'b000100;`
52			`localparam STATE_DONE = 6'b001000;`
53			`localparam STATE_ERROR = 6'b010000;`
54			`localparam STATE_GLITCH = 6'b100000;`
55
56			`reg [5:0] state;`
57			`reg [5:0] next_state;`
58
59			`always @(posedge wb_clk_i or posedge wb_rst_i)`
60			`if(wb_rst_i)`
61			`state <= STATE_IDLE;`
62			`else`
63			`state <= next_state;`
64
65			`always @(*)`
66			`case( state )`
67			`STATE_IDLE: if( (mem_oe_n & mem_we_n) \| mem_cs_n )`
68			`next_state = STATE_IDLE;`
69			`else`
70			`if( ~mem_oe_n & ~mem_we_n )`
71			`next_state = STATE_ERROR;`
72			`else`
73			`if( ~mem_we_n )`
74			`next_state = STATE_WE;`
75			`else`
76			`next_state = STATE_OE;`
77
78			`STATE_WE: if( mem_we_n \| mem_cs_n )`
79			`next_state = STATE_ERROR;`
80			`else`
81			`if( wb_ack_i )`
82			`next_state = STATE_DONE;`
83			`else`
84			`next_state = STATE_WE;`
85
86			`STATE_OE: if( mem_oe_n \| mem_cs_n \| address_change )`
87			`next_state = STATE_ERROR;`
88			`else`
89			`if( wb_ack_i )`
90			`next_state = STATE_DONE;`
91			`else`
92			`next_state = STATE_OE;`
93
94			`STATE_DONE: if( mem_cs_n )`
95			`next_state = STATE_IDLE;`
96			`else`
97			`if( mem_we_n_fall )`
98			`next_state = STATE_WE;`
99			`else if( mem_oe_n_fall )`
100			`next_state = STATE_OE;`
101			`else`
102			`next_state = STATE_DONE;`
103
104			`STATE_ERROR: next_state = STATE_IDLE;`
105
106			`STATE_GLITCH: next_state = STATE_IDLE;`
107
108			`default: next_state = STATE_GLITCH;`
109			`endcase`
110
111
112			`// --------------------------------------------------------------------`
113			`// wb_addr_i flop`
114			`reg [(AW-1):0] wb_addr_i_r;`
115			`assign address_change = (wb_addr_i != wb_addr_i_r);`
116
117			`always @(posedge wb_clk_i)`
118			`if( (state != STATE_DONE) \| (state != STATE_OE) )`
119			`wb_addr_i_r <= wb_addr_i;`
120
121
122			`// --------------------------------------------------------------------`
123			`// outputs`
124			`assign wb_cyc_o = (state == STATE_WE) \| (state == STATE_OE);`
125			`assign wb_stb_o = (state == STATE_WE) \| (state == STATE_OE);`
126			`assign wb_we_o = (state == STATE_WE);`
127
128			`assign dbg_state = state;`
129
130			`endmodule`
131

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[/] [wb_async_mem_bridge/] [trunk/] [src/] [wb_async_mem_sm.v] - Blame information for rev 6