1 |
2 |
jvillar |
from myhdl import *
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3 |
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t_TxState = enum('tx_high_setup', 'tx_high_hold', 'tx_oneus', 'tx_low_setup', 'tx_low_hold', 'tx_fortyus', 'tx_done');
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4 |
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t_State = enum('display_init', 'init_fifteenms', 'init_one', 'init_two', 'init_three', 'init_four', 'init_five', 'init_six', 'init_seven', 'init_eight', 'display_function_set', 'display_entry_set', 'display_set_display', 'display_clr_display', 'display_pause_setup', 'display_pause', 'display_done', 'display_set_addr', 'display_char_write')
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6 |
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def delayCounter(clk, reset, count, load, done, width = 13):
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counter = Signal(intbv(0)[width:0])
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@always_comb
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def done_logic():
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done.next = (counter == 0)
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@always(clk.posedge)
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def countdown_logic():
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if load:
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counter.next = count
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else: #elif not done:
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counter.next = counter - 1
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return instances()
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def lcd(clk, reset, dat, addr, we, busy, SF_D, LCD_E, LCD_RS, LCD_RW):
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state = Signal(t_State.display_init)
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tx_state = Signal(t_TxState.tx_done)
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tx_byte = Signal(intbv(0)[8:0])
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31 |
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tx_init = Signal(bool())
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tx_done = Signal(bool())
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LCD_E0 = Signal(bool())
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SF_D0 = Signal(intbv(0)[4:0])
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LCD_E1 = Signal(bool())
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SF_D1 = Signal(intbv(0)[4:0])
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wr_dat = Signal(intbv(0)[7:0])
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wr_addr = Signal(intbv(0)[7:0])
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@always_comb
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def busy_and_rw_handlers():
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busy.next = (state != t_State.display_done)
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LCD_RW.next = 0
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44 |
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45 |
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#Delay counter
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main_delay_load = Signal(bool())
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main_delay_value = Signal(intbv(0)[20:0])
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tx_delay_load = Signal(bool())
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main_delay_load = Signal(bool())
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delay_load = Signal(bool())
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tx_delay_value = Signal(intbv(0)[20:0])
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main_delay_value = Signal(intbv(0)[20:0])
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delay_value = Signal(intbv(0)[20:0])
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57 |
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delay_done = Signal(bool())
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output_selector = Signal(bool())
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counter = delayCounter(clk, reset, delay_value, delay_load, delay_done, width = 21)
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@always_comb
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def conunter_sharing_load():
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delay_load.next = tx_delay_load or main_delay_load
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@always_comb
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def conunter_sharing_value():
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if tx_delay_load:
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delay_value.next = tx_delay_value
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else:
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delay_value.next = main_delay_value
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# SF_D and LCD_E management for sharing between Init and TX phases.
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@always_comb
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def output_tx_or_init_select(): # 0 tx; 1 init
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output_selector.next = (state == t_State.display_init) | (state == t_State.init_fifteenms) | (state == t_State.init_one) | (state == t_State.init_two) | (state == t_State.init_three) | (state == t_State.init_four) | (state == t_State.init_five) | (state == t_State.init_six) | (state == t_State.init_seven) | (state == t_State.init_eight)
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@always_comb
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def output_tx_or_init_mux():
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if output_selector: # Init
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SF_D.next = SF_D1
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LCD_E.next = LCD_E1
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else: # TX
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SF_D.next = SF_D0
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LCD_E.next = LCD_E0
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@always_comb
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def init_transmissions():
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tx_init.next = (~tx_done) & ((state == t_State.display_function_set) | (state == t_State.display_entry_set) | (state == t_State.display_set_display) | (state == t_State.display_clr_display) | (state == t_State.display_set_addr) | (state == t_State.display_char_write))
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LCD_RS.next = ~(bool(state == t_State.display_function_set) | (state == t_State.display_entry_set) | (state == t_State.display_set_display) | (state == t_State.display_clr_display) | (state == t_State.display_set_addr))
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@always(clk.posedge, reset.posedge)
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def DisplayFSM():
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if reset == 1:
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state.next = t_State.display_init
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main_delay_load.next = 0
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main_delay_value.next = 0
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SF_D1.next = 0
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LCD_E1.next = 0
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tx_byte.next = 0
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else:
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main_delay_load.next = 0;
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main_delay_value.next = 0;
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if state == t_State.display_init:
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tx_byte.next = 0 #00000000
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107 |
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108 |
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state.next = t_State.init_fifteenms
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109 |
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main_delay_load.next = 1
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main_delay_value.next = 750000
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elif state == t_State.init_fifteenms:
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main_delay_load.next = 0
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if delay_done:
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state.next = t_State.init_one;
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main_delay_load.next = 1
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main_delay_value.next = 11
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elif state == t_State.init_one:
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main_delay_load.next = 0
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SF_D1.next = 3
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LCD_E1.next = 1
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124 |
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125 |
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if delay_done:
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state.next = t_State.init_two;
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main_delay_load.next = 1
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128 |
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main_delay_value.next = 205000
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129 |
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130 |
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elif state == t_State.init_two:
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main_delay_load.next = 0
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132 |
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LCD_E1.next = 0
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133 |
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134 |
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if delay_done:
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state.next = t_State.init_three;
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main_delay_load.next = 1
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main_delay_value.next = 11
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138 |
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139 |
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elif state == t_State.init_three:
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140 |
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main_delay_load.next = 0
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141 |
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SF_D1.next = 3
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142 |
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LCD_E1.next = 1
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143 |
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144 |
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if delay_done:
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state.next = t_State.init_four;
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main_delay_load.next = 1
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main_delay_value.next = 5000
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148 |
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149 |
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elif state == t_State.init_four:
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main_delay_load.next = 0
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151 |
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LCD_E1.next = 0
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152 |
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153 |
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if delay_done:
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state.next = t_State.init_five;
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main_delay_load.next = 1
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156 |
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main_delay_value.next = 11
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158 |
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159 |
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elif state == t_State.init_five:
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main_delay_load.next = 0
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SF_D1.next = 3
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LCD_E1.next = 1
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163 |
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164 |
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if delay_done:
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state.next = t_State.init_six;
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main_delay_load.next = 1
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main_delay_value.next = 2000
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168 |
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169 |
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elif state == t_State.init_six:
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main_delay_load.next = 0
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LCD_E1.next = 0
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173 |
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if delay_done:
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state.next = t_State.init_seven;
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main_delay_load.next = 1
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main_delay_value.next = 11
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178 |
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elif state == t_State.init_seven:
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main_delay_load.next = 0
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180 |
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SF_D1.next = 2
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LCD_E1.next = 1
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183 |
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if delay_done:
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state.next = t_State.init_eight;
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main_delay_load.next = 1
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main_delay_value.next = 2000
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188 |
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elif state == t_State.init_eight:
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main_delay_load.next = 0
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LCD_E1.next = 0
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191 |
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192 |
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if delay_done:
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state.next = t_State.display_function_set;
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elif state == t_State.display_function_set:
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tx_byte.next = 40 #00101000
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if tx_done:
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state.next = t_State.display_entry_set
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elif state == t_State.display_entry_set:
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tx_byte.next = 6 #00000110
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if tx_done:
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state.next = t_State.display_set_display
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elif state == t_State.display_set_display:
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tx_byte.next = 12 #00001100
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if tx_done:
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state.next = t_State.display_clr_display
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210 |
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elif state == t_State.display_clr_display:
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tx_byte.next = 1 #00000001
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if tx_done:
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state.next = t_State.display_pause #_setup
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main_delay_load.next = 1
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main_delay_value.next = 82000
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217 |
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elif state == t_State.display_pause_setup:
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state.next = t_State.display_pause
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220 |
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elif state == t_State.display_pause:
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tx_byte.next = 0 #00000000
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222 |
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223 |
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if delay_done:
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state.next = t_State.display_done;
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226 |
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elif state == t_State.display_done:
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tx_byte.next = 0 #00000000
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228 |
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229 |
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if we:
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state.next = t_State.display_set_addr
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wr_addr.next = addr
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232 |
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wr_dat.next = dat
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else:
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state.next = t_State.display_done
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236 |
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elif state == t_State.display_set_addr:
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237 |
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tx_byte.next = 128 | wr_addr #10000000 + addr[6:0]
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238 |
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if tx_done:
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239 |
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state.next = t_State.display_char_write
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240 |
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241 |
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elif state == t_State.display_char_write:
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tx_byte.next = wr_dat
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if tx_done:
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state.next = t_State.display_done;
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# else:
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# raise ValueError("Undefined Display state")
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247 |
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248 |
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249 |
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250 |
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@always(clk.posedge, reset.posedge)
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def TxFSM():
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if reset == 1:
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tx_state.next = t_TxState.tx_done
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254 |
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SF_D0.next = 0
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255 |
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LCD_E0.next = 0
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256 |
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else:
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257 |
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tx_delay_load.next = 0;
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258 |
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tx_delay_value.next = 0;
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259 |
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if tx_state == t_TxState.tx_high_setup:
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260 |
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LCD_E0.next = 0
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261 |
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SF_D0.next = tx_byte[8 : 4]
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262 |
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tx_delay_load.next = 0
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263 |
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if delay_done:
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264 |
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tx_state.next = t_TxState.tx_high_hold
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265 |
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tx_delay_load.next = 1
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266 |
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tx_delay_value.next = 12
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267 |
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268 |
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elif tx_state == t_TxState.tx_high_hold:
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269 |
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LCD_E0.next = 1
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270 |
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SF_D0.next = tx_byte[8 : 4]
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271 |
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tx_delay_load.next = 0
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272 |
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if delay_done:
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273 |
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tx_state.next = t_TxState.tx_oneus
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274 |
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tx_delay_load.next = 1
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275 |
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tx_delay_value.next = 50
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276 |
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277 |
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elif tx_state == t_TxState.tx_oneus:
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278 |
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LCD_E0.next = 0
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279 |
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tx_delay_load.next = 0
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280 |
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if delay_done:
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281 |
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tx_state.next = t_TxState.tx_low_setup
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282 |
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tx_delay_load.next = 1
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283 |
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tx_delay_value.next = 2
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284 |
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285 |
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elif tx_state == t_TxState.tx_low_setup:
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286 |
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LCD_E0.next = 0
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287 |
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SF_D0.next = tx_byte[4 : 0]
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288 |
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tx_delay_load.next = 0
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289 |
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if delay_done:
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290 |
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tx_state.next = t_TxState.tx_low_hold
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291 |
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tx_delay_load.next = 1
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292 |
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tx_delay_value.next = 12
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293 |
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294 |
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elif tx_state == t_TxState.tx_low_hold:
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295 |
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LCD_E0.next = 1
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296 |
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SF_D0.next = tx_byte[4 : 0]
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297 |
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tx_delay_load.next = 0
|
298 |
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if delay_done:
|
299 |
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tx_state.next = t_TxState.tx_fortyus
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300 |
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tx_delay_load.next = 1
|
301 |
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tx_delay_value.next = 2000
|
302 |
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|
303 |
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elif tx_state == t_TxState.tx_fortyus:
|
304 |
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LCD_E0.next = 0
|
305 |
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tx_delay_load.next = 0
|
306 |
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if delay_done:
|
307 |
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tx_state.next = t_TxState.tx_done
|
308 |
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tx_done.next = 1
|
309 |
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|
310 |
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elif tx_state == t_TxState.tx_done:
|
311 |
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LCD_E0.next = 0
|
312 |
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tx_done.next = 0
|
313 |
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tx_delay_load.next = 0
|
314 |
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if tx_init:
|
315 |
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tx_state.next = t_TxState.tx_high_setup
|
316 |
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tx_delay_load.next = 1
|
317 |
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tx_delay_value.next = 2
|
318 |
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# else:
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319 |
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# raise ValueError("Undefined TX state")
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320 |
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|
321 |
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return instances()
|
322 |
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323 |
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|
324 |
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def wb_lcd(wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, SF_D, LCD_E, LCD_RS, LCD_RW):
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325 |
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|
326 |
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busy = Signal(bool(0))
|
327 |
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lcd_we = Signal(bool(0))
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328 |
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#wb_dat_o = Signal(intbv(0)[32:0])
|
329 |
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#wb_ack_o = Signal(bool(0))
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330 |
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|
331 |
|
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status_register_address = 128
|
332 |
|
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status_register_busy = 1
|
333 |
|
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status_register_iddle = 0
|
334 |
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|
335 |
|
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@always_comb
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336 |
|
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def wishbone_logic():
|
337 |
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wb_ack_o.next = wb_cyc_i & wb_stb_i;
|
338 |
|
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lcd_we.next = wb_cyc_i & wb_stb_i & wb_we_i & (wb_adr_i != status_register_address)
|
339 |
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if busy:
|
340 |
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wb_dat_o.next = status_register_busy
|
341 |
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else:
|
342 |
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wb_dat_o.next = status_register_iddle
|
343 |
|
|
|
344 |
|
|
mylcd = lcd (wb_clk_i, wb_rst_i, wb_dat_i, wb_adr_i, lcd_we, busy, SF_D, LCD_E, LCD_RS, LCD_RW)
|
345 |
|
|
|
346 |
|
|
return instances()
|
347 |
|
|
|
348 |
|
|
def generate_wb_lcd():
|
349 |
|
|
wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_ack_o = [Signal(bool(0)) for i in range(6)]
|
350 |
|
|
wb_dat_o, wb_dat_i, wb_adr_i = [ Signal(intbv(0)[32:0]) for i in range(3)]
|
351 |
|
|
wb_sel_i = Signal(intbv(0)[4:0])
|
352 |
|
|
|
353 |
|
|
SF_D = Signal(intbv(0)[4:0])
|
354 |
|
|
LCD_E, LCD_RS, LCD_RW = [Signal(bool(0)) for i in range(3)]
|
355 |
|
|
|
356 |
|
|
toVerilog(wb_lcd, wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, SF_D, LCD_E, LCD_RS, LCD_RW)
|
357 |
|
|
toVHDL(wb_lcd, wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, SF_D, LCD_E, LCD_RS, LCD_RW)
|
358 |
|
|
|
359 |
|
|
|
360 |
|
|
def generate_mm_lcd():
|
361 |
|
|
clk, reset, we, busy, LCD_E, LCD_RS, LCD_RW = [Signal(bool(0)) for i in range(7)]
|
362 |
|
|
dat = Signal(intbv(0)[32:0])
|
363 |
|
|
addr = Signal(intbv(0)[7:0])
|
364 |
|
|
SF_D = Signal(intbv(0)[4:0])
|
365 |
|
|
|
366 |
|
|
toVerilog(lcd, clk, reset, dat, addr, we, busy, SF_D, LCD_E, LCD_RS, LCD_RW)
|
367 |
|
|
toVHDL(lcd, clk, reset, dat, addr, we, busy, SF_D, LCD_E, LCD_RS, LCD_RW)
|
368 |
|
|
|
369 |
|
|
|
370 |
|
|
def main():
|
371 |
|
|
generate_wb_lcd()
|
372 |
|
|
|
373 |
|
|
if __name__ == '__main__':
|
374 |
|
|
main()
|
375 |
|
|
|