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[/] [wb_size_bridge/] [trunk/] [tb/] [models/] [wb_master_model.v] - Blame information for rev 2

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///////////////////////////////////////////////////////////////////////
////                                                               ////
////  WISHBONE rev.B2 Wishbone Master model                        ////
////                                                               ////
////                                                               ////
////  Author: Richard Herveille                                    ////
////          richard@asics.ws                                     ////
////          www.asics.ws                                         ////
////                                                               ////
////  Downloaded from: http://www.opencores.org/projects/mem_ctrl  ////
////                                                               ////
///////////////////////////////////////////////////////////////////////
////                                                               ////
//// Copyright (C) 2001 Richard Herveille                          ////
////                    richard@asics.ws                           ////
////                                                               ////
//// This source file may be used and distributed without          ////
//// restriction provided that this copyright statement is not     ////
//// removed from the file and that any derivative work contains   ////
//// the original copyright notice and the associated disclaimer.  ////
////                                                               ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY       ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS     ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR        ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,           ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES      ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE     ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR          ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT    ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE           ////
//// POSSIBILITY OF SUCH DAMAGE.                                   ////
////                                                               ////
///////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_master_model.v,v 1.1 2009/02/19 23:51:32 kenagy Exp $
//
//  $Date: 2009/02/19 23:51:32 $
//  $Revision: 1.1 $
//  $Author: kenagy $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//
 
`timescale 1ns/10ps
 
 
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
 
  //
  // parameters
  //
  parameter dwidth = 32;
  parameter awidth = 32;
 
  parameter log_level = 3;
 
  //
  // inputs & outputs
  //
  input                  clk, rst;
  output [awidth   -1:0]  adr;
  input  [dwidth   -1:0]  din;
  output [dwidth   -1:0]  dout;
  output                 cyc, stb;
  output                  we;
  output [dwidth/8 -1:0] sel;
  input                   ack, err, rty;
 
  //
  // variables
  //
  reg [awidth   -1:0] adr;
  reg [dwidth   -1:0] dout;
  reg                  cyc, stb;
  reg                  we;
  reg [dwidth/8 -1:0] sel;
 
  reg [dwidth   -1:0] q;
 
  integer err_cur_cnt, err_tot_cnt, err_wb_cnt, err_watchdog;
 
 
  //
  // module body
  //
 
  // check ack, err and rty assertion
  always@(ack or err or rty)
  begin
    case ({ack, err, rty})
      // ok-states
//      3'b000: // none asserted
//      3'b001: // only rty asserted
//      3'b010: // only err asserted
//      3'b100: // only ack asserted
 
      // fault-states
      3'b011: // oops, err and rty
        begin
          err_wb_cnt = err_wb_cnt +1;
          $display("Wishbone error: ERR_I and RTY_I are both asserted at time %t.", $time);
        end
      3'b101: // oops, ack and rty
        begin
          err_wb_cnt = err_wb_cnt +1;
          $display("Wishbone error: ACK_I and RTY_I are both asserted at time %t.", $time);
        end
      3'b110: // oops, ack and err
        begin
          err_wb_cnt = err_wb_cnt +1;
          $display("Wishbone error: ACK_I and ERR_I are both asserted at time %t.", $time);
        end
      3'b111: // oops, ack, err and rty
        begin
          err_wb_cnt = err_wb_cnt +1;
          $display("Wishbone error: ACK_I, ERR_I and RTY_I are all asserted at time %t.", $time);
        end
    endcase
 
    if (err_wb_cnt > err_watchdog)
      begin
        $display("\n!!!-Testbench stopped. More than %d wishbone errors detected.\n", err_watchdog);
        $stop;
      end
  end
 
  // initial settings
  initial
  begin
    //adr = 32'hxxxx_xxxx;
    //adr = 0;
    adr  = {awidth{1'bx}};
    dout = {dwidth{1'bx}};
    cyc  = 1'b0;
    stb  = 1'bx;
    we   = 1'hx;
    sel  = {dwidth/8{1'bx}};
 
    err_tot_cnt = 0;
    err_cur_cnt = 0;
    err_wb_cnt  = 0;
    err_watchdog = 3;
 
    #1;
    $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
  end
 
 
  ////////////////////////////
  //
  // Wishbone write cycle
  //
 
  task wb_write;
    input   delay;
    integer delay;
    input   stb_delay;
    integer stb_delay;
 
    input [awidth -1:0] a;
    input [dwidth -1:0] d;
 
  begin
 
    if( log_level > 2 )
      $display( "###- wb_write: 0x%h @ 0x%h at time %t. ", d, a, $time );
 
    // wait initial delay
    repeat(delay) @(posedge clk);
 
    #1;
    // assert cyc_signal
    cyc  = 1'b1;
    stb  = 1'b0;
 
    // wait for stb_assertion
    repeat(stb_delay) @(posedge clk);
 
    // assert wishbone signals
    adr  = a;
    dout = d;
    stb  = 1'b1;
    we   = 1'b1;
    sel  = {dwidth/8{1'b1}};
    @(posedge clk);
 
    // wait for acknowledge from slave
    // err is treated as normal ack
    // rty is ignored (thus retrying cycle)
    while(~ (ack || err)) @(posedge clk);
 
    // negate wishbone signals
    #1;
    cyc  = 1'b0;
    stb  = 1'bx;
    adr  = {awidth{1'bx}};
    dout = {dwidth{1'bx}};
    we   = 1'hx;
    sel  = {dwidth/8{1'bx}};
 
  end
  endtask
 
  task wb_write_sel;
    input   delay;
    integer delay;
    input   stb_delay;
    integer stb_delay;
 
    input [dwidth/8 -1:0] s;
    input [awidth   -1:0] a;
    input [dwidth   -1:0] d;
 
  begin
 
    if( log_level > 2 )
      $display( "###- wb_write_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );
 
    // wait initial delay
    repeat(delay) @(posedge clk);
 
    #1;
    // assert cyc_signal
    cyc  = 1'b1;
    stb  = 1'b0;
 
    // wait for stb_assertion
    repeat(stb_delay) @(posedge clk);
 
    // assert wishbone signals
    adr  = a;
    dout = d;
    stb  = 1'b1;
    we   = 1'b1;
    sel  = s;
    @(posedge clk);
 
    // wait for acknowledge from slave
    // err is treated as normal ack
    // rty is ignored (thus retrying cycle)
    while(~ (ack || err)) @(posedge clk);
 
    // negate wishbone signals
    #1;
    cyc  = 1'b0;
    stb  = 1'bx;
    adr  = {awidth{1'bx}};
    dout = {dwidth{1'bx}};
    we   = 1'hx;
    sel  = {dwidth/8{1'bx}};
 
  end
  endtask
 
  ////////////////////////////
  //
  // Wishbone read cycle
  //
 
  task wb_read;
    input   delay;
    integer delay;
    input   stb_delay;
    integer stb_delay;
 
    input  [awidth -1:0]  a;
    output  [dwidth -1:0] d;
 
  begin
 
    // wait initial delay
    repeat(delay) @(posedge clk);
 
    #1;
    // assert cyc_signal
    cyc  = 1'b1;
    stb  = 1'b0;
 
    // wait for stb_assertion
    repeat(stb_delay) @(posedge clk);
 
    // assert wishbone signals
    adr  = a;
    dout = {dwidth{1'bx}};
    stb  = 1'b1;
    we   = 1'b0;
    sel  = {dwidth/8{1'b1}};
    @(posedge clk);
 
    // wait for acknowledge from slave
    // err is treated as normal ack
    // rty is ignored (thus retrying cycle)
    while(~ (ack || err)) @(posedge clk);
 
    // negate wishbone signals
    #1;
    cyc  = 1'b0;
    stb  = 1'bx;
    adr  = {awidth{1'bx}};
    dout = {dwidth{1'bx}};
    we   = 1'hx;
    sel  = {dwidth/8{1'bx}};
    d    = din;
 
    if( log_level > 2 )
      $display( "###- wb_read: 0x%h @ 0x%h at time %t. ", d, a, $time );
  end
  endtask
 
  task wb_read_sel;
    input   delay;
    integer delay;
    input   stb_delay;
    integer stb_delay;
 
    input  [dwidth/8 -1:0] s;
    input  [awidth   -1:0]  a;
    output  [dwidth   -1:0] d;
 
  begin
 
    // wait initial delay
    repeat(delay) @(posedge clk);
 
    #1;
    // assert cyc_signal
    cyc  = 1'b1;
    stb  = 1'b0;
 
    // wait for stb_assertion
    repeat(stb_delay) @(posedge clk);
 
    // assert wishbone signals
    adr  = a;
    dout = {dwidth{1'bx}};
    stb  = 1'b1;
    we   = 1'b0;
    sel  = s;
    @(posedge clk);
 
    // wait for acknowledge from slave
    // err is treated as normal ack
    // rty is ignored (thus retrying cycle)
    while(~ (ack || err)) @(posedge clk);
 
    // negate wishbone signals
    #1;
    cyc  = 1'b0;
    stb  = 1'bx;
    adr  = {awidth{1'bx}};
    dout = {dwidth{1'bx}};
    we   = 1'hx;
    sel  = {dwidth/8{1'bx}};
    d    = din;
 
    if( log_level > 2 )
      $display( "###- wb_read_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );
  end
  endtask
 
  ////////////////////////////
  //
  // Wishbone compare cycle
  // read data from location and compare with expected data
  //
 
  task wb_cmp;
    input   delay;
    integer delay;
    input   stb_delay;
    integer stb_delay;
 
    input [awidth -1:0] a;
    input [dwidth -1:0] d_exp;
 
  begin
    wb_read (delay, stb_delay, a, q);
 
    if (d_exp !== q)
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);
      end
 
    if (err_tot_cnt > err_watchdog)
      begin
        $display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);
        $stop;
      end
  end
  endtask
 
 
  task wb_cmp_sel;
    input   delay;
    integer delay;
    input   stb_delay;
    integer stb_delay;
 
    input  [dwidth/8 -1:0] s;
    input [awidth -1:0] a;
    input [dwidth -1:0] d_exp;
 
  begin
    wb_read_sel (delay, stb_delay, s, a, q);
 
    if( (d_exp[7:0] !== q[7:0]) & s == 4'b0001 )
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[7:0], d_exp[7:0], a);
      end
 
    if( (d_exp[15:8] !== q[15:8]) & s == 4'b0010 )
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:8], d_exp[15:8], a);
      end
 
    if( (d_exp[23:16] !== q[23:16]) & s == 4'b0100 )
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[23:16], d_exp[23:16], a);
      end
 
    if( (d_exp[31:24] !== q[31:24]) & s == 4'b1000 )
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:24], d_exp[31:24], a);
      end
 
    if( (d_exp[15:0] !== q[15:0]) & s == 4'b0011 )
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:0], d_exp[15:0], a);
      end
 
    if( (d_exp[31:16] !== q[31:16]) & s == 4'b1100 )
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:16], d_exp[31:16], a);
      end
 
    if( (d_exp !== q) & s == 4'b1111 )
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);
      end
 
      case( s )
        4'b0001:  ;
        4'b0010:  ;
        4'b0100:  ;
        4'b1000:  ;
        4'b0011:  ;
        4'b1100:  ;
        4'b1111:  ;
        default:  $display( "!!!- Data compare error(%d) at time %t. Invalad byte select.", err_tot_cnt, $time );
      endcase
 
 
    if (err_tot_cnt > err_watchdog)
      begin
        $display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);
        $stop;
      end
  end
  endtask
 
 
  ////////////////////////////
  //
  // Error counter handlers
  //
  task set_cur_err_cnt;
    input value;
  begin
    err_cur_cnt = value;
  end
  endtask
 
  task show_cur_err_cnt;
    $display("\nCurrent errors detected: %d\n", err_cur_cnt);
  endtask
 
  task show_tot_err_cnt;
    $display("\nTotal errors detected: %d\n", err_tot_cnt);
  endtask
 
 
  always @(posedge clk)
    if( err & (cyc == 1'b1) & (stb == 1'b1) )
      $display( "!!!- WB Bus Error at time %t. ", $time );
 
endmodule
 

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Subversion Repositories wb_size_bridge

[/] [wb_size_bridge/] [trunk/] [tb/] [models/] [wb_master_model.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	qaztronic	`///////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 Wishbone Master model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////`
11			`//// ////`
12			`///////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`///////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40			`// $Id: wb_master_model.v,v 1.1 2009/02/19 23:51:32 kenagy Exp $`
41			`//`
42			`// $Date: 2009/02/19 23:51:32 $`
43			`// $Revision: 1.1 $`
44			`// $Author: kenagy $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`//`
50
51			`timescale 1ns/10ps
52
53
54			`module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);`
55
56			`//`
57			`// parameters`
58			`//`
59			`parameter dwidth = 32;`
60			`parameter awidth = 32;`
61
62			`parameter log_level = 3;`
63
64			`//`
65			`// inputs & outputs`
66			`//`
67			`input clk, rst;`
68			`output [awidth -1:0] adr;`
69			`input [dwidth -1:0] din;`
70			`output [dwidth -1:0] dout;`
71			`output cyc, stb;`
72			`output we;`
73			`output [dwidth/8 -1:0] sel;`
74			`input ack, err, rty;`
75
76			`//`
77			`// variables`
78			`//`
79			`reg [awidth -1:0] adr;`
80			`reg [dwidth -1:0] dout;`
81			`reg cyc, stb;`
82			`reg we;`
83			`reg [dwidth/8 -1:0] sel;`
84
85			`reg [dwidth -1:0] q;`
86
87			`integer err_cur_cnt, err_tot_cnt, err_wb_cnt, err_watchdog;`
88
89
90			`//`
91			`// module body`
92			`//`
93
94			`// check ack, err and rty assertion`
95			`always@(ack or err or rty)`
96			`begin`
97			`case ({ack, err, rty})`
98			`// ok-states`
99			`// 3'b000: // none asserted`
100			`// 3'b001: // only rty asserted`
101			`// 3'b010: // only err asserted`
102			`// 3'b100: // only ack asserted`
103
104			`// fault-states`
105			`3'b011: // oops, err and rty`
106			`begin`
107			`err_wb_cnt = err_wb_cnt +1;`
108			`$display("Wishbone error: ERR_I and RTY_I are both asserted at time %t.", $time);`
109			`end`
110			`3'b101: // oops, ack and rty`
111			`begin`
112			`err_wb_cnt = err_wb_cnt +1;`
113			`$display("Wishbone error: ACK_I and RTY_I are both asserted at time %t.", $time);`
114			`end`
115			`3'b110: // oops, ack and err`
116			`begin`
117			`err_wb_cnt = err_wb_cnt +1;`
118			`$display("Wishbone error: ACK_I and ERR_I are both asserted at time %t.", $time);`
119			`end`
120			`3'b111: // oops, ack, err and rty`
121			`begin`
122			`err_wb_cnt = err_wb_cnt +1;`
123			`$display("Wishbone error: ACK_I, ERR_I and RTY_I are all asserted at time %t.", $time);`
124			`end`
125			`endcase`
126
127			`if (err_wb_cnt > err_watchdog)`
128			`begin`
129			`$display("\n!!!-Testbench stopped. More than %d wishbone errors detected.\n", err_watchdog);`
130			`$stop;`
131			`end`
132			`end`
133
134			`// initial settings`
135			`initial`
136			`begin`
137			`//adr = 32'hxxxx_xxxx;`
138			`//adr = 0;`
139			`adr = {awidth{1'bx}};`
140			`dout = {dwidth{1'bx}};`
141			`cyc = 1'b0;`
142			`stb = 1'bx;`
143			`we = 1'hx;`
144			`sel = {dwidth/8{1'bx}};`
145
146			`err_tot_cnt = 0;`
147			`err_cur_cnt = 0;`
148			`err_wb_cnt = 0;`
149			`err_watchdog = 3;`
150
151			`#1;`
152			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");`
153			`end`
154
155
156			`////////////////////////////`
157			`//`
158			`// Wishbone write cycle`
159			`//`
160
161			`task wb_write;`
162			`input delay;`
163			`integer delay;`
164			`input stb_delay;`
165			`integer stb_delay;`
166
167			`input [awidth -1:0] a;`
168			`input [dwidth -1:0] d;`
169
170			`begin`
171
172			`if( log_level > 2 )`
173			`$display( "###- wb_write: 0x%h @ 0x%h at time %t. ", d, a, $time );`
174
175			`// wait initial delay`
176			`repeat(delay) @(posedge clk);`
177
178			`#1;`
179			`// assert cyc_signal`
180			`cyc = 1'b1;`
181			`stb = 1'b0;`
182
183			`// wait for stb_assertion`
184			`repeat(stb_delay) @(posedge clk);`
185
186			`// assert wishbone signals`
187			`adr = a;`
188			`dout = d;`
189			`stb = 1'b1;`
190			`we = 1'b1;`
191			`sel = {dwidth/8{1'b1}};`
192			`@(posedge clk);`
193
194			`// wait for acknowledge from slave`
195			`// err is treated as normal ack`
196			`// rty is ignored (thus retrying cycle)`
197			`while(~ (ack \|\| err)) @(posedge clk);`
198
199			`// negate wishbone signals`
200			`#1;`
201			`cyc = 1'b0;`
202			`stb = 1'bx;`
203			`adr = {awidth{1'bx}};`
204			`dout = {dwidth{1'bx}};`
205			`we = 1'hx;`
206			`sel = {dwidth/8{1'bx}};`
207
208			`end`
209			`endtask`
210
211			`task wb_write_sel;`
212			`input delay;`
213			`integer delay;`
214			`input stb_delay;`
215			`integer stb_delay;`
216
217			`input [dwidth/8 -1:0] s;`
218			`input [awidth -1:0] a;`
219			`input [dwidth -1:0] d;`
220
221			`begin`
222
223			`if( log_level > 2 )`
224			`$display( "###- wb_write_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );`
225
226			`// wait initial delay`
227			`repeat(delay) @(posedge clk);`
228
229			`#1;`
230			`// assert cyc_signal`
231			`cyc = 1'b1;`
232			`stb = 1'b0;`
233
234			`// wait for stb_assertion`
235			`repeat(stb_delay) @(posedge clk);`
236
237			`// assert wishbone signals`
238			`adr = a;`
239			`dout = d;`
240			`stb = 1'b1;`
241			`we = 1'b1;`
242			`sel = s;`
243			`@(posedge clk);`
244
245			`// wait for acknowledge from slave`
246			`// err is treated as normal ack`
247			`// rty is ignored (thus retrying cycle)`
248			`while(~ (ack \|\| err)) @(posedge clk);`
249
250			`// negate wishbone signals`
251			`#1;`
252			`cyc = 1'b0;`
253			`stb = 1'bx;`
254			`adr = {awidth{1'bx}};`
255			`dout = {dwidth{1'bx}};`
256			`we = 1'hx;`
257			`sel = {dwidth/8{1'bx}};`
258
259			`end`
260			`endtask`
261
262			`////////////////////////////`
263			`//`
264			`// Wishbone read cycle`
265			`//`
266
267			`task wb_read;`
268			`input delay;`
269			`integer delay;`
270			`input stb_delay;`
271			`integer stb_delay;`
272
273			`input [awidth -1:0] a;`
274			`output [dwidth -1:0] d;`
275
276			`begin`
277
278			`// wait initial delay`
279			`repeat(delay) @(posedge clk);`
280
281			`#1;`
282			`// assert cyc_signal`
283			`cyc = 1'b1;`
284			`stb = 1'b0;`
285
286			`// wait for stb_assertion`
287			`repeat(stb_delay) @(posedge clk);`
288
289			`// assert wishbone signals`
290			`adr = a;`
291			`dout = {dwidth{1'bx}};`
292			`stb = 1'b1;`
293			`we = 1'b0;`
294			`sel = {dwidth/8{1'b1}};`
295			`@(posedge clk);`
296
297			`// wait for acknowledge from slave`
298			`// err is treated as normal ack`
299			`// rty is ignored (thus retrying cycle)`
300			`while(~ (ack \|\| err)) @(posedge clk);`
301
302			`// negate wishbone signals`
303			`#1;`
304			`cyc = 1'b0;`
305			`stb = 1'bx;`
306			`adr = {awidth{1'bx}};`
307			`dout = {dwidth{1'bx}};`
308			`we = 1'hx;`
309			`sel = {dwidth/8{1'bx}};`
310			`d = din;`
311
312			`if( log_level > 2 )`
313			`$display( "###- wb_read: 0x%h @ 0x%h at time %t. ", d, a, $time );`
314			`end`
315			`endtask`
316
317			`task wb_read_sel;`
318			`input delay;`
319			`integer delay;`
320			`input stb_delay;`
321			`integer stb_delay;`
322
323			`input [dwidth/8 -1:0] s;`
324			`input [awidth -1:0] a;`
325			`output [dwidth -1:0] d;`
326
327			`begin`
328
329			`// wait initial delay`
330			`repeat(delay) @(posedge clk);`
331
332			`#1;`
333			`// assert cyc_signal`
334			`cyc = 1'b1;`
335			`stb = 1'b0;`
336
337			`// wait for stb_assertion`
338			`repeat(stb_delay) @(posedge clk);`
339
340			`// assert wishbone signals`
341			`adr = a;`
342			`dout = {dwidth{1'bx}};`
343			`stb = 1'b1;`
344			`we = 1'b0;`
345			`sel = s;`
346			`@(posedge clk);`
347
348			`// wait for acknowledge from slave`
349			`// err is treated as normal ack`
350			`// rty is ignored (thus retrying cycle)`
351			`while(~ (ack \|\| err)) @(posedge clk);`
352
353			`// negate wishbone signals`
354			`#1;`
355			`cyc = 1'b0;`
356			`stb = 1'bx;`
357			`adr = {awidth{1'bx}};`
358			`dout = {dwidth{1'bx}};`
359			`we = 1'hx;`
360			`sel = {dwidth/8{1'bx}};`
361			`d = din;`
362
363			`if( log_level > 2 )`
364			`$display( "###- wb_read_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );`
365			`end`
366			`endtask`
367
368			`////////////////////////////`
369			`//`
370			`// Wishbone compare cycle`
371			`// read data from location and compare with expected data`
372			`//`
373
374			`task wb_cmp;`
375			`input delay;`
376			`integer delay;`
377			`input stb_delay;`
378			`integer stb_delay;`
379
380			`input [awidth -1:0] a;`
381			`input [dwidth -1:0] d_exp;`
382
383			`begin`
384			`wb_read (delay, stb_delay, a, q);`
385
386			`if (d_exp !== q)`
387			`begin`
388			`err_tot_cnt = err_tot_cnt +1;`
389			`err_cur_cnt = err_cur_cnt +1;`
390			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);`
391			`end`
392
393			`if (err_tot_cnt > err_watchdog)`
394			`begin`
395			`$display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);`
396			`$stop;`
397			`end`
398			`end`
399			`endtask`
400
401
402			`task wb_cmp_sel;`
403			`input delay;`
404			`integer delay;`
405			`input stb_delay;`
406			`integer stb_delay;`
407
408			`input [dwidth/8 -1:0] s;`
409			`input [awidth -1:0] a;`
410			`input [dwidth -1:0] d_exp;`
411
412			`begin`
413			`wb_read_sel (delay, stb_delay, s, a, q);`
414
415			`if( (d_exp[7:0] !== q[7:0]) & s == 4'b0001 )`
416			`begin`
417			`err_tot_cnt = err_tot_cnt +1;`
418			`err_cur_cnt = err_cur_cnt +1;`
419			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[7:0], d_exp[7:0], a);`
420			`end`
421
422			`if( (d_exp[15:8] !== q[15:8]) & s == 4'b0010 )`
423			`begin`
424			`err_tot_cnt = err_tot_cnt +1;`
425			`err_cur_cnt = err_cur_cnt +1;`
426			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:8], d_exp[15:8], a);`
427			`end`
428
429			`if( (d_exp[23:16] !== q[23:16]) & s == 4'b0100 )`
430			`begin`
431			`err_tot_cnt = err_tot_cnt +1;`
432			`err_cur_cnt = err_cur_cnt +1;`
433			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[23:16], d_exp[23:16], a);`
434			`end`
435
436			`if( (d_exp[31:24] !== q[31:24]) & s == 4'b1000 )`
437			`begin`
438			`err_tot_cnt = err_tot_cnt +1;`
439			`err_cur_cnt = err_cur_cnt +1;`
440			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:24], d_exp[31:24], a);`
441			`end`
442
443			`if( (d_exp[15:0] !== q[15:0]) & s == 4'b0011 )`
444			`begin`
445			`err_tot_cnt = err_tot_cnt +1;`
446			`err_cur_cnt = err_cur_cnt +1;`
447			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:0], d_exp[15:0], a);`
448			`end`
449
450			`if( (d_exp[31:16] !== q[31:16]) & s == 4'b1100 )`
451			`begin`
452			`err_tot_cnt = err_tot_cnt +1;`
453			`err_cur_cnt = err_cur_cnt +1;`
454			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:16], d_exp[31:16], a);`
455			`end`
456
457			`if( (d_exp !== q) & s == 4'b1111 )`
458			`begin`
459			`err_tot_cnt = err_tot_cnt +1;`
460			`err_cur_cnt = err_cur_cnt +1;`
461			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);`
462			`end`
463
464			`case( s )`
465			`4'b0001: ;`
466			`4'b0010: ;`
467			`4'b0100: ;`
468			`4'b1000: ;`
469			`4'b0011: ;`
470			`4'b1100: ;`
471			`4'b1111: ;`
472			`default: $display( "!!!- Data compare error(%d) at time %t. Invalad byte select.", err_tot_cnt, $time );`
473			`endcase`
474
475
476			`if (err_tot_cnt > err_watchdog)`
477			`begin`
478			`$display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);`
479			`$stop;`
480			`end`
481			`end`
482			`endtask`
483
484
485			`////////////////////////////`
486			`//`
487			`// Error counter handlers`
488			`//`
489			`task set_cur_err_cnt;`
490			`input value;`
491			`begin`
492			`err_cur_cnt = value;`
493			`end`
494			`endtask`
495
496			`task show_cur_err_cnt;`
497			`$display("\nCurrent errors detected: %d\n", err_cur_cnt);`
498			`endtask`
499
500			`task show_tot_err_cnt;`
501			`$display("\nTotal errors detected: %d\n", err_tot_cnt);`
502			`endtask`
503
504
505			`always @(posedge clk)`
506			`if( err & (cyc == 1'b1) & (stb == 1'b1) )`
507			`$display( "!!!- WB Bus Error at time %t. ", $time );`
508
509			`endmodule`
510