| 1 |
4 |
dgisselq |
////////////////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//
|
| 3 |
|
|
// Filename: ddrsdram_tb.cpp
|
| 4 |
|
|
//
|
| 5 |
|
|
// Project: A wishbone controlled DDR3 SDRAM memory controller.
|
| 6 |
|
|
//
|
| 7 |
|
|
// Purpose: To determine whether or not the wbddrsdram Verilog module works.
|
| 8 |
|
|
// Run this program with no arguments. If the last line output
|
| 9 |
|
|
// is "SUCCESS", you will know it works.
|
| 10 |
|
|
//
|
| 11 |
|
|
// Creator: Dan Gisselquist, Ph.D.
|
| 12 |
|
|
// Gisselquist Technology, LLC
|
| 13 |
|
|
//
|
| 14 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 15 |
|
|
//
|
| 16 |
|
|
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
|
| 17 |
|
|
//
|
| 18 |
|
|
// This program is free software (firmware): you can redistribute it and/or
|
| 19 |
|
|
// modify it under the terms of the GNU General Public License as published
|
| 20 |
|
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
| 21 |
|
|
// your option) any later version.
|
| 22 |
|
|
//
|
| 23 |
|
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
| 24 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
| 25 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 26 |
|
|
// for more details.
|
| 27 |
|
|
//
|
| 28 |
|
|
// You should have received a copy of the GNU General Public License along
|
| 29 |
|
|
// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
| 30 |
|
|
// target there if the PDF file isn't present.) If not, see
|
| 31 |
|
|
// <http://www.gnu.org/licenses/> for a copy.
|
| 32 |
|
|
//
|
| 33 |
|
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
| 34 |
|
|
// http://www.gnu.org/licenses/gpl.html
|
| 35 |
|
|
//
|
| 36 |
|
|
//
|
| 37 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 38 |
|
|
//
|
| 39 |
|
|
//
|
| 40 |
|
|
#include <stdio.h>
|
| 41 |
|
|
|
| 42 |
|
|
#include "verilated.h"
|
| 43 |
|
|
#include "Vwbddrsdram.h"
|
| 44 |
|
|
#include "ddrsdramsim.h"
|
| 45 |
|
|
|
| 46 |
|
|
const int BOMBCOUNT = 2048,
|
| 47 |
|
|
SDRAMMASK = 0x3ffffff,
|
| 48 |
|
|
LGMEMSIZE = 28;
|
| 49 |
|
|
|
| 50 |
|
|
class DDRSDRAM_TB {
|
| 51 |
|
|
long m_tickcount;
|
| 52 |
|
|
Vwbddrsdram *m_core;
|
| 53 |
|
|
DDRSDRAMSIM *m_sdram;
|
| 54 |
|
|
bool m_bomb;
|
| 55 |
|
|
public:
|
| 56 |
|
|
|
| 57 |
|
|
DDRSDRAM_TB(void) {
|
| 58 |
|
|
m_core = new Vwbddrsdram;
|
| 59 |
|
|
m_sdram= new DDRSDRAMSIM(LGMEMSIZE);
|
| 60 |
|
|
}
|
| 61 |
|
|
|
| 62 |
|
|
unsigned &operator[](const int index) { return (*m_sdram)[index]; }
|
| 63 |
|
|
void set(unsigned addr, unsigned v) {
|
| 64 |
|
|
(*m_sdram)[addr] = v;
|
| 65 |
|
|
}
|
| 66 |
|
|
|
| 67 |
|
|
void tick(void) {
|
| 68 |
|
|
m_core->i_clk = 1;
|
| 69 |
|
|
|
| 70 |
|
|
m_core->i_ddr_data = (*m_sdram)(
|
| 71 |
|
|
m_core->o_ddr_reset_n,
|
| 72 |
|
|
m_core->o_ddr_cke,
|
| 73 |
|
|
m_core->o_ddr_cs_n,
|
| 74 |
|
|
m_core->o_ddr_ras_n,
|
| 75 |
|
|
m_core->o_ddr_cas_n,
|
| 76 |
|
|
m_core->o_ddr_we_n,
|
| 77 |
|
|
m_core->o_ddr_dqs,
|
| 78 |
|
|
m_core->o_ddr_dm,
|
| 79 |
|
|
m_core->o_ddr_odt,
|
| 80 |
|
|
m_core->o_ddr_bus_oe,
|
| 81 |
|
|
m_core->o_ddr_addr,
|
| 82 |
|
|
m_core->o_ddr_ba,
|
| 83 |
|
|
m_core->o_ddr_data);
|
| 84 |
|
|
|
| 85 |
6 |
dgisselq |
bool writeout = (!m_core->v__DOT__reset_override);
|
| 86 |
4 |
dgisselq |
|
| 87 |
6 |
dgisselq |
if (writeout) {
|
| 88 |
|
|
int cmd;
|
| 89 |
|
|
cmd = (m_core->o_ddr_reset_n?0:32)
|
| 90 |
|
|
|(m_core->o_ddr_cke?0:16)
|
| 91 |
|
|
|(m_core->o_ddr_cs_n?8:0)
|
| 92 |
|
|
|(m_core->o_ddr_ras_n?4:0)
|
| 93 |
|
|
|(m_core->o_ddr_cas_n?2:0)
|
| 94 |
|
|
|(m_core->o_ddr_we_n?1:0);
|
| 95 |
|
|
printf("%08lx-WB: %s/%s %s%s%s %s@0x%08x[%08x/%08x] -- ",
|
| 96 |
|
|
m_tickcount,
|
| 97 |
|
|
(m_core->i_wb_cyc)?"CYC":" ",
|
| 98 |
|
|
(m_core->i_wb_stb)?"STB":" ",
|
| 99 |
|
|
(m_core->o_wb_stall)?"STALL":" ",
|
| 100 |
|
|
(m_core->o_wb_ack)?"ACK":" ",
|
| 101 |
|
|
(m_core->o_cmd_accepted)?"BUS":" ",
|
| 102 |
|
|
(m_core->i_wb_we)?"W":"R",
|
| 103 |
|
|
(m_core->i_wb_addr),
|
| 104 |
|
|
(m_core->i_wb_data),
|
| 105 |
|
|
(m_core->o_wb_data));
|
| 106 |
4 |
dgisselq |
|
| 107 |
6 |
dgisselq |
printf("%s%s %d%d%d%d %s%s%s%s B[%d]@%04x %08x %08x",
|
| 108 |
|
|
(m_core->o_ddr_reset_n)?" ":"R",
|
| 109 |
|
|
(m_core->o_ddr_cke)?"CK":" ",
|
| 110 |
|
|
(m_core->o_ddr_cs_n),
|
| 111 |
|
|
(m_core->o_ddr_ras_n),
|
| 112 |
|
|
(m_core->o_ddr_cas_n),
|
| 113 |
|
|
(m_core->o_ddr_we_n),
|
| 114 |
|
|
//
|
| 115 |
|
|
(m_core->o_ddr_dqs)?"D":" ",
|
| 116 |
|
|
(m_core->o_ddr_dm)?"M":" ",
|
| 117 |
|
|
(m_core->o_ddr_odt)?"O":" ",
|
| 118 |
|
|
(m_core->o_ddr_bus_oe)?"E":" ",
|
| 119 |
|
|
//
|
| 120 |
|
|
(m_core->o_ddr_ba),
|
| 121 |
|
|
(m_core->o_ddr_addr),
|
| 122 |
|
|
(m_core->i_ddr_data),
|
| 123 |
|
|
(m_core->o_ddr_data));
|
| 124 |
4 |
dgisselq |
|
| 125 |
7 |
dgisselq |
printf(" FIFO[%x,%x](%d,%d,%08x-%08x-%08x)",
|
| 126 |
|
|
m_core->v__DOT__bus_fifo_head,
|
| 127 |
|
|
m_core->v__DOT__bus_fifo_tail,
|
| 128 |
|
|
m_core->v__DOT__bus_fifo_new[m_core->v__DOT__bus_fifo_tail],
|
| 129 |
|
|
m_core->v__DOT__bus_fifo_sub[m_core->v__DOT__bus_fifo_tail],
|
| 130 |
|
|
m_core->v__DOT__r_data,
|
| 131 |
|
|
m_core->v__DOT__bus_fifo_data[(m_core->v__DOT__bus_fifo_head-1)&15],
|
| 132 |
|
|
m_core->v__DOT__bus_fifo_data[m_core->v__DOT__bus_fifo_tail]);
|
| 133 |
|
|
|
| 134 |
|
|
printf(" BUS[%03x/%03x/%03x/%d]",
|
| 135 |
|
|
(m_core->v__DOT__bus_active),
|
| 136 |
|
|
(m_core->v__DOT__bus_read),
|
| 137 |
|
|
(m_core->v__DOT__bus_new),
|
| 138 |
|
|
(m_core->v__DOT__bus_subaddr[8]));
|
| 139 |
|
|
|
| 140 |
8 |
dgisselq |
/*
|
| 141 |
6 |
dgisselq |
// Reset logic
|
| 142 |
|
|
printf(" RST(%06x%s[%d] - %08x->%08x)",
|
| 143 |
|
|
m_core->v__DOT__reset_timer,
|
| 144 |
|
|
(m_core->v__DOT__reset_ztimer)?"Z":" ",
|
| 145 |
|
|
(m_core->v__DOT__reset_address),
|
| 146 |
|
|
(m_core->v__DOT__reset_instruction),
|
| 147 |
|
|
(m_core->v__DOT__reset_cmd));
|
| 148 |
8 |
dgisselq |
*/
|
| 149 |
4 |
dgisselq |
|
| 150 |
6 |
dgisselq |
printf(" %s%03x[%d]%04x:%d",
|
| 151 |
|
|
(m_core->v__DOT__r_pending)?"R":" ",
|
| 152 |
|
|
(m_core->v__DOT__r_row),
|
| 153 |
|
|
(m_core->v__DOT__r_bank),
|
| 154 |
|
|
(m_core->v__DOT__r_col),0);
|
| 155 |
|
|
// (m_core->v__DOT__r_sub));
|
| 156 |
|
|
printf(" %s%s%s",
|
| 157 |
7 |
dgisselq |
"B",
|
| 158 |
|
|
// (m_core->v__DOT__all_banks_closed)?"b":"B",
|
| 159 |
6 |
dgisselq |
(m_core->v__DOT__need_close_bank)?"C":"N",
|
| 160 |
|
|
//:(m_core->v__DOT__maybe_close_next_bank)?"c":"N",
|
| 161 |
|
|
(m_core->v__DOT__need_open_bank)?"O":"K");
|
| 162 |
|
|
// :(m_core->v__DOT__maybe_open_next_bank)?"o":"K");
|
| 163 |
|
|
for(int i=0; i<8; i++) {
|
| 164 |
7 |
dgisselq |
printf("%s%x@%x%s",
|
| 165 |
6 |
dgisselq |
(m_core->v__DOT__r_bank==i)?"R":"[",
|
| 166 |
|
|
m_core->v__DOT__bank_status[i],
|
| 167 |
|
|
m_core->v__DOT__bank_address[i],
|
| 168 |
|
|
(m_core->v__DOT__r_nxt_bank==i)?"N":"]");
|
| 169 |
|
|
}
|
| 170 |
|
|
|
| 171 |
4 |
dgisselq |
|
| 172 |
6 |
dgisselq |
extern int gbl_state, gbl_counts;
|
| 173 |
|
|
printf(" %2d:%08x ", gbl_state, gbl_counts);
|
| 174 |
|
|
|
| 175 |
7 |
dgisselq |
printf(" %s%s%s%s%s%s%s:%08x:%08x",
|
| 176 |
6 |
dgisselq |
(m_core->v__DOT__reset_override)?"R":" ",
|
| 177 |
|
|
(m_core->v__DOT__need_refresh)?"N":" ",
|
| 178 |
|
|
(m_core->v__DOT__need_close_bank)?"C":" ",
|
| 179 |
|
|
(m_core->v__DOT__need_open_bank)?"O":" ",
|
| 180 |
|
|
(m_core->v__DOT__valid_bank)?"V":" ",
|
| 181 |
7 |
dgisselq |
(m_core->v__DOT__r_move)?"R":" ",
|
| 182 |
|
|
(m_core->v__DOT__m_move)?"M":" ",
|
| 183 |
6 |
dgisselq |
m_core->v__DOT__activate_bank_cmd,
|
| 184 |
|
|
m_core->v__DOT__cmd);
|
| 185 |
|
|
|
| 186 |
7 |
dgisselq |
printf(" F%s%05x:%x/%s",
|
| 187 |
|
|
(m_core->v__DOT__refresh_ztimer)?"Z":" ",
|
| 188 |
|
|
m_core->v__DOT__refresh_counter,
|
| 189 |
|
|
m_core->v__DOT__refresh_addr,
|
| 190 |
|
|
(m_core->v__DOT__need_refresh)?"N":" ");
|
| 191 |
6 |
dgisselq |
|
| 192 |
|
|
if (m_core->v__DOT__reset_override)
|
| 193 |
|
|
printf(" OVERRIDE");
|
| 194 |
|
|
//if(m_core->v__DOT__last_open_bank)printf(" LST-OPEN");
|
| 195 |
|
|
switch(cmd) {
|
| 196 |
|
|
case DDR_MRSET: printf(" MRSET"); break;
|
| 197 |
|
|
case DDR_REFRESH: printf(" REFRESH"); break;
|
| 198 |
|
|
case DDR_PRECHARGE: printf(" PRECHARGE%s", (m_core->o_ddr_addr&0x400)?"-ALL":""); break;
|
| 199 |
|
|
case DDR_ACTIVATE: printf(" ACTIVATE"); break;
|
| 200 |
|
|
case DDR_WRITE: printf(" WRITE"); break;
|
| 201 |
|
|
case DDR_READ: printf(" READ"); break;
|
| 202 |
|
|
case DDR_ZQS: printf(" ZQS"); break;
|
| 203 |
|
|
case DDR_NOOP: printf(" NOOP"); break;
|
| 204 |
|
|
default: printf(" Unknown-CMD(%02x)", cmd); break;
|
| 205 |
|
|
}
|
| 206 |
|
|
|
| 207 |
|
|
// Decode the command
|
| 208 |
|
|
|
| 209 |
|
|
printf("\n");
|
| 210 |
|
|
}
|
| 211 |
|
|
|
| 212 |
4 |
dgisselq |
m_core->eval();
|
| 213 |
|
|
m_core->i_clk = 0;
|
| 214 |
|
|
m_core->eval();
|
| 215 |
|
|
|
| 216 |
|
|
m_tickcount++;
|
| 217 |
|
|
|
| 218 |
|
|
/*
|
| 219 |
|
|
if ((m_core->o_wb_ack)&&(!m_core->i_wb_cyc)) {
|
| 220 |
|
|
printf("SETTING ERR TO TRUE!!!!! ACK w/ no CYC\n");
|
| 221 |
|
|
// m_bomb = true;
|
| 222 |
|
|
}
|
| 223 |
|
|
*/
|
| 224 |
|
|
}
|
| 225 |
|
|
|
| 226 |
|
|
void reset(void) {
|
| 227 |
|
|
m_core->i_reset = 1;
|
| 228 |
|
|
m_core->i_wb_cyc = 0;
|
| 229 |
|
|
m_core->i_wb_stb = 0;
|
| 230 |
|
|
tick();
|
| 231 |
|
|
m_core->i_reset = 0;
|
| 232 |
|
|
}
|
| 233 |
|
|
|
| 234 |
|
|
void wb_tick(void) {
|
| 235 |
|
|
m_core->i_wb_cyc = 0;
|
| 236 |
|
|
m_core->i_wb_stb = 0;
|
| 237 |
|
|
tick();
|
| 238 |
|
|
}
|
| 239 |
|
|
|
| 240 |
|
|
unsigned wb_read(unsigned a) {
|
| 241 |
|
|
int errcount = 0;
|
| 242 |
|
|
unsigned result;
|
| 243 |
|
|
|
| 244 |
|
|
printf("WB-READ(%08x)\n", a);
|
| 245 |
|
|
|
| 246 |
|
|
m_core->i_wb_cyc = 1;
|
| 247 |
|
|
m_core->i_wb_stb = 1;
|
| 248 |
|
|
m_core->i_wb_we = 0;
|
| 249 |
|
|
m_core->i_wb_addr= a & SDRAMMASK;
|
| 250 |
|
|
|
| 251 |
|
|
if (m_core->o_wb_stall) {
|
| 252 |
|
|
while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall))
|
| 253 |
|
|
tick();
|
| 254 |
|
|
} else
|
| 255 |
|
|
tick();
|
| 256 |
|
|
|
| 257 |
|
|
m_core->i_wb_stb = 0;
|
| 258 |
|
|
|
| 259 |
|
|
while((errcount++ < BOMBCOUNT)&&(!m_core->o_wb_ack))
|
| 260 |
|
|
tick();
|
| 261 |
|
|
|
| 262 |
|
|
|
| 263 |
|
|
result = m_core->o_wb_data;
|
| 264 |
|
|
|
| 265 |
|
|
// Release the bus?
|
| 266 |
|
|
m_core->i_wb_cyc = 0;
|
| 267 |
|
|
m_core->i_wb_stb = 0;
|
| 268 |
|
|
|
| 269 |
|
|
if(errcount >= BOMBCOUNT) {
|
| 270 |
|
|
printf("SETTING ERR TO TRUE!!!!!\n");
|
| 271 |
|
|
m_bomb = true;
|
| 272 |
|
|
} else if (!m_core->o_wb_ack) {
|
| 273 |
|
|
printf("SETTING ERR TO TRUE--NO ACK, NO TIMEOUT\n");
|
| 274 |
|
|
m_bomb = true;
|
| 275 |
|
|
}
|
| 276 |
|
|
tick();
|
| 277 |
|
|
|
| 278 |
|
|
return result;
|
| 279 |
|
|
}
|
| 280 |
|
|
|
| 281 |
|
|
void wb_read(unsigned a, int len, unsigned *buf) {
|
| 282 |
|
|
int errcount = 0;
|
| 283 |
|
|
int THISBOMBCOUNT = BOMBCOUNT * len;
|
| 284 |
|
|
int cnt, rdidx, inc;
|
| 285 |
|
|
|
| 286 |
|
|
printf("WB-READ(%08x, %d)\n", a, len);
|
| 287 |
|
|
|
| 288 |
|
|
while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall))
|
| 289 |
|
|
wb_tick();
|
| 290 |
|
|
|
| 291 |
|
|
if (errcount >= BOMBCOUNT) {
|
| 292 |
|
|
m_bomb = true;
|
| 293 |
|
|
return;
|
| 294 |
|
|
}
|
| 295 |
|
|
|
| 296 |
|
|
errcount = 0;
|
| 297 |
|
|
|
| 298 |
|
|
m_core->i_wb_cyc = 1;
|
| 299 |
|
|
m_core->i_wb_stb = 1;
|
| 300 |
|
|
m_core->i_wb_we = 0;
|
| 301 |
|
|
m_core->i_wb_addr= a & SDRAMMASK;
|
| 302 |
|
|
|
| 303 |
|
|
rdidx =0; cnt = 0;
|
| 304 |
|
|
inc = 1;
|
| 305 |
|
|
|
| 306 |
|
|
do {
|
| 307 |
|
|
int s;
|
| 308 |
|
|
s = (m_core->o_wb_stall==0)?0:1;
|
| 309 |
|
|
tick();
|
| 310 |
|
|
if (!s)
|
| 311 |
|
|
m_core->i_wb_addr += inc;
|
| 312 |
|
|
cnt += (s==0)?1:0;
|
| 313 |
|
|
if (m_core->o_wb_ack)
|
| 314 |
|
|
buf[rdidx++] = m_core->o_wb_data;
|
| 315 |
|
|
} while((cnt < len)&&(errcount++ < THISBOMBCOUNT));
|
| 316 |
|
|
|
| 317 |
|
|
m_core->i_wb_stb = 0;
|
| 318 |
|
|
|
| 319 |
|
|
while((rdidx < len)&&(errcount++ < THISBOMBCOUNT)) {
|
| 320 |
|
|
tick();
|
| 321 |
|
|
if (m_core->o_wb_ack)
|
| 322 |
|
|
buf[rdidx++] = m_core->o_wb_data;
|
| 323 |
|
|
}
|
| 324 |
|
|
|
| 325 |
|
|
// Release the bus?
|
| 326 |
|
|
m_core->i_wb_cyc = 0;
|
| 327 |
|
|
|
| 328 |
|
|
if(errcount >= THISBOMBCOUNT) {
|
| 329 |
|
|
printf("SETTING ERR TO TRUE!!!!! (errcount=%08x, THISBOMBCOUNT=%08x)\n", errcount, THISBOMBCOUNT);
|
| 330 |
|
|
m_bomb = true;
|
| 331 |
|
|
} else if (!m_core->o_wb_ack) {
|
| 332 |
|
|
printf("SETTING ERR TO TRUE--NO ACK, NO TIMEOUT\n");
|
| 333 |
|
|
m_bomb = true;
|
| 334 |
|
|
}
|
| 335 |
|
|
tick();
|
| 336 |
|
|
}
|
| 337 |
|
|
|
| 338 |
|
|
void wb_write(unsigned a, unsigned int v) {
|
| 339 |
|
|
int errcount = 0;
|
| 340 |
|
|
|
| 341 |
|
|
printf("WB-WRITE(%08x) = %08x\n", a, v);
|
| 342 |
|
|
m_core->i_wb_cyc = 1;
|
| 343 |
|
|
m_core->i_wb_stb = 1;
|
| 344 |
|
|
m_core->i_wb_we = 1;
|
| 345 |
|
|
m_core->i_wb_addr= a & SDRAMMASK;
|
| 346 |
|
|
m_core->i_wb_data= v;
|
| 347 |
|
|
|
| 348 |
|
|
if (m_core->o_wb_stall)
|
| 349 |
|
|
while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall))
|
| 350 |
|
|
tick();
|
| 351 |
|
|
tick();
|
| 352 |
|
|
|
| 353 |
|
|
m_core->i_wb_stb = 0;
|
| 354 |
|
|
|
| 355 |
|
|
while((errcount++ < BOMBCOUNT)&&(!m_core->o_wb_ack))
|
| 356 |
|
|
tick();
|
| 357 |
|
|
|
| 358 |
|
|
// Release the bus?
|
| 359 |
|
|
m_core->i_wb_cyc = 0;
|
| 360 |
|
|
m_core->i_wb_stb = 0;
|
| 361 |
|
|
|
| 362 |
|
|
if(errcount >= BOMBCOUNT) {
|
| 363 |
|
|
printf("SETTING ERR TO TRUE!!!!!\n");
|
| 364 |
|
|
m_bomb = true;
|
| 365 |
|
|
} tick();
|
| 366 |
|
|
}
|
| 367 |
|
|
|
| 368 |
|
|
void wb_write(unsigned a, unsigned int ln, unsigned int *buf) {
|
| 369 |
|
|
unsigned errcount = 0, nacks = 0;
|
| 370 |
|
|
|
| 371 |
|
|
m_core->i_wb_cyc = 1;
|
| 372 |
|
|
m_core->i_wb_stb = 1;
|
| 373 |
|
|
for(unsigned stbcnt=0; stbcnt<ln; stbcnt++) {
|
| 374 |
|
|
m_core->i_wb_we = 1;
|
| 375 |
|
|
m_core->i_wb_addr= (a+stbcnt) & SDRAMMASK;
|
| 376 |
|
|
m_core->i_wb_data= buf[stbcnt];
|
| 377 |
|
|
errcount = 0;
|
| 378 |
|
|
|
| 379 |
|
|
while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall)) {
|
| 380 |
|
|
tick(); if (m_core->o_wb_ack) nacks++;
|
| 381 |
|
|
}
|
| 382 |
|
|
// Tick, now that we're not stalled. This is the tick
|
| 383 |
|
|
// that gets accepted.
|
| 384 |
|
|
tick(); if (m_core->o_wb_ack) nacks++;
|
| 385 |
|
|
}
|
| 386 |
|
|
|
| 387 |
|
|
m_core->i_wb_stb = 0;
|
| 388 |
|
|
|
| 389 |
|
|
errcount = 0;
|
| 390 |
|
|
while((nacks < ln)&&(errcount++ < BOMBCOUNT)) {
|
| 391 |
|
|
tick();
|
| 392 |
|
|
if (m_core->o_wb_ack) {
|
| 393 |
|
|
nacks++;
|
| 394 |
|
|
errcount = 0;
|
| 395 |
|
|
}
|
| 396 |
|
|
}
|
| 397 |
|
|
|
| 398 |
|
|
// Release the bus
|
| 399 |
|
|
m_core->i_wb_cyc = 0;
|
| 400 |
|
|
m_core->i_wb_stb = 0;
|
| 401 |
|
|
|
| 402 |
|
|
if(errcount >= BOMBCOUNT) {
|
| 403 |
|
|
printf("SETTING ERR TO TRUE!!!!!\n");
|
| 404 |
|
|
m_bomb = true;
|
| 405 |
|
|
} tick();
|
| 406 |
|
|
}
|
| 407 |
|
|
|
| 408 |
|
|
bool bombed(void) const { return m_bomb; }
|
| 409 |
|
|
|
| 410 |
|
|
};
|
| 411 |
|
|
|
| 412 |
|
|
void uload(unsigned len, unsigned *buf) {
|
| 413 |
|
|
FILE *fp = fopen("/dev/urandom", "r");
|
| 414 |
|
|
|
| 415 |
|
|
if ((NULL == fp)||(len != fread(buf, sizeof(unsigned), len, fp))) {
|
| 416 |
|
|
for(int i=0; i<(int)len; i++)
|
| 417 |
|
|
buf[i] = rand();
|
| 418 |
|
|
} if (NULL == fp)
|
| 419 |
|
|
fclose(fp);
|
| 420 |
|
|
}
|
| 421 |
|
|
|
| 422 |
|
|
int main(int argc, char **argv) {
|
| 423 |
|
|
Verilated::commandArgs(argc, argv);
|
| 424 |
|
|
DDRSDRAM_TB *tb = new DDRSDRAM_TB;
|
| 425 |
|
|
unsigned *rdbuf, *mbuf;
|
| 426 |
|
|
int nw = 3, nr = 13;
|
| 427 |
|
|
unsigned mlen = (1<<(LGMEMSIZE-2));
|
| 428 |
|
|
|
| 429 |
|
|
printf("Giving the core 140k cycles to start up\n");
|
| 430 |
|
|
// Before testing, let's give the unit time enough to warm up
|
| 431 |
|
|
tb->reset();
|
| 432 |
7 |
dgisselq |
for(int i=0; i<141195; i++)
|
| 433 |
4 |
dgisselq |
tb->wb_tick();
|
| 434 |
|
|
|
| 435 |
8 |
dgisselq |
// Let's short circuit the test, and only test *some* of the memory
|
| 436 |
|
|
// space. It'll probably be good enough, and it'll finish while I'm
|
| 437 |
|
|
// waiting ...
|
| 438 |
|
|
mlen = 1<<16;
|
| 439 |
|
|
|
| 440 |
4 |
dgisselq |
printf("Getting some memory ...\n");
|
| 441 |
|
|
rdbuf = new unsigned[mlen];
|
| 442 |
|
|
mbuf = new unsigned[mlen]; // Match buffer
|
| 443 |
|
|
printf("Charging my memory with random values\n");
|
| 444 |
|
|
uload(mlen, rdbuf);
|
| 445 |
|
|
|
| 446 |
|
|
// First test: singular reads through the memory, followed by
|
| 447 |
|
|
// singular writes
|
| 448 |
|
|
printf("Starting the single-read test\n");
|
| 449 |
|
|
for(int i=0; i<(int)mlen; i++) {
|
| 450 |
|
|
tb->wb_write(i, rdbuf[i]);
|
| 451 |
|
|
tb->wb_tick();
|
| 452 |
|
|
if ((*tb)[i] != rdbuf[i]) {
|
| 453 |
|
|
printf("WRITE[%06x] = %08x (Expecting %08x) FAILED\n",
|
| 454 |
|
|
i, (*tb)[i], rdbuf[i]);
|
| 455 |
|
|
goto test_failure;
|
| 456 |
|
|
} if (tb->bombed())
|
| 457 |
|
|
goto test_failure;
|
| 458 |
|
|
|
| 459 |
|
|
} for(int i=0; i<(int)mlen; i++) {
|
| 460 |
|
|
unsigned v;
|
| 461 |
|
|
if (rdbuf[i] != (v=tb->wb_read(i))) {
|
| 462 |
|
|
printf("READ[%06x] = %08x (Expecting %08x)\n",
|
| 463 |
|
|
i, v, rdbuf[i]);
|
| 464 |
|
|
goto test_failure;
|
| 465 |
|
|
} if (tb->bombed())
|
| 466 |
|
|
goto test_failure;
|
| 467 |
|
|
tb->wb_tick();
|
| 468 |
|
|
}
|
| 469 |
|
|
|
| 470 |
|
|
// Second test: Vector writes going through all memory, followed a
|
| 471 |
|
|
// massive vector read
|
| 472 |
|
|
uload(mlen, rdbuf); // Get some new values
|
| 473 |
|
|
tb->wb_write(0, mlen, rdbuf);
|
| 474 |
|
|
if (tb->bombed())
|
| 475 |
|
|
goto test_failure;
|
| 476 |
|
|
for(int i=0; i<(int)mlen; i++) {
|
| 477 |
|
|
unsigned v;
|
| 478 |
|
|
if (rdbuf[i] != (v=(*tb)[i])) {
|
| 479 |
|
|
printf("V-WRITE[%06x] = %08x (Expecting %08x)\n",
|
| 480 |
|
|
i, v, rdbuf[i]);
|
| 481 |
|
|
goto test_failure;
|
| 482 |
|
|
}
|
| 483 |
|
|
}
|
| 484 |
|
|
|
| 485 |
|
|
tb->wb_read( 0, mlen, mbuf);
|
| 486 |
|
|
if (tb->bombed())
|
| 487 |
|
|
goto test_failure;
|
| 488 |
|
|
for(int i=0; i<(int)mlen; i++) {
|
| 489 |
|
|
if (rdbuf[i] != mbuf[i]) {
|
| 490 |
|
|
printf("V-READ[%06x] = %08x (Expecting %08x)\n",
|
| 491 |
|
|
i, mbuf[i], rdbuf[i]);
|
| 492 |
|
|
goto test_failure;
|
| 493 |
|
|
}
|
| 494 |
|
|
}
|
| 495 |
|
|
|
| 496 |
8 |
dgisselq |
// Third test: Vector writes going through all memory, in prime numbers
|
| 497 |
4 |
dgisselq |
// of values at a time, followed by reads via a different prime number
|
| 498 |
8 |
dgisselq |
uload(mlen, rdbuf); // Get some new values
|
| 499 |
4 |
dgisselq |
for(int i=0; i<(int)mlen; i+=nw) {
|
| 500 |
|
|
int ln = ((int)mlen-i>nw)?nw:mlen-i;
|
| 501 |
|
|
tb->wb_write(i, nw, &rdbuf[i]);
|
| 502 |
|
|
for(int j=0; j<ln; j++) {
|
| 503 |
|
|
if ((*tb)[i+j] != rdbuf[i+j]) {
|
| 504 |
|
|
printf("P-WRITE[%06x] = %08x (Expecting %08x) FAILED\n",
|
| 505 |
|
|
i, (*tb)[i], rdbuf[i]);
|
| 506 |
|
|
goto test_failure;
|
| 507 |
|
|
}
|
| 508 |
|
|
} if (tb->bombed())
|
| 509 |
|
|
goto test_failure;
|
| 510 |
|
|
} for(int i=0; i<(int)mlen; i+=nr) {
|
| 511 |
|
|
int ln = ((int)mlen-i>nr)?nr:mlen-i;
|
| 512 |
8 |
dgisselq |
tb->wb_read(i, nr, &mbuf[i]);
|
| 513 |
4 |
dgisselq |
for(int j=0; j<ln; j++) {
|
| 514 |
|
|
if (mbuf[i+j] != rdbuf[i+j]) {
|
| 515 |
|
|
printf("P-READ[%06x] = %08x (Expecting %08x) FAILED\n",
|
| 516 |
|
|
i, mbuf[i], rdbuf[i]);
|
| 517 |
|
|
goto test_failure;
|
| 518 |
|
|
}
|
| 519 |
|
|
} if (tb->bombed())
|
| 520 |
|
|
goto test_failure;
|
| 521 |
|
|
}
|
| 522 |
|
|
|
| 523 |
8 |
dgisselq |
// Fourth test: Singular writes though all of memory, skipping by some
|
| 524 |
|
|
// prime address increment each time, followed by reads via a different
|
| 525 |
|
|
// prime numbered increment.
|
| 526 |
|
|
uload(mlen, rdbuf); // Get some new values
|
| 527 |
|
|
for(int i=0; i<(int)mlen; i++) {
|
| 528 |
|
|
int loc = (i*13)&0x3ffffff;
|
| 529 |
|
|
tb->wb_write(loc, rdbuf[loc]);
|
| 530 |
|
|
if ((*tb)[loc] != rdbuf[loc]) {
|
| 531 |
|
|
printf("R-WRITE[%06x] = %08x (Expecting %08x) FAILED\n",
|
| 532 |
|
|
i, (*tb)[loc], rdbuf[loc]);
|
| 533 |
|
|
goto test_failure;
|
| 534 |
|
|
} if (tb->bombed())
|
| 535 |
|
|
goto test_failure;
|
| 536 |
|
|
} for(int i=0; i<(int)mlen; i++) {
|
| 537 |
|
|
int loc = (i*19)&0x3ffffff;
|
| 538 |
|
|
mbuf[loc] = tb->wb_read(loc);
|
| 539 |
|
|
if (mbuf[loc] != rdbuf[loc]) {
|
| 540 |
|
|
printf("R-READ[%06x] = %08x (Expecting %08x) FAILED\n",
|
| 541 |
|
|
loc, mbuf[loc], rdbuf[loc]);
|
| 542 |
|
|
goto test_failure;
|
| 543 |
|
|
} if (tb->bombed())
|
| 544 |
|
|
goto test_failure;
|
| 545 |
|
|
}
|
| 546 |
4 |
dgisselq |
|
| 547 |
8 |
dgisselq |
|
| 548 |
4 |
dgisselq |
printf("SUCCESS!!\n");
|
| 549 |
|
|
exit(0);
|
| 550 |
|
|
test_failure:
|
| 551 |
|
|
printf("FAIL-HERE\n");
|
| 552 |
|
|
for(int i=0; i<64; i++)
|
| 553 |
|
|
tb->tick();
|
| 554 |
|
|
printf("TEST FAILED\n");
|
| 555 |
|
|
exit(-1);
|
| 556 |
|
|
}
|
