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%%

%% Filename:    spec.tex

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%% Project:     Wishbone to ICAPE2 interface conversion

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%% Purpose:     This LaTeX file contains all of the documentation/description

%%              currently provided with this FPGA Real-time Clock Core.

%%              It's not nearly as interesting as the PDF file it creates,

%%              so I'd recommend reading that before diving into this file.

%%              You should be able to find the PDF file in the SVN distribution

%%              together with this PDF file and a copy of the GPL-3.0 license

%%              this file is distributed under.  If not, just type 'make'

%%              in the doc directory and it (should) build without a problem.

%%

%%

%% Creator:     Dan Gisselquist

%%              Gisselquist Technology, LLC

%%

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%%

%% Copyright (C) 2015, Gisselquist Technology, LLC

%%

%% This program is free software (firmware): you can redistribute it and/or

%% modify it under the terms of  the GNU General Public License as published

%% by the Free Software Foundation, either version 3 of the License, or (at

%% your option) any later version.

%%

%% This program is distributed in the hope that it will be useful, but WITHOUT

%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

%% FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

%% for more details.

%%

%% You should have received a copy of the GNU General Public License along

%% with this program.  (It's in the $(ROOT)/doc directory, run make with no

%% target there if the PDF file isn't present.)  If not, see

%% <http://www.gnu.org/licenses/> for a copy.

%%

%% License:     GPL, v3, as defined and found on www.gnu.org,

%%              http://www.gnu.org/licenses/gpl.html

%%

%%

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\documentclass{gqtekspec}

\project{Real-Time Clock}

\title{Specification}

\author{Dan Gisselquist, Ph.D.}

\email{dgisselq\at opencores.org}

\revision{Rev.~0.1}

\begin{document}

\pagestyle{gqtekspecplain}

\titlepage

\begin{license}

Copyright (C) \theyear\today, Gisselquist Technology, LLC

This project is free software (firmware): you can redistribute it and/or

modify it under the terms of  the GNU General Public License as published

by the Free Software Foundation, either version 3 of the License, or (at

your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT

ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

for more details.

You should have received a copy of the GNU General Public License along

with this program.  If not, see \hbox{<http://www.gnu.org/licenses/>} for a

copy.

\end{license}

\begin{revisionhistory}

0.1 & 5/25/2015 & Gisselquist & First Draft \\\hline

\end{revisionhistory}

% Revision History

% Table of Contents, named Contents

\tableofcontents

% \listoffigures

\listoftables

\begin{preface}

My thanks to those helpers on the Xilinx Forum who helped me get the final

step to getting this working.

\end{preface}

\chapter{Introduction}

\pagenumbering{arabic}

\setcounter{page}{1}

This core makes the ICAPE2 FPGA configuration registers available to be read

or written from a wishbone bus.  As the documentation of this capability could

use a bit to be desired, I have put this file together to help document

what works.

The interface itself is very valuable for a couple of purposes---from my humble

and personal perspective.  The first is the user configurable watchdog timer

which can be used to automatically reset an FPGA after it locks up.  The second

is the warm boot start capability, which makes it possible to create a fall

back configuration image and test it without compromising the ability of the

FPGA to be started in a known good image.  The third valuable capability is that

of commanding a reconfiguration.  All of these capabilities are available

through this interface.  Further details are available from Xilinx's "7-Series

FPGAs Configuration" User Guide.

This introduction is the first chapter.  Beyond this introduction, most

of the capabilities are documented elsewhere.  Hence, the register chapter

will be omitted and the reader will be gently pointed to the User's Guide.

This leaves the Wishbone chapter and the I/O Port's chapter which follow.

As always, write me if you have any questions or problems.

\chapter{Architecture}\label{chap:arch}

If I understand correctly, every one of Xilinx's 7--Series FPGA's contains

two ICAPE2 interface modules.  These modules allow user logic to communicate

with the configuration interface of the chip.  This interface, however, isn't

well documented.  According to the User's Guide, it matches the SelectMAP

interface, yet in practice \ldots it doesn't.

This core encapsulates the difficulty of matching that interface.  Register

addresses match those in the User's Guide, as do register definitions.

\chapter{Operation}\label{chap:ops}

Consider the warm boot reload operation.  To do this, write the address in

configuration memory of an FPGA image to the warm boot start address (WBSTAR).

In this case, that is address 5'h10 within this interface.  A second write to

the configuration command address (CMD), 5'h4 in this interface, will issue the

IPROG command to the FPGA and cause it to configure itself from the address

you just gave it.

There, wasn't that simple?

Now I can, from the comfort of my home, reconfigure an FPGA in my office without

needing to press the power button or connect to a JTAG cable.  Not bad, no?

\chapter{Wishbone Datasheet}\label{chap:wishbone}

Tbl.~\ref{tbl:wishbone}

\begin{table}[htbp]

\begin{center}

\begin{wishboneds}

Revision level of wishbone & WB B4 spec \\\hline

Type of interface & Slave, Read/Write \\\hline

Port size & 32--bit \\\hline

Port granularity & 32--bit \\\hline

Maximum Operand Size & 32--bit \\\hline

Data transfer ordering & (Irrelevant) \\\hline

Clock constraints & See the Datasheet for your part\\\hline

Signal Names & \begin{tabular}{ll}

                Signal Name & Wishbone Equivalent \\\hline

                {\tt i\_clk} & {\tt CLK\_I} \\

                {\tt i\_wb\_cyc} & {\tt CYC\_I} \\

                {\tt i\_wb\_stb} & {\tt STB\_I} \\

                {\tt i\_wb\_we} & {\tt WE\_I} \\

                {\tt i\_wb\_addr} & {\tt ADR\_I} \\

                {\tt i\_wb\_data} & {\tt DAT\_I} \\

                {\tt o\_wb\_ack} & {\tt ACK\_O} \\

                {\tt o\_wb\_stall} & {\tt STALL\_O} \\

                {\tt o\_wb\_data} & {\tt DAT\_O}

                \end{tabular}\\\hline

\end{wishboneds}

\caption{Wishbone Datasheet}\label{tbl:wishbone}

\end{center}\end{table}

is required by the wishbone specification, and so

it is included here.  The big thing to notice is that this ICAPE2 interface

acts as a wishbone slave, and that all accesses to the ICAPE2 registers become

32--bit reads and writes to this interface.  Bit ordering is the normal

ordering where bit~31 is the most significant bit and so forth.  (Bit reversal

is accomplished internally to match Xilinx's definition.)  The {\tt o\_stall}

and {\tt o\_ack} lines are necessarily used to deal with the fact that

operations to the device take many clocks to complete (14 for writes, 21 for

reads), so be prepared to wait a couple of clocks for your access to complete.

Further, the {\tt o\_ack} line will go high while the bus is stalled in many

cases, indicating that the operation is complete but that the core is not

yet ready to handle a subsequent request.

\chapter{I/O Ports}\label{chap:ioports}

This core offers no I/O ports beyond those of the wishbone discussed in

Chapt.~\ref{chap:wishbone}.  The I/O ports associated with the ICAPE2 interface

are captured internally, and not brought to the output of this core.

% Appendices

% Index

\end{document}