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[/] [wbicapetwo/] [trunk/] [rtl/] [wbicapesimple.v] - Blame information for rev 4

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1 4 dgisselq
///////////////////////////////////////////////////////////////////////////
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//
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// Filename:    wbicapesimple.v
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//
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// Project:     Wishbone to ICAPE_SPARTAN6 interface conversion
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//
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// Purpose:     This is a companion project to the ICAPE2 conversion, instead
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//              involving a conversion from a 32-bit WISHBONE bus to read
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//      and write the ICAPE_SPARTAN6 program.  Since this is a simple interface
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//      only, the smarts have been stripped out of it.  Therefore, if you wish
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//      to write to or read from particular registers, you will need to do all
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//      the sequencing yourself.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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module  wbicapesimple(i_clk,
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                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
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                        o_wb_ack, o_wb_stall, o_wb_data, icap_dbg);
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        input                   i_clk;
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        // Wishbone inputs
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        input                   i_wb_cyc, i_wb_stb, i_wb_we;
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        input           [15:0]   i_wb_data;
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        // Wishbone outputs
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        output  reg             o_wb_ack;
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        output  wire            o_wb_stall;
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        output  reg     [15:0]   o_wb_data;
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        output  wire    [25:0]   icap_dbg;
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        // Divide our clock by 8.  Thus, a 100 MHz clock with a 10 ns period
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        // gets divided down to an 80 ns period, which is greater than the 
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        // minimum 50 ns as per the data sheet.
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        reg     [2:0]    clk_divider;
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        initial clk_divider=0;
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        always @(posedge i_clk)
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                clk_divider <= clk_divider + 3'h1;
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        reg     icap_posedge, icap_preedge;
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        initial icap_posedge = 0;
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        always @(posedge i_clk)
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                icap_posedge <= (clk_divider == 3'b011);
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        initial icap_preedge = 0;
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        always @(posedge i_clk)
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                icap_preedge <= (clk_divider == 3'b010);
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                // icap_posedge <= (&clk_divider);
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        wire    icap_clk;
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        assign  icap_clk = clk_divider[2];
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        reg             icap_ce_n, icap_we_n;
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        reg     [15:0]   icap_data_i;
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        wire            icap_busy;
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        wire    [15:0]   icap_data_o;
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        ICAP_SPARTAN6   icap_inst(
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                .BUSY(icap_busy), // Active high, low during all writes
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                .O(icap_data_o),
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                .CE(icap_ce_n),
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                .CLK(icap_clk),
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                .I(icap_data_i),
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                .WRITE(icap_we_n));
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        // assign       o_wb_stall = (i_wb_cyc)&&((~icap_posedge)||((~icap_ce_n)&&(icap_busy)));
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        wire    [15:0]   brev_i_wb_data;
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        assign  brev_i_wb_data[ 0] = i_wb_data[ 7];
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        assign  brev_i_wb_data[ 1] = i_wb_data[ 6];
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        assign  brev_i_wb_data[ 2] = i_wb_data[ 5];
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        assign  brev_i_wb_data[ 3] = i_wb_data[ 4];
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        assign  brev_i_wb_data[ 4] = i_wb_data[ 3];
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        assign  brev_i_wb_data[ 5] = i_wb_data[ 2];
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        assign  brev_i_wb_data[ 6] = i_wb_data[ 1];
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        assign  brev_i_wb_data[ 7] = i_wb_data[ 0];
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        //
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        assign  brev_i_wb_data[ 8] = i_wb_data[15];
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        assign  brev_i_wb_data[ 9] = i_wb_data[14];
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        assign  brev_i_wb_data[10] = i_wb_data[13];
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        assign  brev_i_wb_data[11] = i_wb_data[12];
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        assign  brev_i_wb_data[12] = i_wb_data[11];
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        assign  brev_i_wb_data[13] = i_wb_data[10];
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        assign  brev_i_wb_data[14] = i_wb_data[ 9];
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        assign  brev_i_wb_data[15] = i_wb_data[ 8];
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        //
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        initial icap_data_i = 0;
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        always @(posedge i_clk)
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                if (icap_preedge)
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                begin
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                        if (~i_wb_cyc)
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                                icap_data_i <= 16'hffff;
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                        else if ((icap_ce_n)||(~icap_busy))
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                                icap_data_i <= brev_i_wb_data[15:0];
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                end
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        initial icap_we_n = 1'b1;
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        always @(posedge i_clk)
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                if ((icap_preedge)&&((icap_ce_n)||(~icap_busy)))
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                        icap_we_n <= ~i_wb_we;
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        initial icap_ce_n = 1'b1;
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        always @(posedge i_clk)
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                if ((icap_preedge)&&((icap_ce_n)||(~icap_busy)))
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                        icap_ce_n <= ~((i_wb_cyc)&&(i_wb_stb));
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                else if ((icap_preedge)&&(~i_wb_cyc))
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                        icap_ce_n <= 1'b1;
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        //initial       r_wb_stall = 1'b0;
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        //always @(posedge i_clk)
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                //r_wb_stall <= (~icap_posedge)&&(
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                                        //&&(icap_preedge)&&(~icap_busy));
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        // assign       o_wb_stall = (i_wb_cyc)&&((~icap_posedge)||((~icap_ce_n)&&(icap_busy)));
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        assign  o_wb_stall = (~icap_posedge)
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                                ||((i_wb_cyc)&&(~icap_ce_n)&&(icap_busy));
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        initial o_wb_ack = 1'b0;
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        always @(posedge i_clk)
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                o_wb_ack <= ((~icap_ce_n)&&(i_wb_cyc)
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                                        &&(icap_preedge)&&(~icap_busy));
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        wire    [15:0]   brev_icap_data;
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        assign  brev_icap_data[ 0] = icap_data_o[ 7];
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        assign  brev_icap_data[ 1] = icap_data_o[ 6];
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        assign  brev_icap_data[ 2] = icap_data_o[ 5];
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        assign  brev_icap_data[ 3] = icap_data_o[ 4];
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        assign  brev_icap_data[ 4] = icap_data_o[ 3];
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        assign  brev_icap_data[ 5] = icap_data_o[ 2];
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        assign  brev_icap_data[ 6] = icap_data_o[ 1];
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        assign  brev_icap_data[ 7] = icap_data_o[ 0];
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        //
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        assign  brev_icap_data[ 8] = icap_data_o[15];
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        assign  brev_icap_data[ 9] = icap_data_o[14];
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        assign  brev_icap_data[10] = icap_data_o[13];
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        assign  brev_icap_data[11] = icap_data_o[12];
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        assign  brev_icap_data[12] = icap_data_o[11];
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        assign  brev_icap_data[13] = icap_data_o[10];
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        assign  brev_icap_data[14] = icap_data_o[ 9];
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        assign  brev_icap_data[15] = icap_data_o[ 8];
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        //
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        initial o_wb_data = 16'h000;
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        always @(posedge i_clk)
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                if ((icap_posedge)&&((icap_ce_n)||(~icap_busy)))
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                        o_wb_data <= brev_icap_data;
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        assign  icap_dbg[25:0] = {
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                        i_wb_cyc,i_wb_stb, i_wb_we, o_wb_ack, o_wb_stall,
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                        icap_posedge, icap_clk, icap_ce_n, icap_busy, icap_we_n,
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                        (icap_we_n)?icap_data_o : icap_data_i };
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endmodule
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